This document describes the design of a Parallel Self-Timed Adder (PASTA). PASTA is an asynchronous adder circuit that operates in parallel for bits that do not require carry propagation. It uses half adders and multiplexers in a regular structure with minimal interconnections. The document discusses the architecture and operation of PASTA through state diagrams. It also reviews related work on asynchronous and synchronous adder designs. Simulation results using MICROWIND and DSCH tools in 45nm CMOS technology verify the performance advantages of PASTA over existing asynchronous adders in terms of area, power, delay.
This document discusses task scheduling on adaptive multi-core architectures. It begins by introducing instruction-level parallelism (ILP) and thread-level parallelism (TLP). It then discusses different multi-core architectures like symmetric, asymmetric, and adaptive multi-cores which can seamlessly exploit both ILP and TLP. It presents the Bahurupi adaptive multi-core architecture and describes an optimal task scheduling algorithm to minimize makespan. Experimental results show that adaptive architectures outperform static symmetric and asymmetric architectures for mixed workloads.
This document describes a proposed modification to the carry select adder (CSLA) circuit to reduce its area and power consumption. Specifically, it replaces the ripple carry adder with a carry input of 1 with a binary to excess-1 converter (BEC) in the CSLA. This modification is analyzed through logic effort methodology and custom layout simulations in a 0.18um CMOS process. The results show the modified CSLA design reduces area by 113 gates compared to the regular CSLA, with only an 11 gate delay increase. Overall, the proposed BEC-based modification achieves lower area and power for the CSLA.
This document presents a design for a simple accuracy reconfigurable adder (SARA) to improve the accuracy-power-delay efficiency of approximate adders. SARA is proposed as an alternative to existing accuracy configurable adders that require large areas due to redundancy and error correction circuitry. SARA uses a simple carry prediction approach without redundancy. It is evaluated as part of a 16-bit adder and shown to reduce delay compared to a ripple carry adder. SARA is also applied in an 8x8 Wallace multiplier, demonstrating reduced delay compared to using a ripple carry adder. The proposed SARA design achieves improvements in area, power, and delay efficiency for approximate arithmetic circuits.
IRJET - A Speculative Approximate Adder for Error Recovery UnitIRJET Journal
This document presents a speculative approximate adder for error recovery. The adder is partitioned into non-overlapping blocks whose carries are predicted based on input signals of the current and next blocks. This reduces the critical path delay on average to one block. An error recovery unit is also proposed to further reduce output error rates. Simulation results show the proposed adder achieves lower error rates and error metrics compared to state-of-the-art approximate adders, with only a small increase in delay and area due to the error recovery unit.
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...IRJET Journal
The document reviews recent progress in approximate adders for energy-efficient digital signal processing. It summarizes various types of approximate adders that have been proposed, including speculative adders, segmented adders, carry select adders, and adders using approximate full adders. The document provides details on the design and operation of several specific approximate adder circuits. It also compares the delay and area complexity of different approximate adder designs.
A multi objective hybrid aco-pso optimization algorithm for virtual machine p...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IRJET- Comparison of Multiplier Design with Various Full AddersIRJET Journal
This document compares the design of 4x4 array and Wallace tree multipliers using different full adders. It analyzes the power consumption, area, and delay of multipliers built with conventional, transmission function, transistor-based, and hybrid (12-transistor) full adders. Simulation results show the hybrid full adder achieves the lowest power consumption of 0.8946mW for the Wallace tree multiplier, demonstrating its benefit for building low power multipliers. In conclusion, replacing existing full adders in multipliers with the proposed hybrid full adder reduces area, power consumption, and transient time.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
This document discusses task scheduling on adaptive multi-core architectures. It begins by introducing instruction-level parallelism (ILP) and thread-level parallelism (TLP). It then discusses different multi-core architectures like symmetric, asymmetric, and adaptive multi-cores which can seamlessly exploit both ILP and TLP. It presents the Bahurupi adaptive multi-core architecture and describes an optimal task scheduling algorithm to minimize makespan. Experimental results show that adaptive architectures outperform static symmetric and asymmetric architectures for mixed workloads.
This document describes a proposed modification to the carry select adder (CSLA) circuit to reduce its area and power consumption. Specifically, it replaces the ripple carry adder with a carry input of 1 with a binary to excess-1 converter (BEC) in the CSLA. This modification is analyzed through logic effort methodology and custom layout simulations in a 0.18um CMOS process. The results show the modified CSLA design reduces area by 113 gates compared to the regular CSLA, with only an 11 gate delay increase. Overall, the proposed BEC-based modification achieves lower area and power for the CSLA.
This document presents a design for a simple accuracy reconfigurable adder (SARA) to improve the accuracy-power-delay efficiency of approximate adders. SARA is proposed as an alternative to existing accuracy configurable adders that require large areas due to redundancy and error correction circuitry. SARA uses a simple carry prediction approach without redundancy. It is evaluated as part of a 16-bit adder and shown to reduce delay compared to a ripple carry adder. SARA is also applied in an 8x8 Wallace multiplier, demonstrating reduced delay compared to using a ripple carry adder. The proposed SARA design achieves improvements in area, power, and delay efficiency for approximate arithmetic circuits.
IRJET - A Speculative Approximate Adder for Error Recovery UnitIRJET Journal
This document presents a speculative approximate adder for error recovery. The adder is partitioned into non-overlapping blocks whose carries are predicted based on input signals of the current and next blocks. This reduces the critical path delay on average to one block. An error recovery unit is also proposed to further reduce output error rates. Simulation results show the proposed adder achieves lower error rates and error metrics compared to state-of-the-art approximate adders, with only a small increase in delay and area due to the error recovery unit.
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...IRJET Journal
The document reviews recent progress in approximate adders for energy-efficient digital signal processing. It summarizes various types of approximate adders that have been proposed, including speculative adders, segmented adders, carry select adders, and adders using approximate full adders. The document provides details on the design and operation of several specific approximate adder circuits. It also compares the delay and area complexity of different approximate adder designs.
A multi objective hybrid aco-pso optimization algorithm for virtual machine p...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IRJET- Comparison of Multiplier Design with Various Full AddersIRJET Journal
This document compares the design of 4x4 array and Wallace tree multipliers using different full adders. It analyzes the power consumption, area, and delay of multipliers built with conventional, transmission function, transistor-based, and hybrid (12-transistor) full adders. Simulation results show the hybrid full adder achieves the lowest power consumption of 0.8946mW for the Wallace tree multiplier, demonstrating its benefit for building low power multipliers. In conclusion, replacing existing full adders in multipliers with the proposed hybrid full adder reduces area, power consumption, and transient time.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low power test pattern generation for bist applicationseSAT Journals
Abstract This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length. Keywords—Built-in self-test (BIST), low power, single-input change (SIC), test pattern generator (TPG)
A Modified Design of Test Pattern Generator for Built-In-Self- Test ApplicationsIJERA Editor
Test Pattern Generators (TPG) are very important logic part of the Circuits that have self-test features.
Nowadays, the self-test feature is an in-built part of the modern application hardware designs. This feature
enables the user to test and verify the specific hardware failure with the help of the hardware itself. To enable
self-test an extra operational and control circuit is required by the application based operational and control
circuit. The size of the self-test block is generally small as compared to the actual hardware. Most of the self-test
hardware includes Linear Feedback Shift Register (LFSR) to generate the test signal pattern in the self-test mode
of circuit operation. In the present work a simple 3-FF based modified design of TPG is designed and simulated
to generate a 4-bit test signal sequence. The present work also shows FPGA based simulation and synthesis of a
16-bit TPG design using the 4-bit TPG. The present TPG design concept can be replicated to generate a test
sequence of higher bit length for advanced applications. The present design is simulated on Xilinx tool for
functional verification.
32 bit×32 bit multiprecision razor based dynamicMastan Masthan
This document summarizes a research paper that presents a reconfigurable multiplier circuit that can dynamically adjust its precision, voltage, and frequency to minimize power consumption based on workload. It incorporates multiple smaller precision multipliers that can operate independently or in parallel. Razor flip-flops and dynamic voltage scaling are used to aggressively lower the voltage while ensuring correctness. Experimental results showed the design achieved up to 86.3% power reduction with only 11.1% area overhead compared to a fixed-width multiplier.
Performance Evaluation of Various CMOS Full Adder Designs: A ReviewIRJET Journal
This document reviews various CMOS full adder designs that have been proposed by researchers. It begins with an introduction on the importance of full adders in VLSI systems and the need to optimize parameters like power, speed and area. It then summarizes 11 research papers on different full adder circuit designs including 8T, 10T and novel multiplexer-based designs. Simulation results comparing power consumption, propagation delay and power-delay product of the proposed adders with traditional designs are discussed. The document concludes that full adder choice depends on the application requirements and optimized designs can improve overall system performance.
Compare "Urdhva Tiryakbhyam Multiplier" and "Hierarchical Array of Array Mul...ijsrd.com
Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. The need of high speed multiplier is increasing as the need of high speed processors are increasing. In this project, comparative study of different multipliers is done for high speed. The project includes two 4x4 bit Vedic Multiplier (VM) "Urdhva Tiryakbhyam multiplier" and "Hierarchical Array of Array Multiplier" of Ancient Indian Vedic Mathematics which are compared in terms of their speed. Urdhva Tiryakbhyam sutra increases the speed of multiplier by reducing the number of iterations then Hierarchical Array of Array Multiplier.
A Novel Approach to GSA, GA and Wavelet Transform to Design Fuzzy Logic Contr...IAES-IJPEDS
This paper proposes a novel approach for obtaining a closed loop control
scheme based on Fuzzy Logic Controller to regulate the output voltage
waveform of multilevel inverter. Fuzzy Logic Controller is used to guide and
control the inverter to synthesize a stepped output voltage waveform with
reduced harmonics. In this paper, three different intelligent soft-computing
methods are used to design a fuzzy system to be used as a closed loop control
system for regulating the inverter output. Gravitational Search Algorithm
and Genetic Algorithm are used as optimization methods to evaluate
switching angles for different combination of input voltages applied to MLI.
Wavelet Transform is used as synthesizing technique to shape stepped output
waveform of inverter using orthogonal wavelet sets. The proposed FLC
controlled method is carried out for a wider range of input dc voltages by
considering ±10% variations in nominal voltage value. A 7-level inverter is
used to validate the results of proposed control methods. The three proposed
methods are then compared in terms of various parameters like
computational time, switching angles and THD to justify the performance
and system flexibility. Finally, hardware based results are also obtained to
verify the viability of the proposed method.
Design and implementation a prototype system for fusion image by using SWT-PC...IJECEIAES
The technology of fusion image is dominance strongly over domain research for recent years, the techniques of fusion have various applications in real time used and proposed such as purpose of military and remote sensing etc., the fusion image is very efficient in processing of digital image. Single image produced from two images or more information of relevant combining process results from multi sensor fusion image. FPGA is the best implementation types of most technology enabling wide spread.This device works with modern versions for different critical characteristics same huge number of elements logic in order to permit complex algorithm implemented. In this paper,filters are designed and implemented in FPGA utilized for disease specified detection from images CT/MRI scanned where the samples are taken for human's brain with various medical images and the processing of fusion employed by using technique Stationary Wavelet Transform and Principal Component Analysis (SWT-PCA). Accuracy image output increases when implemented this technique and that was done by sampling down eliminating where effects blurring and artifacts doesn't influenced. The algorithm of SWT-PCA parameters quality measurements like NCC, MSE, PSNR, coefficients and Eigen values.The advantages significant of this system that provide real time, time rapid to market and portability beside the change parametric continuing in the DWT transform. The designed and simulation of module proposed system has been done by using MATLAB simulink and blocks generator system, Xilinx synthesized with synthesis tool (XST) and implemented in XilinxSpartan 6-SP605 device.
This document presents a GPU-accelerated algorithm for solving the Group Steiner Problem (GSP) which arises in routing phases of VLSI circuit design. The algorithm uses a depth-bounded heuristic to construct approximate minimum-cost Steiner trees in parallel using CUDA-aware MPI. Evaluation on a supercomputer shows the parallel implementation achieves up to 302x speedup over serial algorithms and scales well with problem size and processor count.
Co-Simulation Interfacing Capabilities in Device-Level Power Electronic Circu...IJPEDS-IAES
Power electronic circuit simulation today has become increasingly more demanding in both
the speed and accuracy. Whilst almost every simulator has its own advantages and disadvantages,
co-simulations are becoming more prevalent. This paper provides an overview of
the co-simulation capabilities of device-level circuit simulators. More specifically, a listing
of device-level simulators with their salient features are compared and contrasted. The
co-simulation interfaces between several simulation tools are discussed. A case study is
presented to demonstrate the co-simulation between a device-level simulator (PSIM) interfacing
a system-level simulator (Simulink), and a finite element simulation tool (FLUX).
Results demonstrate the necessity and convenience as well as the drawbacks of such a comprehensive
simulation.
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGAVLSICS Design
Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.
Low Power Clock Distribution Schemes in VLSI DesignIJERA Editor
This paper reviewed the comparison between different clock distribution schemes which used for low power
VLSI design which are the most important aspect in the industry. The main clock distribution schemes are
single driver clock scheme and distributed buffers clock scheme. There are different tradeoffs in both the
techniques such as size of buffers, number of buffers etc.
Presented approaches for generation of multiple clock gating domain parameterized PVT independent power abstracts for large IP blocks. We accomplish the gating domain parameterization through separation of the attribution of switching due to each single domain through a marking and tracing process, thereby precluding the need for separate domain by domain simulation to achieve the parameterization.
Experimental results comparing proposed approach on IP blocks of varying sizes from a real industry strength microprocessor design clearly highlight accuracy impact while keeping run time and model size increase in an acceptable range. In terms of extensions, we are exploring approaches where we could preserve each of the domains independently, for which we are looking into formulations based on constructing clock gating domain conflict hyper graphs and coloring them to determine domain interactions.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An fpga implementation of the lms adaptive filter eSAT Journals
This document describes an FPGA implementation of the Least Mean Square (LMS) adaptive filter algorithm for active vibration control. It compares fixed-point and floating-point implementations in terms of area usage and performance. The LMS algorithm is implemented using a finite state machine model with separate modules for operations like filtering, error estimation, and weight adaptation. Both implementations utilize this structural model. The fixed-point version uses 16-bit integers and fractions, while the floating-point version leverages IP cores. Results show the floating-point implementation has better accuracy and resource utilization than the fixed-point version for active vibration control applications on FPGAs.
The proposed Vedic multiplier is based on traditional Vedic Sutras multiplication techniques that were used to multiply numbers in the decimal system. It uses the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" to multiply two numbers faster and with less area than other multipliers like booth and array multipliers. The Vedic multiplier proves to be highly efficient for applications like digital signal processing in terms of both speed and smaller area compared to other designs.
Parallel implementation of pulse compression method on a multi-core digital ...IJECEIAES
Pulse compression algorithm is widely used in radar applications. It requires a huge processing power in order to be executed in real time. Therefore, its processing must be distributed along multiple processing units. The present paper proposes a real time platform based on the multi-core digital signal processor (DSP) C6678 from Texas Instruments (TI). The objective of this paper is the optimization of the parallel implementation of pulse compression algorithm over the eight cores of the C6678 DSP. Two parallelization approaches were implemented. The first approach is based on the open multi processing (OpenMP) programming interface, which is a software interface that helps to execute different sections of a program on a multi core processor. The second approach is an optimized method that we have proposed in order to distribute the processing and to synchronize the eight cores of the C6678 DSP. The proposed method gives the best performance. Indeed, a parallel efficiency of 94% was obtained when the eight cores were activated.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
Implementation of Carry Skip Adder using PTLIRJET Journal
The document proposes a design and implementation of a carry skip adder using pass transistor logic to improve performance over a conventional carry skip adder. It describes the structures of a conventional carry skip adder and the proposed pass transistor logic carry skip adder. Simulation results show that the proposed design reduces the number of transistors, area, delay, and average power compared to the conventional carry skip adder.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low power test pattern generation for bist applicationseSAT Journals
Abstract This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length. Keywords—Built-in self-test (BIST), low power, single-input change (SIC), test pattern generator (TPG)
A Modified Design of Test Pattern Generator for Built-In-Self- Test ApplicationsIJERA Editor
Test Pattern Generators (TPG) are very important logic part of the Circuits that have self-test features.
Nowadays, the self-test feature is an in-built part of the modern application hardware designs. This feature
enables the user to test and verify the specific hardware failure with the help of the hardware itself. To enable
self-test an extra operational and control circuit is required by the application based operational and control
circuit. The size of the self-test block is generally small as compared to the actual hardware. Most of the self-test
hardware includes Linear Feedback Shift Register (LFSR) to generate the test signal pattern in the self-test mode
of circuit operation. In the present work a simple 3-FF based modified design of TPG is designed and simulated
to generate a 4-bit test signal sequence. The present work also shows FPGA based simulation and synthesis of a
16-bit TPG design using the 4-bit TPG. The present TPG design concept can be replicated to generate a test
sequence of higher bit length for advanced applications. The present design is simulated on Xilinx tool for
functional verification.
32 bit×32 bit multiprecision razor based dynamicMastan Masthan
This document summarizes a research paper that presents a reconfigurable multiplier circuit that can dynamically adjust its precision, voltage, and frequency to minimize power consumption based on workload. It incorporates multiple smaller precision multipliers that can operate independently or in parallel. Razor flip-flops and dynamic voltage scaling are used to aggressively lower the voltage while ensuring correctness. Experimental results showed the design achieved up to 86.3% power reduction with only 11.1% area overhead compared to a fixed-width multiplier.
Performance Evaluation of Various CMOS Full Adder Designs: A ReviewIRJET Journal
This document reviews various CMOS full adder designs that have been proposed by researchers. It begins with an introduction on the importance of full adders in VLSI systems and the need to optimize parameters like power, speed and area. It then summarizes 11 research papers on different full adder circuit designs including 8T, 10T and novel multiplexer-based designs. Simulation results comparing power consumption, propagation delay and power-delay product of the proposed adders with traditional designs are discussed. The document concludes that full adder choice depends on the application requirements and optimized designs can improve overall system performance.
Compare "Urdhva Tiryakbhyam Multiplier" and "Hierarchical Array of Array Mul...ijsrd.com
Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. The need of high speed multiplier is increasing as the need of high speed processors are increasing. In this project, comparative study of different multipliers is done for high speed. The project includes two 4x4 bit Vedic Multiplier (VM) "Urdhva Tiryakbhyam multiplier" and "Hierarchical Array of Array Multiplier" of Ancient Indian Vedic Mathematics which are compared in terms of their speed. Urdhva Tiryakbhyam sutra increases the speed of multiplier by reducing the number of iterations then Hierarchical Array of Array Multiplier.
A Novel Approach to GSA, GA and Wavelet Transform to Design Fuzzy Logic Contr...IAES-IJPEDS
This paper proposes a novel approach for obtaining a closed loop control
scheme based on Fuzzy Logic Controller to regulate the output voltage
waveform of multilevel inverter. Fuzzy Logic Controller is used to guide and
control the inverter to synthesize a stepped output voltage waveform with
reduced harmonics. In this paper, three different intelligent soft-computing
methods are used to design a fuzzy system to be used as a closed loop control
system for regulating the inverter output. Gravitational Search Algorithm
and Genetic Algorithm are used as optimization methods to evaluate
switching angles for different combination of input voltages applied to MLI.
Wavelet Transform is used as synthesizing technique to shape stepped output
waveform of inverter using orthogonal wavelet sets. The proposed FLC
controlled method is carried out for a wider range of input dc voltages by
considering ±10% variations in nominal voltage value. A 7-level inverter is
used to validate the results of proposed control methods. The three proposed
methods are then compared in terms of various parameters like
computational time, switching angles and THD to justify the performance
and system flexibility. Finally, hardware based results are also obtained to
verify the viability of the proposed method.
Design and implementation a prototype system for fusion image by using SWT-PC...IJECEIAES
The technology of fusion image is dominance strongly over domain research for recent years, the techniques of fusion have various applications in real time used and proposed such as purpose of military and remote sensing etc., the fusion image is very efficient in processing of digital image. Single image produced from two images or more information of relevant combining process results from multi sensor fusion image. FPGA is the best implementation types of most technology enabling wide spread.This device works with modern versions for different critical characteristics same huge number of elements logic in order to permit complex algorithm implemented. In this paper,filters are designed and implemented in FPGA utilized for disease specified detection from images CT/MRI scanned where the samples are taken for human's brain with various medical images and the processing of fusion employed by using technique Stationary Wavelet Transform and Principal Component Analysis (SWT-PCA). Accuracy image output increases when implemented this technique and that was done by sampling down eliminating where effects blurring and artifacts doesn't influenced. The algorithm of SWT-PCA parameters quality measurements like NCC, MSE, PSNR, coefficients and Eigen values.The advantages significant of this system that provide real time, time rapid to market and portability beside the change parametric continuing in the DWT transform. The designed and simulation of module proposed system has been done by using MATLAB simulink and blocks generator system, Xilinx synthesized with synthesis tool (XST) and implemented in XilinxSpartan 6-SP605 device.
This document presents a GPU-accelerated algorithm for solving the Group Steiner Problem (GSP) which arises in routing phases of VLSI circuit design. The algorithm uses a depth-bounded heuristic to construct approximate minimum-cost Steiner trees in parallel using CUDA-aware MPI. Evaluation on a supercomputer shows the parallel implementation achieves up to 302x speedup over serial algorithms and scales well with problem size and processor count.
Co-Simulation Interfacing Capabilities in Device-Level Power Electronic Circu...IJPEDS-IAES
Power electronic circuit simulation today has become increasingly more demanding in both
the speed and accuracy. Whilst almost every simulator has its own advantages and disadvantages,
co-simulations are becoming more prevalent. This paper provides an overview of
the co-simulation capabilities of device-level circuit simulators. More specifically, a listing
of device-level simulators with their salient features are compared and contrasted. The
co-simulation interfaces between several simulation tools are discussed. A case study is
presented to demonstrate the co-simulation between a device-level simulator (PSIM) interfacing
a system-level simulator (Simulink), and a finite element simulation tool (FLUX).
Results demonstrate the necessity and convenience as well as the drawbacks of such a comprehensive
simulation.
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGAVLSICS Design
Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.
Low Power Clock Distribution Schemes in VLSI DesignIJERA Editor
This paper reviewed the comparison between different clock distribution schemes which used for low power
VLSI design which are the most important aspect in the industry. The main clock distribution schemes are
single driver clock scheme and distributed buffers clock scheme. There are different tradeoffs in both the
techniques such as size of buffers, number of buffers etc.
Presented approaches for generation of multiple clock gating domain parameterized PVT independent power abstracts for large IP blocks. We accomplish the gating domain parameterization through separation of the attribution of switching due to each single domain through a marking and tracing process, thereby precluding the need for separate domain by domain simulation to achieve the parameterization.
Experimental results comparing proposed approach on IP blocks of varying sizes from a real industry strength microprocessor design clearly highlight accuracy impact while keeping run time and model size increase in an acceptable range. In terms of extensions, we are exploring approaches where we could preserve each of the domains independently, for which we are looking into formulations based on constructing clock gating domain conflict hyper graphs and coloring them to determine domain interactions.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An fpga implementation of the lms adaptive filter eSAT Journals
This document describes an FPGA implementation of the Least Mean Square (LMS) adaptive filter algorithm for active vibration control. It compares fixed-point and floating-point implementations in terms of area usage and performance. The LMS algorithm is implemented using a finite state machine model with separate modules for operations like filtering, error estimation, and weight adaptation. Both implementations utilize this structural model. The fixed-point version uses 16-bit integers and fractions, while the floating-point version leverages IP cores. Results show the floating-point implementation has better accuracy and resource utilization than the fixed-point version for active vibration control applications on FPGAs.
The proposed Vedic multiplier is based on traditional Vedic Sutras multiplication techniques that were used to multiply numbers in the decimal system. It uses the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" to multiply two numbers faster and with less area than other multipliers like booth and array multipliers. The Vedic multiplier proves to be highly efficient for applications like digital signal processing in terms of both speed and smaller area compared to other designs.
Parallel implementation of pulse compression method on a multi-core digital ...IJECEIAES
Pulse compression algorithm is widely used in radar applications. It requires a huge processing power in order to be executed in real time. Therefore, its processing must be distributed along multiple processing units. The present paper proposes a real time platform based on the multi-core digital signal processor (DSP) C6678 from Texas Instruments (TI). The objective of this paper is the optimization of the parallel implementation of pulse compression algorithm over the eight cores of the C6678 DSP. Two parallelization approaches were implemented. The first approach is based on the open multi processing (OpenMP) programming interface, which is a software interface that helps to execute different sections of a program on a multi core processor. The second approach is an optimized method that we have proposed in order to distribute the processing and to synchronize the eight cores of the C6678 DSP. The proposed method gives the best performance. Indeed, a parallel efficiency of 94% was obtained when the eight cores were activated.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
Implementation of Carry Skip Adder using PTLIRJET Journal
The document proposes a design and implementation of a carry skip adder using pass transistor logic to improve performance over a conventional carry skip adder. It describes the structures of a conventional carry skip adder and the proposed pass transistor logic carry skip adder. Simulation results show that the proposed design reduces the number of transistors, area, delay, and average power compared to the conventional carry skip adder.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
This document summarizes a research paper that presents a new approach to designing parallel self-timed adders called PASTA (Parallel Self-Timed Adder). PASTA uses a recursive formulation and only half adders, allowing some bit operations to occur in parallel without carry propagation. This achieves logarithmic performance without complex circuitry. The design is regular and modular, using half adders and multiplexers. Simulation results show PASTA has better practicality and performance than existing asynchronous adders.
IRJET-A Review on Trends in Multicore Processor Based on Cache and Power Diss...IRJET Journal
K.Aruli, B.Nivetha, G.N.Jayabhavani, M.Saravanan "A Review on Trends in Multicore Processor Based on Cache and Power Dissipation", International Research Journal of Engineering and Technology (IRJET), Volume2,issue-01 April 2015.e-ISSN:2395-0056, p-ISSN:2395-0072. www.irjet.net
Abstract
A multi-core processor is an integrated circuit to which two or more processors attached for enhanced performance, reduced power consumption, and more efficient simultaneous processing of multiple tasks. Multi-core processing is a growing industrial trend as single core processors rapidly reach the physical limits of complexity and speed. It exploits increased feature-size and density. It increases functional units per chip and limit energy consumption per operation. This paper provides the review of various papers in multicore architecture, discussing various parameters like number of cores, cache coherence and power dissipation.
Performance Analysis of a Low-Power High-Speed Hybrid 1-Bit Full Adder Circui...IRJET Journal
The document describes a proposed hybrid 1-bit full adder circuit designed using different CMOS technologies. Full adders are important building blocks for arithmetic circuits. Existing full adder designs have limitations like high power consumption, voltage degradation, and slow speed. The proposed hybrid design addresses these issues. It uses a combination of logic styles for the sum generation and carry generation circuits. The sum circuit uses an improved XNOR module to reduce power and overcome switching delays at low voltages. The carry generation circuit uses transmission gates to reduce the carry propagation delay. The proposed hybrid full adder circuit was simulated using Cadence at 180nm, 90nm, and 45nm process technologies. Simulation results showed improvements in power, delay, and transistor count compared
This document discusses mapping networks onto a hybrid Network-on-Chip (NoC) architecture that integrates packet switching, circuit switching, and virtual circuit switching. It reviews prior work on mapping applications onto NoC architectures to optimize performance, energy consumption, and latency. The paper proposes a hybrid scheme to map cores and communications onto different switching mechanisms in the NoC to balance latency, flexibility, and efficiency.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This document discusses the performance evaluation of a low power carry save adder (CSA) for VLSI applications. It begins with an abstract that examines subthreshold leakage in CSA circuits and how reducing threshold voltage can lower power consumption. The document then reviews previous work on CSA design. It presents the architecture of a proposed 4-bit CSA designed using gate diffusion input cells to reduce area and power. Simulation results show the CSA has total average power of 4.93μW, propagation delay of 16.3ns, and 37% reduced area due to using GDI cells. The CSA operates as intended in subthreshold regions with low static leakage current.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount
of leakage current which confine increases the power consumption of the devices. Adders are the basic
building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
LOAD BALANCING AND ENERGY EFFICIENCY IN WSN BY CLUSTER JOINING METHODIAEME Publication
In any WSN life of network is depending on life of sensor node. Thus, proper load balancing is very useful for improving life of network. The tree-based routing protocols like GSTEB used dynamic tree structures for routing without any formation of collections. In cases of larger networks, the scheme is not always feasible. In this proposed work cluster-based routing method is used. Cluster head is selected such that it should be close to the base station and should have maximum residential energy than other nodes selected for cluster formation. Size of cluster is controlled by using location-based cluster joining method such that nodes selects their nearest collection head based on the signal strength from cluster head and distance between node and cluster head. Nodes connect to head having the highest signal strength and closest to the base station, this minimizes size of cluster and reduces extra energy consumption. In addition to this cluster formation process starts only after availability of data due to an event. So proposed protocol performs better than existing tree based protocols like GSTEB in terms of energy efficiency
LOAD BALANCING AND ENERGY EFFICIENCY IN WSN BY CLUSTER JOINING METHODIAEME Publication
In any WSN life of network is depending on life of sensor node. Thus, proper load balancing is very useful for improving life of network. The tree-based routing protocols like GSTEB used dynamic tree structures for routing without any formation of collections. In cases of larger networks, the scheme is not always feasible. In this proposed work cluster-based routing method is used. Cluster head is selected such that it should be close to the base station and should have maximum residential energy than other nodes selected for cluster formation. Size of cluster is controlled by using location-based cluster joining method such that nodes selects their nearest collection head based on the signal strength from cluster head and distance between node and cluster head. Nodes connect to head having the highest signal strength and closest to the base station, this minimizes size of cluster and reduces extra energy consumption. In addition to this cluster formation process starts only after availability of data due to an event. So proposed protocol performs better than existing tree based protocols like GSTEB in terms of energy efficiency
FIFO Based Routing Scheme for Clock-less SystemWaqas Tariq
As a result of the increasing limitations and growing complexity of semi-custom synchronous design, asynchronous circuits are gaining interest. Asynchronous Systems when combined with the local synchronous logic have provoked renewed interest over recent years, as they have the potential to combine the benefits of asynchronous and synchronous design paradigms, in this paper a new technique using FIFO in order to overcome the limitation on timing imposed by slow routing is proposed. FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain.
Review on optimized area,delay and power efficient carry select adder using n...IRJET Journal
This document discusses optimized area, delay, and power efficient carry select adders using NAND gates. Carry select adders are commonly used fast adders but require more area due to using two ripple carry adders and a multiplexer. The proposed design aims to significantly reduce area, power, and redundant logic in carry select adders by developing a new logic formulation technique using only NAND gates. NAND gates have advantages including lower delay than NOR gates, easier fabrication, and better power performance. The design aims to optimize area, delay, and power over conventional carry select adder designs.
Analysis of different bit carry look ahead adder using verilog code 2IAEME Publication
This document analyzes and compares different bit carry look ahead adders implemented using Verilog code. It summarizes the performance of 4-bit, 8-bit, and 16-bit carry look ahead adders synthesized on Xilinx. The carry look ahead adder architecture is described, which calculates carry bits in parallel to reduce delay compared to ripple carry adders. Simulation results show that as the bit width increases, the number of slices, LUTs, logic levels, and delay also increase for carry look ahead adders. The carry look ahead adder has the lowest area-delay product, making it suitable for applications requiring low power and high speed.
Static Load Balancing of Parallel Mining Efficient Algorithm with PBEC in Fre...IRJET Journal
This document presents a proposed static load balancing method for parallel mining of frequent sequences. It partitions the set of all frequent sequences into disjoint prefix-based equivalence classes (PBECs). It estimates the relative execution time of each PBEC using the sequential PrefixSpan algorithm on sampling data sets. The PBECs are then assigned to processors based on these estimated execution times to balance the computational load. The goal is to develop an efficient parallel frequent sequence mining algorithm that can scale to large datasets through static load balancing of computations across multiple processors.
This paper describes a parallel single-rail self-timed adder using dual gate MOSFETs which is based on a recursive formulation for performing multi bit binary addition. Thus the addition is parallel for those bits that do not need any carry chain propagation and the circuit attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical design of dual gate MOSFET is provided along with a completion detection unit. The design is regular and does not have any practical limitations of high fan outs. A high fan-in gate is required on the design but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using LT spice tool that verify the practicality and superiority of the proposed approach over existing asynchronous adders.
This document summarizes a research paper that proposes using a Real-Coded Genetic Algorithm to design Unified Power Flow Controller (UPFC) damping controllers. The goal is to damp low frequency oscillations in power systems. The paper models a single-machine infinite-bus power system installed with a UPFC. It linearizes the system equations and formulates the controller design as an optimization problem to minimize oscillations. Simulation results comparing the proposed RCGA approach to conventional tuning are presented to demonstrate its effectiveness and robustness in damping power system oscillations.
Similar to Design of Parallel Self-Timed Adder (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.