Abstract This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length. Keywords—Built-in self-test (BIST), low power, single-input change (SIC), test pattern generator (TPG)
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
A Modified Design of Test Pattern Generator for Built-In-Self- Test ApplicationsIJERA Editor
Test Pattern Generators (TPG) are very important logic part of the Circuits that have self-test features.
Nowadays, the self-test feature is an in-built part of the modern application hardware designs. This feature
enables the user to test and verify the specific hardware failure with the help of the hardware itself. To enable
self-test an extra operational and control circuit is required by the application based operational and control
circuit. The size of the self-test block is generally small as compared to the actual hardware. Most of the self-test
hardware includes Linear Feedback Shift Register (LFSR) to generate the test signal pattern in the self-test mode
of circuit operation. In the present work a simple 3-FF based modified design of TPG is designed and simulated
to generate a 4-bit test signal sequence. The present work also shows FPGA based simulation and synthesis of a
16-bit TPG design using the 4-bit TPG. The present TPG design concept can be replicated to generate a test
sequence of higher bit length for advanced applications. The present design is simulated on Xilinx tool for
functional verification.
In our project, we propose a novel architecture which generates the test patterns with reduced switching activities. LP-TPG (Test pattern Generator) structure consists of modified low power linear feedback shift register (LP-LFSR), m-bit counter; gray counter, NOR-gate structure and XOR-array. The m-bit counter is initialized with Zeros and which generates 2m test patterns in sequence. The m-bit counter and gray code generator are controlled by common clock signal [CLK]. The output of m-bit counter is applied as input to gray code generator and NOR-gate structure. When all the bits of counter output are Zero, the NOR-gate output is one. Only when the NOR-gate output is one, the clock signal is applied to activate the LP-LFSR which generates the next seed. The seed generated from LP-LFSR is Exclusive–OR ed with the data generated from gray code generator. The patterns generated from the Exclusive–OR array are the final output patterns. The proposed architecture is simulated using Modelsim and synthesized using Xilinx ISE 13.2 and it will be implemented on XC3S500e Spartan 3E FPGA board for hardware implementation and testing. The Xilinx Chip scope tool will be used to test the FPGA inside results while the logic running on FPGA.
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...iosrjce
Now a day’s highly integrated multi layer board with IC’s is virtually impossible to be accessed
physically for testing. The major problem detected during testing a circuit includes test generation and gate to
I/O pin problems. In design of any circuit, consuming low power and less hardware utilization is an important
design parameter. Therefore reliable testing methods are introduced which reduces the cost of the hardware
required and also power consumed by the device. In this project a new fault coverage test pattern generator is
generated using a linear feedback shift register called FC-LFSR which can perform fault analysis and reduces
the total power of the circuit. In this test, it generates three intermediate patterns between the random patterns
which reduces the transitional activities of primary inputs so that the switching activities inside the circuit under
test will be reduced. The test patterns generated are applied to c17 benchmark circuit, whose results with fault
coverage of the circuit being tested. The simulation for this design is performed using Xilinx ISE software using
Verilog hardware description language
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
This document discusses a technique called Linear Feedback Shift Register - Bit Complement Test Pattern Generation (LFSR-BCTPG) to minimize test power in VLSI circuits. The LFSR-BCTPG generates test patterns with the LFSR but complements output bits to reduce repeated patterns. This increases unique test vectors and improves fault coverage while reducing circuit size and dynamic power compared to a conventional LFSR. The technique generates test patterns by alternating the enable signals to the two halves of the LFSR flip-flops. Evaluation on ISCAS benchmark circuits showed this method reduces dynamic power consumption during testing.
Clock Gating Cells for Low Power Scan Testing By Dft TechniqueIJERA Editor
This document summarizes research on reducing power consumption during scan testing of integrated circuits. It discusses using design-for-test (DFT) techniques like clock gating cells to minimize unnecessary clock toggling during scan testing. By identifying unused clock signals through scan-based testing, clock gating cells can be inserted to temporarily avoid those clock signals, reducing heat and power problems. The document also explores modifying test patterns to reduce switching activity during scan shifting and capture to further lower power consumption.
Techniques for Minimizing Power Consumption in DFT during Scan Test ActivityIJTET Journal
1. The document discusses techniques for minimizing power consumption during scan test activity. It proposes a novel circuit technique to eliminate switching in combinational logic during scan shifting by masking logic inputs. Blocking transistors are added to gate the power supply to first-level gates at flip-flop outputs during scan shifting.
2. A selective trigger scan architecture is proposed that reduces switching between scan cells and test vectors by using NOR gates to compare previous and next test vector values and only applying differences. Scan chain reordering is also used to minimize transitions between flip-flops.
3. Experimental results on ISCAS89 benchmarks show the proposed techniques reduce static power by 6.1-11% and area overhead by 47% compared to
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
A Modified Design of Test Pattern Generator for Built-In-Self- Test ApplicationsIJERA Editor
Test Pattern Generators (TPG) are very important logic part of the Circuits that have self-test features.
Nowadays, the self-test feature is an in-built part of the modern application hardware designs. This feature
enables the user to test and verify the specific hardware failure with the help of the hardware itself. To enable
self-test an extra operational and control circuit is required by the application based operational and control
circuit. The size of the self-test block is generally small as compared to the actual hardware. Most of the self-test
hardware includes Linear Feedback Shift Register (LFSR) to generate the test signal pattern in the self-test mode
of circuit operation. In the present work a simple 3-FF based modified design of TPG is designed and simulated
to generate a 4-bit test signal sequence. The present work also shows FPGA based simulation and synthesis of a
16-bit TPG design using the 4-bit TPG. The present TPG design concept can be replicated to generate a test
sequence of higher bit length for advanced applications. The present design is simulated on Xilinx tool for
functional verification.
In our project, we propose a novel architecture which generates the test patterns with reduced switching activities. LP-TPG (Test pattern Generator) structure consists of modified low power linear feedback shift register (LP-LFSR), m-bit counter; gray counter, NOR-gate structure and XOR-array. The m-bit counter is initialized with Zeros and which generates 2m test patterns in sequence. The m-bit counter and gray code generator are controlled by common clock signal [CLK]. The output of m-bit counter is applied as input to gray code generator and NOR-gate structure. When all the bits of counter output are Zero, the NOR-gate output is one. Only when the NOR-gate output is one, the clock signal is applied to activate the LP-LFSR which generates the next seed. The seed generated from LP-LFSR is Exclusive–OR ed with the data generated from gray code generator. The patterns generated from the Exclusive–OR array are the final output patterns. The proposed architecture is simulated using Modelsim and synthesized using Xilinx ISE 13.2 and it will be implemented on XC3S500e Spartan 3E FPGA board for hardware implementation and testing. The Xilinx Chip scope tool will be used to test the FPGA inside results while the logic running on FPGA.
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...iosrjce
Now a day’s highly integrated multi layer board with IC’s is virtually impossible to be accessed
physically for testing. The major problem detected during testing a circuit includes test generation and gate to
I/O pin problems. In design of any circuit, consuming low power and less hardware utilization is an important
design parameter. Therefore reliable testing methods are introduced which reduces the cost of the hardware
required and also power consumed by the device. In this project a new fault coverage test pattern generator is
generated using a linear feedback shift register called FC-LFSR which can perform fault analysis and reduces
the total power of the circuit. In this test, it generates three intermediate patterns between the random patterns
which reduces the transitional activities of primary inputs so that the switching activities inside the circuit under
test will be reduced. The test patterns generated are applied to c17 benchmark circuit, whose results with fault
coverage of the circuit being tested. The simulation for this design is performed using Xilinx ISE software using
Verilog hardware description language
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
This document discusses a technique called Linear Feedback Shift Register - Bit Complement Test Pattern Generation (LFSR-BCTPG) to minimize test power in VLSI circuits. The LFSR-BCTPG generates test patterns with the LFSR but complements output bits to reduce repeated patterns. This increases unique test vectors and improves fault coverage while reducing circuit size and dynamic power compared to a conventional LFSR. The technique generates test patterns by alternating the enable signals to the two halves of the LFSR flip-flops. Evaluation on ISCAS benchmark circuits showed this method reduces dynamic power consumption during testing.
Clock Gating Cells for Low Power Scan Testing By Dft TechniqueIJERA Editor
This document summarizes research on reducing power consumption during scan testing of integrated circuits. It discusses using design-for-test (DFT) techniques like clock gating cells to minimize unnecessary clock toggling during scan testing. By identifying unused clock signals through scan-based testing, clock gating cells can be inserted to temporarily avoid those clock signals, reducing heat and power problems. The document also explores modifying test patterns to reduce switching activity during scan shifting and capture to further lower power consumption.
Techniques for Minimizing Power Consumption in DFT during Scan Test ActivityIJTET Journal
1. The document discusses techniques for minimizing power consumption during scan test activity. It proposes a novel circuit technique to eliminate switching in combinational logic during scan shifting by masking logic inputs. Blocking transistors are added to gate the power supply to first-level gates at flip-flop outputs during scan shifting.
2. A selective trigger scan architecture is proposed that reduces switching between scan cells and test vectors by using NOR gates to compare previous and next test vector values and only applying differences. Scan chain reordering is also used to minimize transitions between flip-flops.
3. Experimental results on ISCAS89 benchmarks show the proposed techniques reduce static power by 6.1-11% and area overhead by 47% compared to
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
This document describes a DFT-based approach for reducing switching activity during scan shift testing of circuits. It begins with an analysis of switching activity during normal operation versus scan testing, finding that scan shift activity is approximately 2.5 times higher than normal operation. It then proposes a method that modifies the RTL description to "freeze" some scan cell outputs during scan shift by inserting additional logic gates. This is done at the RTL level before synthesis so that timing closure can be automatically handled. The goal is to reduce scan shift power by preventing transitions from propagating while minimizing additional hardware overhead.
Fpga implementation of run length encoding with new formulated codeword gener...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IRJET- Reduction of Power, Leakage and Area of a Standard Cell Asics using Th...IRJET Journal
This document describes a new approach to reduce power, leakage, and area in standard cell ASICs using threshold logic gates and power gating techniques. Threshold logic gates are designed that behave as multi-input, single-output flip-flops computing a threshold function. Pulsed inputs of varying width are provided. Power gating techniques like sleep mode and MTCMOS are used to reduce leakage and dynamic power. Simulation results show the proposed hybrid circuit of conventional and threshold logic gates with power gating achieves 73% power reduction compared to conventional designs.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Iaetsd power capture safe test pattern determinationIaetsd Iaetsd
The document proposes a method to determine power-safe test patterns for at-speed scan-based testing to address excessive capture power issues. It involves two main processes: 1) test pattern refinement process which refines existing power-safe patterns to detect faults detected by power-risky patterns while satisfying power constraints, and 2) low-power test pattern regeneration process which generates new power-safe patterns if faults remain undetected after refinement. Experimental results show the method can detect over 75% of power-risky faults through refinement with up to 12.76% reduction in test data volume without loss of fault coverage.
This document summarizes the performance enhancement and characterization of a junctionless vertical slit field effect transistor (JLVeSFET). Key findings from simulations include:
1) The JLVeSFET shows an optimized subthreshold slope of 65mV/decade and OFF current of ~10-18A/μm for a 50nm radius device with a high-k dielectric.
2) Using a high-k dielectric (Si3N4) instead of SiO2 increases the Ion/Ioff ratio to ~1011 and reduces the subthreshold slope to 63mV/decade.
3) Increasing the gate doping concentration reduces the subthreshold slope slightly while increasing the Ion/
Cycle-free CycleGAN using invertible generator for unsupervised low-dose CT d...KwonTaesung
This document presents a method for unsupervised low-dose CT denoising using an invertible generator in a cycle-free CycleGAN framework. Conventional CycleGAN models require two generators and discriminators, while the proposed method uses a single invertible generator and discriminator. This reduces model complexity while achieving comparable denoising performance to state-of-the-art unsupervised methods. Quantitative and qualitative results on low-dose CT datasets demonstrate the effectiveness of the proposed cycle-free CycleGAN for parameter-efficient unsupervised low-dose CT denoising.
This document proposes a universal algorithm for stage switching in hypercube interconnection networks used in multi-core systems. It analyzes a 4-stage 16x16 hypercube network and derives a switching algorithm where the selection bit sequence changes at each stage in a predefined manner. This algorithm is then generalized for an n-stage hypercube network to establish relationships between the selection bit patterns at different stages. The proposed universal algorithm could be used for linear switching in hypercube networks of any size to efficiently design higher order interconnection blocks for multi-core systems.
Determining Multiple Steady State Zcs Operating Points Of A Switch Mode Conta...tchunsen
The document presents a new method for determining all possible steady-state zero current switching (ZCS) operating points of a switch-mode contactless power transfer system. It uses a stroboscopic mapping model and calculates fixed points corresponding to circuit ZCS conditions. This allows identifying four steady-state operating points for an inductor-capacitor-inductor type system. Parameter influences on ZCS periods are studied using bifurcation diagrams. Both simulations and experiments verified the proposed method, providing opportunities for a practical system to operate at different soft switching frequencies.
Performance evaluation of ann based plasma position controllers for aditya to...IAEME Publication
This paper evaluates the performance of artificial neural network (ANN) based plasma position controllers for the Aditya tokamak device. Radial basis function networks and generalized recurrent neural networks are developed as controllers and their performance is compared to an existing backpropagation network controller. Training data for the ANNs comes from the Aditya RZIP model. Testing shows the backpropagation network provides better performance in terms of signal-to-noise ratio and root mean square error compared to the other controllers. Further testing on actual plasma discharge data from Aditya is recommended, as well as exploring neuro-fuzzy controllers for plasma position control.
Comparison of cascade P-PI controller tuning methods for PMDC motor based on ...IJECEIAES
In this paper, there are two contributions: The first contribution is to design a robust cascade P-PI controller to control the speed and position of the permanent magnet DC motor (PMDC). The second contribution is to use three methods to tuning the parameter values for this cascade controller by making a comparison between them to obtain the best results to ensure accurate tracking trajectory on the axis to reach the desired position. These methods are the classical method (CM) and it requires some assumptions, the genetic algorithm (GA), and the particle swarm optimization algorithm (PSO). The simulation results show the system becomes unstable after applying the load when using the classical method because it assumes cancellation of the load effect. Also, an overshoot of about 3.763% is observed, and a deviation from the desired position of about 12.03 degrees is observed when using the GA algorithm, while no deviation or overshoot is observed when using the PSO algorithm. Therefore, the PSO algorithm has superiority as compared to the other two methods in improving the performance of the PMDC motor by extracting the best parameters for the cascade P-PI controller to reach the desired position at a regular speed.
The document summarizes research on using a genetic algorithm to optimize the location and parameters of Flexible AC Transmission System (FACTS) devices in a power system. It first introduces FACTS devices and their ability to control power flow. It then describes using a genetic algorithm to simultaneously determine the optimal type, location, and rating of FACTS devices with the objectives of minimizing generation costs and power losses/voltage deviations. The methodology is tested on the IEEE 30-bus system with different FACTS device types. The results indicate the genetic algorithm approach can effectively determine the configuration of FACTS devices that increase system loadability.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
Several alternative methods available:
Enhanced sudden short circuit tests:
Improvement over IEEE Standard 115-1983; uses rotor current measurements to identify field circuit data
Does not provide accurate q-axis data
Stator decrement tests:
Unit tripped with only d-axis armature current (P=0, iq=0); terminal voltage and field current time responses used to estimate d-axis data
Similar test with only q-axis armature current (id=0) gives q-axis data; load angle equal to power factor angle, a condition difficult to determine when parameters not known accurately
Difficulty in maintaining constant field voltage with bus-fed exciters
Currently, fairly widely used.
References 1, 2 and 3 describe this approach
Continuous Conversion of CT Kernel using Switchable CycleGAN with AdaINserin10
This document proposes a method for continuous conversion of CT kernels using a switchable CycleGAN with adaptive instance normalization (AdaIN). It introduces soft and sharp CT kernels and the need for continuous conversion between them. The method uses a CycleGAN with a single generator and AdaIN to allow interpolation between kernel styles. Experimental results show the model can successfully interpolate between two kernels and among three kernels, outperforming alternative methods. The addition of a self-consistency loss further improves image quality.
- The document proposes ProxGen, a unified framework for stochastic proximal gradient descent methods that can handle arbitrary preconditioners and non-convex regularizers.
- ProxGen derives proximal updates for popular optimizers like Adam that incorporate the preconditioner into the proximal mapping, which previous work had not addressed.
- Experiments on sparse neural networks and binary neural networks demonstrate that ProxGen converges faster and achieves better generalization than subgradient-based methods and previous proximal gradient methods.
The optimal solution for unit commitment problem using binary hybrid grey wol...IJECEIAES
The aim of this work is to solve the unit commitment (UC) problem in power systems by calculating minimum production cost for the power generation and finding the best distribution of the generation among the units (units scheduling) using binary grey wolf optimizer based on particle swarm optimization (BGWOPSO) algorithm. The minimum production cost calculating is based on using the quadratic programming method and represents the global solution that must be arriving by the BGWOPSO algorithm then appearing units status (on or off). The suggested method was applied on “39 bus IEEE test systems”, the simulation results show the effectiveness of the suggested method over other algorithms in terms of minimizing of production cost and suggesting excellent scheduling of units.
This document discusses built-in self-test (BIST) techniques for testing combinational circuits using FPGAs. It begins with an introduction to BIST and discusses reasons for on-chip testing compared to off-chip testing. It then reviews different types of faults in integrated circuits and compares digital and analog testing techniques. The document also compares design-for-test (DFT) and BIST techniques. Finally, it classifies existing BIST techniques and reviews approaches based on input vectors, test operation modes, and response analysis domain.
This document describes the design and implementation of a PRBS (pseudorandom bit sequence) generator module using a linear feedback shift register (LFSR). It includes the theoretical background of LFSRs, a 4-bit example, hardware implementation on a breadboard and printed circuit board, and results showing the output sequences for different feedback configurations. The generator can be extended to output any desired 8-bit sequence using a parallel-to-serial converter. Maximum randomness was achieved with feedback from the 1st and 2nd shift registers.
The document discusses built-in self-testing (BIST) for testing integrated circuits. BIST uses on-chip pattern generators and response compactors to test circuits without needing expensive external automatic test equipment. It reduces costs associated with test generation, storage, application and diagnosis. The document covers BIST architectures, linear feedback shift registers for pseudo-random pattern generation, response compaction, and fault coverage analysis of BIST.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
This document describes a DFT-based approach for reducing switching activity during scan shift testing of circuits. It begins with an analysis of switching activity during normal operation versus scan testing, finding that scan shift activity is approximately 2.5 times higher than normal operation. It then proposes a method that modifies the RTL description to "freeze" some scan cell outputs during scan shift by inserting additional logic gates. This is done at the RTL level before synthesis so that timing closure can be automatically handled. The goal is to reduce scan shift power by preventing transitions from propagating while minimizing additional hardware overhead.
Fpga implementation of run length encoding with new formulated codeword gener...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IRJET- Reduction of Power, Leakage and Area of a Standard Cell Asics using Th...IRJET Journal
This document describes a new approach to reduce power, leakage, and area in standard cell ASICs using threshold logic gates and power gating techniques. Threshold logic gates are designed that behave as multi-input, single-output flip-flops computing a threshold function. Pulsed inputs of varying width are provided. Power gating techniques like sleep mode and MTCMOS are used to reduce leakage and dynamic power. Simulation results show the proposed hybrid circuit of conventional and threshold logic gates with power gating achieves 73% power reduction compared to conventional designs.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Iaetsd power capture safe test pattern determinationIaetsd Iaetsd
The document proposes a method to determine power-safe test patterns for at-speed scan-based testing to address excessive capture power issues. It involves two main processes: 1) test pattern refinement process which refines existing power-safe patterns to detect faults detected by power-risky patterns while satisfying power constraints, and 2) low-power test pattern regeneration process which generates new power-safe patterns if faults remain undetected after refinement. Experimental results show the method can detect over 75% of power-risky faults through refinement with up to 12.76% reduction in test data volume without loss of fault coverage.
This document summarizes the performance enhancement and characterization of a junctionless vertical slit field effect transistor (JLVeSFET). Key findings from simulations include:
1) The JLVeSFET shows an optimized subthreshold slope of 65mV/decade and OFF current of ~10-18A/μm for a 50nm radius device with a high-k dielectric.
2) Using a high-k dielectric (Si3N4) instead of SiO2 increases the Ion/Ioff ratio to ~1011 and reduces the subthreshold slope to 63mV/decade.
3) Increasing the gate doping concentration reduces the subthreshold slope slightly while increasing the Ion/
Cycle-free CycleGAN using invertible generator for unsupervised low-dose CT d...KwonTaesung
This document presents a method for unsupervised low-dose CT denoising using an invertible generator in a cycle-free CycleGAN framework. Conventional CycleGAN models require two generators and discriminators, while the proposed method uses a single invertible generator and discriminator. This reduces model complexity while achieving comparable denoising performance to state-of-the-art unsupervised methods. Quantitative and qualitative results on low-dose CT datasets demonstrate the effectiveness of the proposed cycle-free CycleGAN for parameter-efficient unsupervised low-dose CT denoising.
This document proposes a universal algorithm for stage switching in hypercube interconnection networks used in multi-core systems. It analyzes a 4-stage 16x16 hypercube network and derives a switching algorithm where the selection bit sequence changes at each stage in a predefined manner. This algorithm is then generalized for an n-stage hypercube network to establish relationships between the selection bit patterns at different stages. The proposed universal algorithm could be used for linear switching in hypercube networks of any size to efficiently design higher order interconnection blocks for multi-core systems.
Determining Multiple Steady State Zcs Operating Points Of A Switch Mode Conta...tchunsen
The document presents a new method for determining all possible steady-state zero current switching (ZCS) operating points of a switch-mode contactless power transfer system. It uses a stroboscopic mapping model and calculates fixed points corresponding to circuit ZCS conditions. This allows identifying four steady-state operating points for an inductor-capacitor-inductor type system. Parameter influences on ZCS periods are studied using bifurcation diagrams. Both simulations and experiments verified the proposed method, providing opportunities for a practical system to operate at different soft switching frequencies.
Performance evaluation of ann based plasma position controllers for aditya to...IAEME Publication
This paper evaluates the performance of artificial neural network (ANN) based plasma position controllers for the Aditya tokamak device. Radial basis function networks and generalized recurrent neural networks are developed as controllers and their performance is compared to an existing backpropagation network controller. Training data for the ANNs comes from the Aditya RZIP model. Testing shows the backpropagation network provides better performance in terms of signal-to-noise ratio and root mean square error compared to the other controllers. Further testing on actual plasma discharge data from Aditya is recommended, as well as exploring neuro-fuzzy controllers for plasma position control.
Comparison of cascade P-PI controller tuning methods for PMDC motor based on ...IJECEIAES
In this paper, there are two contributions: The first contribution is to design a robust cascade P-PI controller to control the speed and position of the permanent magnet DC motor (PMDC). The second contribution is to use three methods to tuning the parameter values for this cascade controller by making a comparison between them to obtain the best results to ensure accurate tracking trajectory on the axis to reach the desired position. These methods are the classical method (CM) and it requires some assumptions, the genetic algorithm (GA), and the particle swarm optimization algorithm (PSO). The simulation results show the system becomes unstable after applying the load when using the classical method because it assumes cancellation of the load effect. Also, an overshoot of about 3.763% is observed, and a deviation from the desired position of about 12.03 degrees is observed when using the GA algorithm, while no deviation or overshoot is observed when using the PSO algorithm. Therefore, the PSO algorithm has superiority as compared to the other two methods in improving the performance of the PMDC motor by extracting the best parameters for the cascade P-PI controller to reach the desired position at a regular speed.
The document summarizes research on using a genetic algorithm to optimize the location and parameters of Flexible AC Transmission System (FACTS) devices in a power system. It first introduces FACTS devices and their ability to control power flow. It then describes using a genetic algorithm to simultaneously determine the optimal type, location, and rating of FACTS devices with the objectives of minimizing generation costs and power losses/voltage deviations. The methodology is tested on the IEEE 30-bus system with different FACTS device types. The results indicate the genetic algorithm approach can effectively determine the configuration of FACTS devices that increase system loadability.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
Several alternative methods available:
Enhanced sudden short circuit tests:
Improvement over IEEE Standard 115-1983; uses rotor current measurements to identify field circuit data
Does not provide accurate q-axis data
Stator decrement tests:
Unit tripped with only d-axis armature current (P=0, iq=0); terminal voltage and field current time responses used to estimate d-axis data
Similar test with only q-axis armature current (id=0) gives q-axis data; load angle equal to power factor angle, a condition difficult to determine when parameters not known accurately
Difficulty in maintaining constant field voltage with bus-fed exciters
Currently, fairly widely used.
References 1, 2 and 3 describe this approach
Continuous Conversion of CT Kernel using Switchable CycleGAN with AdaINserin10
This document proposes a method for continuous conversion of CT kernels using a switchable CycleGAN with adaptive instance normalization (AdaIN). It introduces soft and sharp CT kernels and the need for continuous conversion between them. The method uses a CycleGAN with a single generator and AdaIN to allow interpolation between kernel styles. Experimental results show the model can successfully interpolate between two kernels and among three kernels, outperforming alternative methods. The addition of a self-consistency loss further improves image quality.
- The document proposes ProxGen, a unified framework for stochastic proximal gradient descent methods that can handle arbitrary preconditioners and non-convex regularizers.
- ProxGen derives proximal updates for popular optimizers like Adam that incorporate the preconditioner into the proximal mapping, which previous work had not addressed.
- Experiments on sparse neural networks and binary neural networks demonstrate that ProxGen converges faster and achieves better generalization than subgradient-based methods and previous proximal gradient methods.
The optimal solution for unit commitment problem using binary hybrid grey wol...IJECEIAES
The aim of this work is to solve the unit commitment (UC) problem in power systems by calculating minimum production cost for the power generation and finding the best distribution of the generation among the units (units scheduling) using binary grey wolf optimizer based on particle swarm optimization (BGWOPSO) algorithm. The minimum production cost calculating is based on using the quadratic programming method and represents the global solution that must be arriving by the BGWOPSO algorithm then appearing units status (on or off). The suggested method was applied on “39 bus IEEE test systems”, the simulation results show the effectiveness of the suggested method over other algorithms in terms of minimizing of production cost and suggesting excellent scheduling of units.
This document discusses built-in self-test (BIST) techniques for testing combinational circuits using FPGAs. It begins with an introduction to BIST and discusses reasons for on-chip testing compared to off-chip testing. It then reviews different types of faults in integrated circuits and compares digital and analog testing techniques. The document also compares design-for-test (DFT) and BIST techniques. Finally, it classifies existing BIST techniques and reviews approaches based on input vectors, test operation modes, and response analysis domain.
This document describes the design and implementation of a PRBS (pseudorandom bit sequence) generator module using a linear feedback shift register (LFSR). It includes the theoretical background of LFSRs, a 4-bit example, hardware implementation on a breadboard and printed circuit board, and results showing the output sequences for different feedback configurations. The generator can be extended to output any desired 8-bit sequence using a parallel-to-serial converter. Maximum randomness was achieved with feedback from the 1st and 2nd shift registers.
The document discusses built-in self-testing (BIST) for testing integrated circuits. BIST uses on-chip pattern generators and response compactors to test circuits without needing expensive external automatic test equipment. It reduces costs associated with test generation, storage, application and diagnosis. The document covers BIST architectures, linear feedback shift registers for pseudo-random pattern generation, response compaction, and fault coverage analysis of BIST.
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...IJEEE
This paper presents an efficient design and implementation of a 64 bit RISC Processor for Data Logging System. RISC is a design mechanism to reduce the amount of space, time, cost, power and heat etc. reduces the complexity of instruction. The processor is designed for both fixed and floating point number arithmetic calculation. A Data Logger is an electronic instrument that records environmental parameters such as temperature, Humidity, Wind Speed light intensity, water level and water quality. Data Loggers find its key application where automation and control is required. The necessary code written in the hardware description language Verilog HDL.
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...Manoj Subramanian
This document contains 90 project codes related to VLSI design and applications. The project codes cover various topics including low power design, arithmetic circuits, sequential circuits, FPGA design, image processing, cryptography, and biomedical applications. Xilinx ISE and Spartan 3 FPGA are mentioned as the main tools and hardware used. The majority of the projects involve circuit design and implementation for applications such as avionics, communications, computer vision, and power management.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
Greetings from IGeekS Technologies ….
We were humbled to receive your enquiry regarding your academic project. We assure you to give all kinds of guidance for you to successfully complete your project.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Academic Projects
As a part of our vision to provide a field experience to young graduates, we offering academic projects to MCA/B.Tech/BE/M.Tech/BCA students. Normally our way of project guidance will start with in-depth training. Why because unless and until a student know the technology, he cannot implement a project. We designed such courses based on industry requirements.
Placements
Our support never ends with training. We are maintaining a dedicated consulting division with 5 HR executives to assist our students to find good opportunities. Once a student finishes his course and project, immediately we will collect their profiles and will contact with the companies. Since January 2010, more than 450 students got placed with the help of our quality training, project assistance and placement support.
Facilities
• Project confirmation and completion certificate.
• Project base paper, synopsis and PPT.
• In-depth training by industry experts
• Project guidance from experienced people
• Regular seminars and group discussions
• Lab facility
• Good placement assistance
• A CD which contains all the required softwares and materials.
• Lab modules with 100s of examples to improve students programming skills.
Please visit our websites for further information:-
www.makefinalyearproject.com
www.igeekstechnoloiges.com
We look forward to have you in our office for a detailed technical discussion for in-depth understanding of the base paper and synopsis. Our training methodology includes to first prepare the candidates to the relevant technology used in the selected project and then start the project implementation; this gives the candidate the pre-requisite knowledge to understand not only the project but also the code in which the project is implemented.The program concludes by issuing of project completion certificate from our organization.
We attached the proposed project titles for the academic year 2015. Find the attachment. Select the titles we will send the synopsis and base paper...If have any own topic (base paper) pls send us.we will check and confirm the implementation.
We will explain the base paper and synopsis, for technical discussion or admission contact Mr. Nandu-9590544567.
This document presents a mini project on linear feedback shift registers (LFSRs). It describes how an 8-bit LFSR works using 8 D-flip flops connected in a chain with outputs XORed together. The LFSR generates a pseudo-random sequence that repeats after 255 cycles. It discusses the circuit, working, and timing diagrams of the 8-bit LFSR. Applications mentioned include random number generation, error detection/correction, and implementing cyclic redundancy checks for data transmission.
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLNaseer LoneRider
This is my Mini project. It is very clear and has lots of animation in it. If you like to know about booth algorithm and VHDL this the perfect presentation. Download it and see as SLIDE SHOW. You will enjoy more of my work, Give blessings.
Low power VLSI design has become an important discipline due to increasing device densities, operating frequencies, and proliferation of portable electronics. Power dissipation, which was previously neglected, is now a primary design constraint. There are several sources of power dissipation in CMOS circuits, including switching power due to charging and discharging capacitances, short-circuit power during signal transitions, and leakage power from subthreshold and gate leakage currents. Designers have some control over power consumption by optimizing factors such as activity levels, clock frequency, supply voltage, transistor sizing and architecture.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
A REVIEW OF LOW POWERAND AREA EFFICIENT FSM BASED LFSR FOR LOGIC BISTjedt_journal
The document discusses techniques for implementing low power and area efficient built-in self-test circuits using finite state machine (FSM) based linear feedback shift registers (LFSRs). It proposes an FSM based LFSR that combines random injection and bipartite LFSR techniques to generate test patterns with reduced switching activity. Synthesis results show the proposed FSM based LFSR achieves up to 15% power reduction and optimal area overhead compared to conventional test pattern generators.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Two innovative high-speed low power parallel 8-bit counter architectures are proposed. Then, High speed 8-bit frequency divider circuits using the proposed architectures are realized. The proposed parallel counter architectures consist of two sections – The Counting Path and the State Excitation Module. The counting path consists of three counting modules in which the first module (basic module) generates future states for the two remaining counting modules. The State Excitation Module decodes the count states of the basic module and carries this decoding over clock cycles through pipelined DFF to trigger the subsequent counting modules. The existing 8-bit parallel counter architecture [1] consumed a total transistor count of 442 whereas the proposed parallel counters consumed only 274 transistors. The power dissipation of the existing parallel counter architecture and the proposed parallel counter architecture were 4.21mW (PINT) and 3.60mW (PINT) respectively at 250MHz. The worst case delay observed for the 8-bit counter using existing parallel counter architecture [1] and the proposed parallel counter architectures were 7.481ns, 6.737ns and 6.677ns respectively using Altera Quartus II. A reduction in area (transistor count) by 27.45% and a reduction in power dissipation by 16.28% are achieved for the frequency dividers using proposed counter architectures. Also a reduction in delay by 10.75% and 7.62% is achieved for the 8-bit frequency divider circuits using proposed counter methods I & II respectively.
Iaetsd design and implementation of multiple sic vectorsIaetsd Iaetsd
This document discusses the design and implementation of multiple single input change (MSIC) vectors for test pattern generation in built-in self-test (BIST) schemes. It proposes using a reconfigurable Johnson counter and scalable SIC counter to generate minimum transition sequences. Test patterns generated using this multiple SIC approach are applied to ISCAS benchmark circuits. Simulation results show the functionality of the proposed pattern generator and its ability to achieve high fault coverage comparable to primary test patterns.
IRJET - Low Power M-Sequence Code Generator using LFSR for Body Sensor No...IRJET Journal
The document describes a proposed low power m-sequence code generator using a linear feedback shift register (LFSR) for body sensor node applications. An LFSR generates pseudo-random binary sequences through a linear feedback function combining bits in the shift register. The document evaluates different designs for the XOR gates used in the feedback function, finding a transmission gate based design consumes significantly less power than other designs. It then proposes a 7-bit m-sequence code generator using a 3-stage LFSR with XOR gates in the feedback loop for low power consumption, suitable for use in wireless body sensor nodes.
This document discusses a proposed Random Single Input Change (RSIC) test sequence generation circuit to reduce power consumption during testing of integrated circuits. The circuit consists of a shift register, counter, and XOR gates. It generates test vectors that have high correlation and only a single input change between adjacent vectors. This helps lower the switching activity within the circuit-under-test, reducing dynamic power consumption. The document presents the circuit design in DSCH and Cadence simulation tools. It provides power dissipation values for the circuit components and an overall power of 213.034mW for the RSIC circuit. The results indicate the RSIC approach can help reduce testing power consumption.
This document presents a proposed aging-aware reliable multiplier design with an adaptive hold logic (AHL) circuit. The multiplier uses a variable-latency technique and can adjust the AHL circuit to achieve reliable operation under negative bias temperature instability and positive bias temperature instability effects, which degrade transistor speed over time. The AHL circuit can determine if an input pattern requires one or two clock cycles to complete, and can adjust its judging criteria to minimize performance degradation from aging. Experimental results on 16x16 and 32x32 column-bypassing and row-bypassing multipliers show the proposed design achieves significant performance improvements compared to fixed-latency designs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of low power divider techniques using radixeSAT Journals
This document summarizes a research paper on implementing low power divider techniques using radix-8 division. It describes the design of a radix-8 divider that aims to reduce energy dissipation without penalizing latency. The algorithm and implementation of the divider are explained. Several low power techniques are then applied, including switching off inactive blocks, retiming the recurrence, reducing transitions in multiplexers, changing the redundant representation, partitioning the selection function, and modifying the conversion and rounding process. Applying these techniques can reduce energy dissipation by up to 70% compared to a standard implementation. The performance of the radix-8 divider is also compared to a radix-4 divider and one using overlapped radix-2 stages.
Design of 16 bit low power processor using clock gating technique 2-3IAEME Publication
This document summarizes a research paper that presents the design of a 16-bit low power processor using clock gating technique. It describes how clock gating works to reduce power by disabling the clock signal to idle components. The paper outlines the design of a 16-bit RISC processor architecture and instruction format. Clock gating is applied at the gate and register transfer levels by inserting AND gates to selectively disable clocks. Simulation results show the processor executing sample instructions and a 23.15% reduction in total power is achieved through clock gating.
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction...IJECEIAES
To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 µW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 µW while CVSL shows total power consumption of 18.94 µW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
Modeling & Simulation of PMSM Drives with Fuzzy Logic ControllerIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Controller Design and Load Frequency Control for Single Area Power System wit...IJERA Editor
The document presents a load frequency control technique for a single area power system using model order reduction. It first describes the modeling of a single area power system as a third order transfer function. It then uses Routh approximation to reduce this to a second order system without significantly changing the dynamic behavior. An internal model control approach is also presented to design a PID controller for improved load disturbance rejection. Simulation results show that the step response of the original third order system matches well with that of the reduced second order system, validating the model order reduction technique. The reduced order model enables simpler controller design while maintaining good dynamic characteristics.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping ...IOSR Journals
This document proposes a technique called a bit-swapping linear feedback shift register (BS-LFSR) to reduce average and peak power in built-in self-tests (BISTs). The BS-LFSR swaps the values of two cells in an LFSR based on the value of a third cell, reducing transitions by 50% compared to a standard LFSR. It is combined with an algorithm that orders check cells to further reduce average and peak power during testing. Experimental results on benchmark circuits show up to 65% reduction in average power and 55% reduction in peak power with little impact on fault coverage or test time.
An approach to Measure Transition Density of Binary Sequences for X-filling b...IJECEIAES
Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.
Optimum capacity allocation of distributed generation units using parallel ps...eSAT Journals
Abstract This paper proposes the application of Parallel Particle Swarm Optimization (PPSO) technique to find the optimal sizing of multiple DG(Distributed Generation) units in the radial distribution network by reduction in real power losses and enhancement in voltage profile. Message passing interface (MPI) is used for the parallelization of PSO. The initial population of PSO algorithm has been divided between the processors at run time. The proposed technique is tested on standard 123-bus test system and the obtained results show that the simulation time is significantly reduced and is concluded that parallelization helps in enhancing the performance of basic PSO. The procedure has been implemented in an environment in which OpenDSS (Open Distribution System Simulator) is driven from MATLAB. An adaptive weight particle swarm optimization algorithm has been developed in MATLAB , parallelization is achieved using MATLABMPI and the unbalanced three-phase distribution load flow (DLF) has been performed using Electric Power Research Institute’s (EPRI) open source tool OpenDSS. Index Terms: Distributed Generation, Message Passing Interface, Optimal Placement, Parallel Particle Swarm Optimisation
Similar to Low power test pattern generation for bist applications (20)
Mechanical properties of hybrid fiber reinforced concrete for pavementseSAT Journals
Abstract
The effect of addition of mono fibers and hybrid fibers on the mechanical properties of concrete mixture is studied in the present
investigation. Steel fibers of 1% and polypropylene fibers 0.036% were added individually to the concrete mixture as mono fibers and
then they were added together to form a hybrid fiber reinforced concrete. Mechanical properties such as compressive, split tensile and
flexural strength were determined. The results show that hybrid fibers improve the compressive strength marginally as compared to
mono fibers. Whereas, hybridization improves split tensile strength and flexural strength noticeably.
Keywords:-Hybridization, mono fibers, steel fiber, polypropylene fiber, Improvement in mechanical properties.
Material management in construction – a case studyeSAT Journals
Abstract
The objective of the present study is to understand about all the problems occurring in the company because of improper application
of material management. In construction project operation, often there is a project cost variance in terms of the material, equipments,
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if the material management is not properly managed it will create a project cost variance. Project cost can be controlled by taking
corrective actions towards the cost variance. Therefore a methodology is used to diagnose and evaluate the procurement process
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and improvement was proposed and tested in selected projects. The results obtained show that the main problem of procurement is
related to schedule delays and lack of specified quality for the project. To prevent this situation it is often necessary to dedicate
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procurement process. These helped to eliminate the root causes for many types of problems that were detected.
Managing drought short term strategies in semi arid regions a case studyeSAT Journals
Abstract
Drought management needs multidisciplinary action. Interdisciplinary efforts among the experts in various fields of the droughts
prone areas are helpful to achieve tangible and permanent solution for this recurring problem. The Gulbarga district having the total
area around 16, 240 sq.km, and accounts 8.45 per cent of the Karnataka state area. The district has been situated with latitude 17º 19'
60" North and longitude of 76 º 49' 60" east. The district is situated entirely on the Deccan plateau positioned at a height of 300 to
750 m above MSL. Sub-tropical, semi-arid type is one among the drought prone districts of Karnataka State. The drought
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Keywords: Drought, South-West monsoon, Semi-Arid, Rainfall, Strategies etc.
Life cycle cost analysis of overlay for an urban road in bangaloreeSAT Journals
Abstract
Pavements are subjected to severe condition of stresses and weathering effects from the day they are constructed and opened to traffic
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bituminous pavement in an urban road in Bangalore. Along with this, Life cycle cost analyses at these sections are done by Net
Present Value (NPV) method to identify the most feasible option. The results show that though the initial cost of construction of
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Laboratory studies of dense bituminous mixes ii with reclaimed asphalt materialseSAT Journals
Abstract
The issue of growing demand on our nation’s roadways over that past couple of decades, decreasing budgetary funds, and the need to
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are today’s burning issue and has become the purpose of the study.
In the present study, the samples of existing bituminous layer materials were collected from NH-48(Devahalli to Hassan) site.The
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RAP material was blended with virgin aggregate such that all specimens tested for the, Dense Bituminous Macadam-II (DBM-II)
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Laboratory results and analysis showed the use of recycled materials showed significant variability in Marshall Stability, and the
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methodology, the reduction in the total cost is 19%, 30%, comparing with the virgin mixes.
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Laboratory investigation of expansive soil stabilized with natural inorganic ...eSAT Journals
This document summarizes a study on stabilizing expansive black cotton soil with the natural inorganic stabilizer RBI-81. Laboratory tests were conducted to evaluate the effect of RBI-81 on the soil's engineering properties. The tests showed that with 2% RBI-81 and 28 days of curing, the unconfined compressive strength increased by around 250% and the CBR value improved by approximately 400% compared to the untreated soil. Overall, the study found that RBI-81 effectively improved the strength properties of the black cotton soil and its suitability as a soil stabilizer was supported.
Influence of reinforcement on the behavior of hollow concrete block masonry p...eSAT Journals
Abstract
Reinforced masonry was developed to exploit the strength potential of masonry and to solve its lack of tensile strength. Experimental
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non-linear finite elements (FE) model based on the micro-modeling approach is developed for both unreinforced and reinforced
masonry prisms using ANSYS (14.5). The proposed FE model uses multi-linear stress-strain relationships to model the non-linear
behavior of hollow concrete block, mortar, and grout. Willam-Warnke’s five parameter failure theory has been adopted to model the
failure of masonry materials. The comparison of the numerical and experimental results indicates that the FE models can successfully
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Keywords: Structural masonry, Hollow concrete block prism, grout, Compression failure, Finite element method,
Numerical modeling.
Influence of compaction energy on soil stabilized with chemical stabilizereSAT Journals
This document summarizes a study on the influence of compaction energy on soil stabilized with a chemical stabilizer. Laboratory tests were conducted on locally available loamy soil treated with a patented polymer liquid stabilizer and compacted at four different energy levels. The study found that increasing the compaction effort increased the density of both untreated and treated soil, but the rate of increase was lower for stabilized soil. Treating the soil with the stabilizer improved its unconfined compressive strength and resilient modulus, and reduced accumulated plastic strain, with these properties further improved by higher compaction efforts. The stabilized soil exhibited strength and performance benefits compared to the untreated soil.
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Abstract
The study demonstrate the potentiality of satellite remote sensing technique for the generation of baseline information on forest types
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forest division is 5814Sq.Kms analysis of the satellite data in the study area reveals that about 84% of the total area is Covered by
crop land, 1.778% of the area is covered by dry deciduous forest, 1.38 % of mixed plantation, which is very threatening to the
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and exact condition of the trees can be observed and necessary precautions can be taken for future plantation works in an appropriate
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Factors influencing compressive strength of geopolymer concreteeSAT Journals
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NaOH to sodium silicate (Na2SiO3) 1, 1.5, 2 and 2.5, alkaline liquid to fly ash ratio 0.35 and 0.40 and replacement of water in
Na2SiO3 solution by 10%, 20% and 30% were used in the present study. The test results indicated that the highest compressive
strength 54 MPa was observed for 16M of NaOH, ratio of NaOH to Na2SiO3 2.5 and alkaline liquid to fly ash ratio of 0.35. Lowest
compressive strength of 27 MPa was observed for 8M of NaOH, ratio of NaOH to Na2SiO3 is 1 and alkaline liquid to fly ash ratio of
0.40. Alkaline liquid to fly ash ratio of 0.35, water replacement of 10% and 30% for 8 and 16 molarity of NaOH and has resulted in
compressive strength of 36 MPa and 20 MPa respectively. Superplasticiser dosage of 2 % by weight of fly ash has given higher
strength in all cases.
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Experimental investigation on circular hollow steel columns in filled with li...eSAT Journals
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thickness. Specimens were tested separately after adopting Taguchi’s L9 (Latin Squares) Orthogonal array in order to save the initial
experimental cost on number of specimens and experimental duration. Analysis was carried out using ANN (Artificial Neural
Network) technique with the assistance of Mini Tab- a statistical soft tool. Comparison for predicted, experimental & ANN output is
obtained from linear regression plots. From this research study, it can be concluded that *Cross sectional area of steel tube has most
significant effect on ultimate load carrying capacity, *as length of steel tube increased- load carrying capacity decreased & *ANN
modeling predicted acceptable results. Thus ANN tool can be utilized for predicting ultimate load carrying capacity for composite
columns.
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Evaluation of punching shear in flat slabseSAT Journals
Abstract
Flat-slab construction has been widely used in construction today because of many advantages that it offers. The basic philosophy in
the design of flat slab is to consider only gravity forces; this method ignores the effect of punching shear due to unbalanced moments
at the slab column junction which is critical. An attempt has been made to generate generalized design sheets which accounts both
punching shear due to gravity loads and unbalanced moments for cases (a) interior column; (b) edge column (bending perpendicular
to shorter edge); (c) edge column (bending parallel to shorter edge); (d) corner column. These design sheets are prepared as per
codal provisions of IS 456-2000. These design sheets will be helpful in calculating the shear reinforcement to be provided at the
critical section which is ignored in many design offices. Apart from its usefulness in evaluating punching shear and the necessary
shear reinforcement, the design sheets developed will enable the designer to fix the depth of flat slab during the initial phase of the
design.
Keywords: Flat slabs, punching shear, unbalanced moment.
Evaluation of performance of intake tower dam for recent earthquake in indiaeSAT Journals
Abstract
Intake towers are typically tall, hollow, reinforced concrete structures and form entrance to reservoir outlet works. A parametric
study on dynamic behavior of circular cylindrical towers can be carried out to study the effect of depth of submergence, wall thickness
and slenderness ratio, and also effect on tower considering dynamic analysis for time history function of different soil condition and
by Goyal and Chopra accounting interaction effects of added hydrodynamic mass of surrounding and inside water in intake tower of
dam
Key words: Hydrodynamic mass, Depth of submergence, Reservoir, Time history analysis,
Evaluation of operational efficiency of urban road network using travel time ...eSAT Journals
This document evaluates the operational efficiency of an urban road network in Tiruchirappalli, India using travel time reliability measures. Traffic volume and travel times were collected using video data from 8-10 AM on various roads. Average travel times, 95th percentile travel times, and buffer time indexes were calculated to assess reliability. Non-motorized vehicles were found to most impact reliability on one road. A relationship between buffer time index and traffic volume was developed. Finally, a travel time model was created and validated based on length, speed, and volume.
Estimation of surface runoff in nallur amanikere watershed using scs cn methodeSAT Journals
Abstract
The development of watershed aims at productive utilization of all the available natural resources in the entire area extending from
ridge line to stream outlet. The per capita availability of land for cultivation has been decreasing over the years. Therefore, water and
the related land resources must be developed, utilized and managed in an integrated and comprehensive manner. Remote sensing and
GIS techniques are being increasingly used for planning, management and development of natural resources. The study area, Nallur
Amanikere watershed geographically lies between 110 38’ and 110 52’ N latitude and 760 30’ and 760 50’ E longitude with an area of
415.68 Sq. km. The thematic layers such as land use/land cover and soil maps were derived from remotely sensed data and overlayed
through ArcGIS software to assign the curve number on polygon wise. The daily rainfall data of six rain gauge stations in and around
the watershed (2001-2011) was used to estimate the daily runoff from the watershed using Soil Conservation Service - Curve Number
(SCS-CN) method. The runoff estimated from the SCS-CN model was then used to know the variation of runoff potential with different
land use/land cover and with different soil conditions.
Keywords: Watershed, Nallur watershed, Surface runoff, Rainfall-Runoff, SCS-CN, Remote Sensing, GIS.
Estimation of morphometric parameters and runoff using rs & gis techniqueseSAT Journals
This document summarizes a study that used remote sensing and GIS techniques to estimate morphometric parameters and runoff for the Yagachi catchment area in India over a 10-year period. Morphometric analysis was conducted to understand the hydrological response at the micro-watershed level. Daily runoff was estimated using the SCS curve number model. The results showed a positive correlation between rainfall and runoff. Land use/land cover changes between 2001-2010 were found to impact estimated runoff amounts. Remote sensing approaches provided an effective means to model runoff for this large, ungauged area.
Effect of variation of plastic hinge length on the results of non linear anal...eSAT Journals
Abstract The nonlinear Static procedure also well known as pushover analysis is method where in monotonically increasing loads are applied to the structure till the structure is unable to resist any further load. It is a popular tool for seismic performance evaluation of existing and new structures. In literature lot of research has been carried out on conventional pushover analysis and after knowing deficiency efforts have been made to improve it. But actual test results to verify the analytically obtained pushover results are rarely available. It has been found that some amount of variation is always expected to exist in seismic demand prediction of pushover analysis. Initial study is carried out by considering user defined hinge properties and default hinge length. Attempt is being made to assess the variation of pushover analysis results by considering user defined hinge properties and various hinge length formulations available in literature and results compared with experimentally obtained results based on test carried out on a G+2 storied RCC framed structure. For the present study two geometric models viz bare frame and rigid frame model is considered and it is found that the results of pushover analysis are very sensitive to geometric model and hinge length adopted. Keywords: Pushover analysis, Base shear, Displacement, hinge length, moment curvature analysis
Effect of use of recycled materials on indirect tensile strength of asphalt c...eSAT Journals
Abstract
Depletion of natural resources and aggregate quarries for the road construction is a serious problem to procure materials. Hence
recycling or reuse of material is beneficial. On emphasizing development in sustainable construction in the present era, recycling of
asphalt pavements is one of the effective and proven rehabilitation processes. For the laboratory investigations reclaimed asphalt
pavement (RAP) from NH-4 and crumb rubber modified binder (CRMB-55) was used. Foundry waste was used as a replacement to
conventional filler. Laboratory tests were conducted on asphalt concrete mixes with 30, 40, 50, and 60 percent replacement with RAP.
These test results were compared with conventional mixes and asphalt concrete mixes with complete binder extracted RAP
aggregates. Mix design was carried out by Marshall Method. The Marshall Tests indicated highest stability values for asphalt
concrete (AC) mixes with 60% RAP. The optimum binder content (OBC) decreased with increased in RAP in AC mixes. The Indirect
Tensile Strength (ITS) for AC mixes with RAP also was found to be higher when compared to conventional AC mixes at 300C.
Keywords: Reclaimed asphalt pavement, Foundry waste, Recycling, Marshall Stability, Indirect tensile strength.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
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Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
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Low power test pattern generation for bist applications
1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 698
LOW POWER TEST PATTERN GENERATION FOR BIST
APPLICATIONS
Karthikkumar.B1
, Anusha.T2
, Dhanagopal.R3
1
ME (Applied Electronics), ECE, Jayaram College of Engineering and Technology, Trichy, India
2
ME (Applied Electronics), ECE, Jayaram College of Engineering and Technology, Trichy, India
3
Assistant Professor, ECE, Jayaram College of Engineering and Technology, Trichy, India
Abstract
This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change
(MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a
scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the
test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class
of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and
low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no
more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.
Keywords—Built-in self-test (BIST), low power, single-input change (SIC), test pattern generator (TPG)
-----------------------------------------------------------------------***-----------------------------------------------------------------------
1. INTRODUCTION
BUILT-IN SELF-TEST (BIST) techniques can effectively
reduce the difficulty and complexity of VLSI testing, by
Introducing on-chip test hardware into the circuit-under-test
(CUT). In conventional BIST architectures, the linear feedback
Shift register (LFSR) is commonly used in the test pattern
Generators (tpgs) and output response analyzers. A major
Drawback of these architectures is that the pseudorandom
Patterns generated by the LFSR lead to significantly high
switching activities in the CUT [1], which can cause excessive
Power dissipation. They can also damage the circuit and reduce
Product yield and lifetime [2], [3]. In addition, the LFSR
Usually needs to generate very long pseudorandom sequences
In order to achieve the target fault coverage in nanometer
technology.
1.1 Prior Work
Several advanced BIST techniques have been studied and
applied. The first class is the LFSR tuning. Girard et al.
analyzed the impact of an LFSR‟s polynomial and seed
selection on the CUT‟s switching activity, and proposed a
method to select the LFSR seed for energy reduction [4].
The second class is low-power TPGs. One approach is to design
low-transition TPGs. Wang and Gupta used two LFSRs of
different speeds to control those inputs that have elevated
transition densities [5]. Corno et al. provided a low power TPG
based on the cellular automata to reduce the test power in
combinational circuits [6]. Another approach focuses on
modifying LFSRs. The scheme in [7] reduces the power in the
CUT in general and clock tree in particular. In [8], a low power
BIST for data path architecture is proposed, which is circuit
dependent. However, this dependency implies that no detecting
subsequences must be determined for each circuit test sequence.
Bonhomme et al. [9] used a clock gating technique where two
no overlapping clocks control the odd and even scan cells of the
scan chain so that the shift power dissipation is reduced by a
factor of two. The ring generator [10] can generate a single-
input change (SIC) sequence which can effectively reduce test
power. The third approach aims to reduce the dynamic power
dissipation during scan shift through gating of the outputs of a
portion of the scan cells. Bhunia et al. [11] inserted blocking
logic into the stimulus path of the scan flip-flops to prevent the
propagation of the scan ripple effect to logic gates. The need for
transistors insertion, however, makes it difficult to use with
standard cell libraries that do not have power-gated cells. In
[12], the efficient selection of the most suitable subset of scan
cells for gating along with their gating values is studied.
The third class makes use of the prevention of pseudorandom
patterns that do not have new fault detecting abilities [13]–[15].
These architectures apply the minimum number of test vectors
required to attain the target fault coverage and therefore reduce
the power. However, these methods have high area overhead,
need to be customized for the CUT, and start with a specific
seed. Gerstendorfer et al. also proposed to filter out no detecting
patterns using gate-based blocking logics [16], which, however,
add significant delay in the signal propagation path from the
scan flip-flop to logic.
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 699
Several low-power approaches have also been proposed for
Scan-based BIST. The architecture in [17] modifies scan-path
Structures, and lets the CUT inputs remain unchanged during a
shift operation. Using multiple scan chains with many scan
enable (SE) inputs to activate one scan chain at a time, the TPG
proposed in [18] can reduce average power consumption during
scan-based tests and the peak power in the CUT. In [19], a
pseudorandom BIST scheme was proposed to reduce switching
activities in scan chains. Other approaches include LT-LFSR
[20], a low-transition random TPG [21], and the weighted
LFSR [22]. The TPG in [20] can reduce the transitions in the
scan inputs by assigning the same value to most neighboring
bits in the scan chain. In [21], power reduction is achieved by
increasing the correlation between consecutive test patterns.
The weighted LFSR in [22] decreases energy consumption and
increases fault coverage by adding weights to tune the
pseudorandom vectors for various probabilities.
2. PROPOSED MSIC-TPG SCHEME
Fig 1 Symbolic Representation of an MSIC Pattern
This section develops a TPG scheme that can convert an SIC
vector to unique low transition vectors for multiple scan chains.
First, the SIC vector is decompressed to its multiple
codeword‟s. Meanwhile, the generated codeword‟s will bit-
XOR with a same seed vector in turn. Hence, a test pattern with
similar test vectors will be applied to all scan chains. The
Proposed MSIC-TPG consists of an SIC generator, a seed
generator, an XOR gate network, and a clock and control block.
2.1 Test Pattern Generation Method
Assume there are m primary inputs (PIs) and M scan chains in a
full scan design, and each scan chain has l scan cells. Fig. 1(a)
shows the symbolic simulation for one generated pattern. The
vector generated by an m-bit LFSR with the primitive
polynomial can be expressed as S(t) = S0(t)S1(t)S2(t), . . . ,
Sm−1(t) (hereinafter referred to as the seed), and the vector
generated by an l-bit Johnson counter can be expressed as J (t)
= J0(t)J1(t)J2(t), . . . , Jl−1(t). In the first clock cycle, J = J0 J1
J2, . . . , Jl−1 will bit-XOR with S = S0S1S2, . . . , SM−1, and
the results X1Xl+1X2l+1, . . . , X(M−1)l+1 will be shifted into
M scan chains, respectively. In the second clock cycle, J = J0 J1
J2, . . . , Jl−1 will be circularly shifted as J = Jl−1 J0 J1, . . . ,
Jl−2, which will also bit-XOR with the seed S = S0S1S2, . . . ,
SM−1. The resulting X2Xl+2X2l+2, . . . , X(M−1)l+2 will be
shifted into M scan chains, respectively. After l clocks, each
scan chain will be fully loaded with a unique Johnson
codeword, and seed S0S1S2, . . . , Sm−1 will be applied to m
PIs. Since the circular Johnson counter can generate l unique
Johnson code words through circular shifting a Johnson vector,
the circular Johnson counter and XOR gates in Fig. 1 actually
constitute a linear sequential decompressor
2.2 Reconfigurable Johnson Counter
According to the different scenarios of scan length, this paper
develops two kinds of SIC generators to generate Johnson
vectors and Johnson code words, i.e., the reconfigurable
Johnson counter and the scalable SIC counter.
For a short scan length, we develop a reconfigurable Johnson
counter to generate an SIC sequence in time domain.
As shown in Fig. 2(a), it can operate in three modes.
1) Initialization: When RJ_Mode is set to 1 and Init is set to
logic 0, the reconfigurable Johnson counter will be initialized to
all zero states by clocking CLK2 more than l times.
2) Circular shift register mode: When RJ_Mode and Init are set
to logic 1, each stage of the Johnson counter will output a
Johnson codeword by clocking CLK2 l times.
3) Normal mode: When RJ_Mode is set to logic 0, the
reconfigurable Johnson counter will generate 2l unique SIC
vectors by clocking CLK2 2l times.
Fig.2 Reconfigurable Johnson Counter
3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 700
2.3 Scalable SIC Counter
When the maximal scan chain length l is much larger than the
scan chain number M, we develop an SIC counter named the
“scalable SIC counter.” As shown in Fig. 2(b), it contains a k-
bit adder clocked by the rising SE signal, a k-bit subtractor
clocked by test clock CLK2, an M-bit shift register clocked by
test clock CLK2, and k multiplexers. The value of k is the
integer of log2(l − M). The waveforms of the scalable SIC
counter are shown in Fig. 2(c). The k-bit adder is clocked by the
falling SE signal, and generates a new count that is the number
of 1s (0s) to fill into the shift register. As shown in Fig. 2(b), it
can operate in three modes
Fig 3 Scalable SIC Counter
1) If SE = 0, the count from the adder is stored to the k-bit
subtractor. During SE = 1, the contents of the k-bit subtractor
will be decreased from the stored count to all zeros gradually.
2) If SE = 1 and the contents of the k-bit subtractor are not all
zeros, M-Johnson will be kept at logic 1 (0).
3) Otherwise, it will be kept at logic 0 (1). Thus, the needed 1s
(0s) will be shifted into the M-bit shift register by clocking
CLK2 l times, and unique Johnson codeword‟s will be applied
into different scan chains.
For example, after full-scan design, ISCAS‟89 s13207 has 10
scan chains whose maximum scan length is 64. To implement a
scalable SIC counter as shown in Fig. 2(b), it only needs 6 D-
type flip-flops (DFFs) for the adder, 6 DFFs for the subtractor,
10 DFFs for a 10-bit shift register for 10 scan chains, 6
multiplexers, and additional 19 combinational logic gates. The
equivalent gates are 204 in total. For a 64-bit Johnson counter,
it needs 64 DFFs, which are about 428 equivalent gates. The
overhead of a MSIC-TPG can thus be effectively decreased by
using the scalable SIC counter..
2.4 MSIC-TPGs for Test-per-Clock Schemes
The MSIC-TPG for test-per-clock schemes is illustrated in Fig.
3(a). The CUT‟s PIs X1 − Xmn are arranged as an n ×m
SRAM-like grid structure. Each grid has a two-input XOR gate
whose inputs are tapped from a seed output and an output of the
Johnson counter. The outputs of the XOR gates are applied to
the CUT‟s PIs. A seed generator is an m-stage Conventional
LFSR, and operates at low frequency CLK1. The test procedure
is as follows.
1) The seed generator generates a new seed by clocking CLK1
one time.
2) The Johnson counter generates a new vector by clocking
CLK2 one time.
3) Repeat 2 until 2l Johnson vectors are generated.
4) Repeat 1–3 until the expected fault coverage or test length is
achieved.
Fig 4 MSIC-TPGs test-per-clock
2.4 MSIC-TPGs for Test-per-Scan Schemes
The MSIC-TPG for test-per-scan schemes is illustrated in Fig.
3(b). The stage of the SIC generator is the same as the
maximum scan length, and the width of a seed generator is not
smaller than the scan chain number. The inputs of the XOR
gates come from the seed generator and the SIC counter, and
their outputs are applied to M scan chains, respectively. The
outputs of the seed generator and XOR gates are applied to the
CUT‟s PIs, respectively. The test procedure is as follows.
1) The seed circuit generates a new seed by clocking CLK1 one
time.
2) RJ_Mode is set to “0”. The reconfigurable Johnson counter
will operate in the Johnson counter mode and generate a
Johnson vector by clocking CLK2 one time.
3) After a new Johnson vector is generated, RJ_Mode and Init
are set to 1. The reconfigurable Johnson counter operates as a
circular shift register, and generates l codewords by clocking
CLK2 l times. Then, a capture operation is inserted.
4) Repeat 2–3 until 2l Johnson vectors are generated.
5) Repeat 1–4 until the expected fault coverage or test length is
achieved.
4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 701
Fig 5 MSIC-TPGs Test-Per-Scan schemes
3. PRINCIPLE OF MSIC SEQUENCES
The main objective of the proposed algorithm is to reduce the
switching activity. In order to reduce the hardware overhead,
the linear relations are selected with consecutive vectors or
within a pattern, which can generate a sequence with a
sequential decompressed, facilitating hardware implementation.
Another requirement is that the MSIC sequence should not
contain any repeated test patterns, because repeated patterns
could prolong the test time and reduce test efficiency [5].
Finally, uniformly distributed patterns are desired to reduce the
test length (number of patterns required to achieve a target fault
coverage) [21]. This section aims to extract a class of test
sequences that meets these requirements.
3.1 Example
Suppose there are four scan chains whose lengths are 8 in a full-
scan design. The 8-bit Johnson codeword‟s and 4-bit (or more
bits) seeds can be used to generate an MSIC sequence.
A MSIC sequence with seed 01101 is
For (25 − 1) unique seeds, there are 31 such blocks. Therefore,
there are 16 × 31 = 496 unique patterns in this MSIC sequence.
Also, the transition between patterns X(t) and X(t+1) is one for
every scan chain, and transitions for scan chain 2 to scan in
“1001111” are two per clock. Seed “01101” is kept unchanged
for patterns X(1) to X(16).
4. PERFORMANCE ANALYSIS
To analyze the performance of the proposed MSIC-TPG,
Experiments on ISCAS‟85 benchmarks and standard full-scan
Designs of ISCAS‟89 benchmarks are conducted. The
performance Simulations are carried out with the Synopsys
Design Analyzer and Prime Power. Fault simulations are
carried Out with Synopsys Tetramax. Syntheses are carried out
with Nangate library based on 45-nm typical technology. The
testFrequency is 100 mhz, and the power supply voltage is 1.1
V. The test application method is test-per-clock for ISCAS‟85
Benchmarks and test-per-scan for ISCAS‟89 benchmarks. The
Number of scan chains is 10 for s13207 and s15850, and 20 For
s38417, s35932 and s38584.
4.1 Fault Coverage Comparison
The fault coverage‟s for ISCAS benchmarks with the MSIC-
TPG, the conventional LFSR, and the methods in [7] and [21].
In this table, the columns labeled SFC, TFC, and TL refer to the
stuck-at fault coverage, transition fault coverage, and test
length, respectively. The TFC values of this table correspond to
launch-on-shift test patterns. In order to achieve fair
comparisons, for ISCAS‟89 benchmarks, our TLs are chosen to
be the same as those in [7]. For the first three ISCAS‟85
benchmarks, our TLs are chosen according to [21]. The last two
ISCAS‟85 benchmarks are selected to have similar fault
coverage‟s as [7].
Compared with the conventional LFSR, the MSIC-TPG
achieves similar stuck-at fault coverage for ISCAS‟85
benchmarks and higher stuck-at fault coverage for ISCAS‟89
benchmarks except for s38417. It also achieves higher
transition fault coverage for both ISCAS‟85 and ISCAS‟89
benchmarks except for s35392. Compared to the LT-LFSR
method in [21], it can be seen from the ISCAS‟85 benchmarks
that, with the same TL, the MSIC-TPG achieves similar test
efficiency.
Compared to the TPG in [7], the results with ISCAS‟89
benchmarks show that, with the same TL, the MSIC-TPG has
higher efficiency, except for s38417. Note that, for ISCAS‟89
benchmarks, the results of our method and those of [21] in the
table should not be compared directly because of the different
TLs.
4.2 Average and Peak Power Reduction
The total and peak power reductions of CUTs with the MSIC-
TPG and with the LFSR-TPG, where columns labeled “Ptot”
and “Ppeak” refer to the CUT‟s total power and peak power
with the MSIC-TPG, respectively. Columns labeled “_Ptot” and
“_Ppeak” refer to the percentages of different methods‟ total
power reduction and peak power reduction with respect to the
LFSR method, respectively. The results of [25] are also
included for comparison. For ISCAS‟85 benchmarks, the
MSIC-TPG saves 25%–50.0% total power and 15.6%–32.6%
peak power against the conventional LFSR. All total power
reductions and peak power reductions are higher than those
with variable-length ring counter in [25].
For ISCAS‟89 benchmarks, the MSIC-TPG can save 21.38%–
34.52% total power and 3%–32.4% peak power against the
conventional LFSR. The total power reductions and peak power
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 702
reductions are not higher than those with the variable-length
ring counter in [25]. One reason for this is that the power
simulation results for the MSIC-TPG are with 45-nm
technology, whereas results in [25] are with 0.25-μm
technology. Experimental results show that leak power
contributes about 10% to total power with 45-nm technology,
but contributes little to total power with 0.18- or 0.25-μm
technology.
5. RESULTS
In this paper BIST will be used for generate the TEST
PATTERN GENERATION. To evaluate the proposed model,
the LFSR is used to measure power and area in this model we
are used Johnson counter, scalable SIC counter.
5.1 Simulation Procedure
5.1.1 Simulate Seed Generator
Step 1: Open the ModelSim SE 6.3f software and use the
browse button in the project location box to specify the location
of the directory that you created for the project. ModelSim uses
a working library to contain the information on the design in
progress; in the Default Library Name field we used the name
work. Click OK.
Step 2: Go to the Library window, select the pattern and right
click the pattern to simulate the program.
Step 3: Again go to the Library window, select the pattern and
right click that to add the wave. If enable the clock 2 we will
get test pattern output.
Step 4: Generate the seed generator value, enable the seed
generator value 01101 and then get output of seed generator. It
will be change until 8 bit and single input changes.
Fig 6 Output for pattern method
5.1.2 Find Fault Occurrence
Step 1: Go to the Library, select the Test Main. right click the
test main, to write the program and simulate.
Step 2: Opened simulated window add to wave. if fault value is
„0‟means fault is not enabled. If fault value „1‟ means fault
enabled and will be get different output
Fig 7 Output for testing method
5.1.3 Simulate Power and Area
Step 1: open the Xilinx ISE 13.2 software.
Step 2: open the new file, to write the program for power and
area and simulate
Design summary
Step 3: Finally get the output of total equivalent gate count
design is 7.216
6. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 703
Fig 8 Output of power and area
6. CONCLUSIONS
This paper has proposed a low-power test pattern generation
method that could be easily implemented by hardware. It also
developed a theory to express a sequence generated by linear
Sequential architectures, and extracted a class of SIC sequences
named MSIC. Analysis results showed that an MSIC sequence
had the favorable features of uniform distribution, low input
Transition density, and low dependency relationship between
the test length and the TPG‟s initial states. Combined with the
proposed reconfigurable Johnson counter or scalable SIC
counter, the MSIC-TPG can be easily implemented, and is
flexible to test-per-clock schemes and test-per-scan schemes.
For a test-per-clock scheme, the MSIC-TPG applies SIC
sequences to the cut with the SRAM like grid. For a test-per
scan scheme, the MSIC-TPG converts and sic vector to low
Transition vectors for all scan chains. Experimental results and
analysis results demonstrate that the MSIC-TPG is scalable to
scan length, and has negligible impact on the test overhead.
REFERENCES
[1]. Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang,
Kaile Gao, and Bin Liang” Test Patterns of Multiple SIC
Vectors: Theory and Application in BIST Schemes” IEEE
transactions on very large scale integration (vlsi) systems, vol.
21, no. 4, april 2013
[2]. A. Abu-Issa and S. Quigley, “Bit-swapping LFSR and
scan-chain ordering: A novel technique for peak- and average-
power reduction in scan-based BIST,” IEEE Trans. Comput.-
Aided Design Integr. Circuits Syst., vol. 28, no. 5, pp. 755–759,
May 2009.
[3]. Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S.
Pravossoudovitch, “A gated clock scheme for low power scan
testing of logic ICs or embedded cores,” in Proc. 10th Asian
Test Symp., Nov. 2001, pp. 253–258.