International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
The document proposes a novel approach for designing high speed carry select adders. It describes replacing conventional dual ripple carry adders in carry select adders with a single ripple carry adder and add-one circuit to reduce area. The proposed design is evaluated through Verilog simulation and synthesis using a 0.18um technology. Results show the proposed carry select adder achieves reduced delay and area compared to regular carry select adders.
Design & implementation of high speed carry select adderssingh7603
This document describes the design and implementation of a high-speed carry select adder. It begins with an introduction that discusses reducing area and power consumption in digital adders. It then defines a carry select adder and describes how it independently generates multiple carries to select from in order to reduce carry propagation delay. The document outlines the structure of a basic 16-bit carry select adder and describes replacing ripple carry adders with binary to excess-1 converters to further reduce area and power. It also proposes using D-latches instead to achieve lower delay and higher speeds. The document implements various adder designs in VHDL and verifies their operation through simulation and synthesis.
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
This document describes the design of a Parallel Self-Timed Adder (PASTA). PASTA is an asynchronous adder circuit that operates in parallel for bits that do not require carry propagation. It uses half adders and multiplexers in a regular structure with minimal interconnections. The document discusses the architecture and operation of PASTA through state diagrams. It also reviews related work on asynchronous and synchronous adder designs. Simulation results using MICROWIND and DSCH tools in 45nm CMOS technology verify the performance advantages of PASTA over existing asynchronous adders in terms of area, power, delay.
This document discusses using the Service-ORiented Computing EnviRonment (SORCER) platform for deterministic and stochastic optimization problems. It describes how global optimization algorithms VTDIRECT95 and QNSTOP were modified to run as optimization services on SORCER. As a case study, the EBF3PanelOpt framework for structural optimization of curvilinear aircraft panels was integrated with SORCER. This allowed the optimization problem to be solved in a distributed manner across computational resources for significantly faster objective function evaluations.
This document describes a bit-serial multiplier project implemented using Verilog HDL. It discusses bit-serial arithmetic and its advantages over parallel multipliers. The project involves designing and simulating a bit-serial multiplier using a Xilinx tool. The multiplier is tested to verify correct functionality.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
IRJET- MAC Unit by Efficient Grouping of Partial Products along with Circular...IRJET Journal
This document describes a proposed MAC (multiply and accumulate) unit design that aims to improve performance and reduce resource usage compared to conventional pipeline MAC unit designs. The proposed design uses Booth encoding to reduce the number of partial products, groups the partial products into blocks that are added using multi-operand adders, and implements circular convolution by rearranging the partial products. Simulation results show that the proposed design achieves higher performance and lower resource usage than conventional pipeline and redundant carry-save MAC unit designs. The design is synthesized on an Altera Stratix III FPGA to take advantage of fast carry chains.
The document proposes a novel approach for designing high speed carry select adders. It describes replacing conventional dual ripple carry adders in carry select adders with a single ripple carry adder and add-one circuit to reduce area. The proposed design is evaluated through Verilog simulation and synthesis using a 0.18um technology. Results show the proposed carry select adder achieves reduced delay and area compared to regular carry select adders.
Design & implementation of high speed carry select adderssingh7603
This document describes the design and implementation of a high-speed carry select adder. It begins with an introduction that discusses reducing area and power consumption in digital adders. It then defines a carry select adder and describes how it independently generates multiple carries to select from in order to reduce carry propagation delay. The document outlines the structure of a basic 16-bit carry select adder and describes replacing ripple carry adders with binary to excess-1 converters to further reduce area and power. It also proposes using D-latches instead to achieve lower delay and higher speeds. The document implements various adder designs in VHDL and verifies their operation through simulation and synthesis.
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
This document describes the design of a Parallel Self-Timed Adder (PASTA). PASTA is an asynchronous adder circuit that operates in parallel for bits that do not require carry propagation. It uses half adders and multiplexers in a regular structure with minimal interconnections. The document discusses the architecture and operation of PASTA through state diagrams. It also reviews related work on asynchronous and synchronous adder designs. Simulation results using MICROWIND and DSCH tools in 45nm CMOS technology verify the performance advantages of PASTA over existing asynchronous adders in terms of area, power, delay.
This document discusses using the Service-ORiented Computing EnviRonment (SORCER) platform for deterministic and stochastic optimization problems. It describes how global optimization algorithms VTDIRECT95 and QNSTOP were modified to run as optimization services on SORCER. As a case study, the EBF3PanelOpt framework for structural optimization of curvilinear aircraft panels was integrated with SORCER. This allowed the optimization problem to be solved in a distributed manner across computational resources for significantly faster objective function evaluations.
This document describes a bit-serial multiplier project implemented using Verilog HDL. It discusses bit-serial arithmetic and its advantages over parallel multipliers. The project involves designing and simulating a bit-serial multiplier using a Xilinx tool. The multiplier is tested to verify correct functionality.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
IRJET- MAC Unit by Efficient Grouping of Partial Products along with Circular...IRJET Journal
This document describes a proposed MAC (multiply and accumulate) unit design that aims to improve performance and reduce resource usage compared to conventional pipeline MAC unit designs. The proposed design uses Booth encoding to reduce the number of partial products, groups the partial products into blocks that are added using multi-operand adders, and implements circular convolution by rearranging the partial products. Simulation results show that the proposed design achieves higher performance and lower resource usage than conventional pipeline and redundant carry-save MAC unit designs. The design is synthesized on an Altera Stratix III FPGA to take advantage of fast carry chains.
This document presents a GPU-accelerated algorithm for solving the Group Steiner Problem (GSP) which arises in routing phases of VLSI circuit design. The algorithm uses a depth-bounded heuristic to construct approximate minimum-cost Steiner trees in parallel using CUDA-aware MPI. Evaluation on a supercomputer shows the parallel implementation achieves up to 302x speedup over serial algorithms and scales well with problem size and processor count.
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ul...JAYAPRAKASH JPINFOTECH
This paper presents an efficient dual-clock VLSI design for sample adaptive offset (SAO) estimation in H.265 video encoding. The design processes statistics collection at a high clock speed and parameter decision at a low clock speed, reducing area by 56%. Algorithm and architecture optimizations including coarse range selection and accumulator bit width reduction achieve a further 25% area reduction. The proposed design is capable of 8k 120-frames/second encoding while occupying 51k logic gates, only one-third the area of state-of-the-art implementations. It was modeled and analyzed using Modelsim and Xilinx ISE software.
This document discusses the Ark Loader Quantum, a system for constructing green energy products. It describes the loading process, which involves understanding transit requirements and how the load is tiered and layered. Time and motion standards like Black Jack and Bushy Run are used as metrics. The document also mentions emulating an assembler to construct a scalable manifold design that can speed up assembly through increased speed and performance. Precision, throughput, machine output, and other metrics are evaluated. Over 264 hours were spent emulating the loading process from pre-developed benchmarks and standards. A mathematical model was constructed by developing a conversion hypothesis as part of modeling the overall Ark system.
A Virtual Machine Placement Algorithm for Energy Efficient Cloud Resource Res...SuvomDas
In this slide, we are going to discuss a new graph colouring model for advance resource reservation with minimum energy consumption in heterogeneous IaaS cloud data centres. We will start with an exact integer linear programming (ILP) formulation which generalises the graph colouring problem mathematically and follow with a Energy Efficient Graph Pre colouring (EEGP) heuristic to address the scalability and to reduce convergence times. The results of performance evaluation and comparisons of EEGP with the exact algorithm will demonstrate the efficiency of EEGP for the energy efficient advance resource reservation problem.
We will see the efficiency of the EEGP algorithm by comparing it with the exact integer linear programming solution
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Time and Reliability Optimization Bat Algorithm for Scheduling Workflow in CloudIRJET Journal
This document describes using a meta-heuristic optimization algorithm called the Bat Algorithm (BA) to schedule workflows in cloud computing environments. The BA is applied to optimize a multi-objective function that minimizes workflow execution time and maximizes reliability while keeping costs within a user-specified budget. The BA is compared to a basic randomized evolutionary algorithm (BREA) that uses greedy approaches. Experimental results show the BA performs better by finding schedules that have lower execution times and higher reliability within the given budget constraints. The BA is well-suited for this problem because it can efficiently search large solution spaces and automatically focus on optimal regions like other metaheuristics.
IRJET- Advance Approach for Load Balancing in Cloud Computing using (HMSO) Hy...IRJET Journal
This document proposes a new hybrid multi-swarm optimization (HMSO) algorithm for load balancing in cloud computing. It aims to minimize response time and costs while improving resource utilization and customer satisfaction. The HMSO algorithm uses multi-level particle swarm optimization to find an optimal resource allocation solution. Simulation results show that the proposed HMSO technique reduces response time and datacenter costs compared to other algorithms. It also achieves a more balanced load distribution across resources.
implementation and comparision of effective area efficient architecture for CSLAvenkatesh nayakoti
This document presents a modified carry select adder (CSLA) architecture to improve efficiency over a regular CSLA. The modified design replaces one of the ripple carry adders in the CSLA with a binary-excess-1 converter to reduce the number of gates. Simulation results show the modified 16-bit CSLA has fewer gates and offers advantages of lower area, power and complexity compared to a regular CSLA design. The modified architecture provides an efficient alternative for low area and low power VLSI implementations.
Performance Analysis and Comparison of Transmission Line Varying the Capacito...ijtsrd
In this paper, performance analysis of transmission line 11 KV with thyristor controlled series capacitor providing stability and power enhancement under the application of PI and PID controllers is compared after varying the capacitance of transmission line capacitor. Simulation results of uncompensated and also for compensated transmission line of 11 KV are compared with PI and PID controllers working with the transmission line system for improving the real power as well as reactive power in the supportive MATLAB environment self tuning is applied through MATLAB PID TUNER for both PID and PI controllers. Sameer Khan | Dr. Aziz Ahmad "Performance Analysis and Comparison of Transmission Line (Varying the Capacitor Value) with (PI and PID) Controllers using TCSC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-2 , February 2021, URL: https://www.ijtsrd.com/papers/ijtsrd38401.pdf Paper Url: https://www.ijtsrd.com/engineering/electrical-engineering/38401/performance-analysis-and-comparison-of-transmission-line-varying-the-capacitor-value-with-pi-and-pid-controllers-using-tcsc/sameer-khan
GRAPH MATCHING ALGORITHM FOR TASK ASSIGNMENT PROBLEMIJCSEA Journal
Task assignment is one of the most challenging problems in distributed computing environment. An optimal task assignment guarantees minimum turnaround time for a given architecture. Several approaches of optimal task assignment have been proposed by various researchers ranging from graph partitioning based tools to heuristic graph matching. Using heuristic graph matching, it is often impossible to get optimal task assignment for practical test cases within an acceptable time limit. In this paper, we have parallelized the basic heuristic graph-matching algorithm of task assignment which is suitable only for cases where processors and inter processor links are homogeneous. This proposal is a derivative of the basic task assignment methodology using heuristic graph matching. The results show that near optimal assignments are obtained much faster than the sequential program in all the cases with reasonable speed-up.
White paper: How to build a real-time vehicle route optimiserPhilip Welch
This document discusses the development of a real-time vehicle route optimization system called ODL Live. It highlights 5 key technical challenges addressed: 1) Using incremental processing to optimize routes in real-time. 2) Mapping real-time problems to static problems that can be solved periodically. 3) Simulating historic data to accurately test the system. 4) Estimating accurate travel times using free map data. 5) Adapting the system to a cloud-based architecture. Addressing these challenges was necessary to build a system that can efficiently optimize routes in real-time as new information is received.
ANSYS SCADE Usage for Unmanned Aircraft VehiclesAnsys
SCADE on-board the UAS P.1HH HammerHead
The Use of SCADE to develop the P.1HH Vehicle Control & Management System (Integrated Modular Avionics System) greatly reduced development time and effort.
Learn more about ANSYS SCADE Solutions for Aerospace & Defense http://bit.ly/1EdcsOJ
SparkNet implements a scalable, distributed algorithm to train deep neural networks that can be applied to existing batch processing frameworks like MapReduce and Spark.
Work by researchers at UC Berkeley.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Research Summary: Scalable Algorithms for Nearest-Neighbor Joins on Big Traje...Alex Klibisz
Research summary for my STAT645 course fall 2016. Paper Scalable Algorithms for Nearest-Neighbor Joins on Big Trajectory Data by Fang, Cheng, Tang, Maniu, Yang. http://ieeexplore.ieee.org/document/7498408/
A Study on Video Steganographic Techniquesijceronline
Data hiding techniques have taken important role with the rapid growth of intensive transfer of multimedia content and secret communications. The method of Steganography is used to share the data secretly and securely. It is the science of embedding secret information into the cover media with the modification to the cover image, which cannot be easily identified by human eyes. Steganography algorithms can be applied in audio, video and image file. Hiding secret information in video file is known as video steganography. Video Steganography means hiding a secret message that can be either a secret text message or an image within a larger one in such a way that just by looking at it, an unwanted person cannot detect the presence of any hidden message. For hiding secret information in the video, there are many Steganography techniques which are further explained in this paper along with some of the research works done in some fields under video steganography by some authors. The paper describes the progress in the field of video Steganography and intends to give the comparison between its different uses and techniques
Rocker arms are part of the valve-actuating mechanism. A rocker arm is designed to pivot on a pivot
pin or shaft that is secured to a bracket. The bracket is mounted on the cylinder head. One end of a
rocker arm is in contact with the top of the valve stem, and the other end is actuated by the camshaft.
In installations where the camshaft is located below the cylinder head, the rocker arms
are actuated by pushrods. The lifters have rollers which are forced by the valve springs to follow the
profiles of the cams. Failure of rocker arm is a measure concern as it is one of the important
components of push rod IC engines.Present work finds the various stresses under extreme load
condition. For this we are modeling the arm using design software and the stressed regions are
found out usingAnsys software. Here in this thesis we are observing that by changing different
materials how the stresses are varying in the rocker arm under extreme load condition. And after
comparing results we are proposing best suitable material for the rocker arm under extreme load conditions.
Study on groundwater quality in and around sipcot industrial complex, area cu...ijceronline
STATE INDUSTRIES PROMOTION CORPORATION OF TAMIL NADU(SIPCOT) cuddalore phase 1 has estabilished in 1984 at an extent of 518.79 acres. currently between 26 and 29 functional units are lie within phase1 of the industrial estates.At least 10 villages lie within or in the vicinity of the industrial complex. Till date no sites has been developed for secure storage of hazardous wastes generated by the industries in the estate. In absence of such facilities factories have dumped these wastes on neighbouring lands and in open pits. By the industries own admission,out of the 20 million litres of fresh water required by the companies, 18 million litres (90%) of the water is released back to their environment as toxic effluents.These poisons have leached into the ground water and contaminated the water resources of communities living around the factory. This study was carried out to asses the Quality of ground water in and around SIPCOT industrial complex in cuddalore district. The Quality was assessed in terms of physico chemical parameters.Ground water samples were collected from 30 locations in and around the study area and analyzed (APHA,1998) to know the present status of the Ground water Quality. The results were compared with standards prescribed by ISI 10500-91.It was found that the ground water was contaminated at few sampling locations.The remaining locations shows that the parameters are within the desirable limits and fit for drinking purpose
Development of a Cassava Starch Extraction Machineijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Strong (Weak) Triple Connected Domination Number of a Fuzzy Graphijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
This document presents a GPU-accelerated algorithm for solving the Group Steiner Problem (GSP) which arises in routing phases of VLSI circuit design. The algorithm uses a depth-bounded heuristic to construct approximate minimum-cost Steiner trees in parallel using CUDA-aware MPI. Evaluation on a supercomputer shows the parallel implementation achieves up to 302x speedup over serial algorithms and scales well with problem size and processor count.
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ul...JAYAPRAKASH JPINFOTECH
This paper presents an efficient dual-clock VLSI design for sample adaptive offset (SAO) estimation in H.265 video encoding. The design processes statistics collection at a high clock speed and parameter decision at a low clock speed, reducing area by 56%. Algorithm and architecture optimizations including coarse range selection and accumulator bit width reduction achieve a further 25% area reduction. The proposed design is capable of 8k 120-frames/second encoding while occupying 51k logic gates, only one-third the area of state-of-the-art implementations. It was modeled and analyzed using Modelsim and Xilinx ISE software.
This document discusses the Ark Loader Quantum, a system for constructing green energy products. It describes the loading process, which involves understanding transit requirements and how the load is tiered and layered. Time and motion standards like Black Jack and Bushy Run are used as metrics. The document also mentions emulating an assembler to construct a scalable manifold design that can speed up assembly through increased speed and performance. Precision, throughput, machine output, and other metrics are evaluated. Over 264 hours were spent emulating the loading process from pre-developed benchmarks and standards. A mathematical model was constructed by developing a conversion hypothesis as part of modeling the overall Ark system.
A Virtual Machine Placement Algorithm for Energy Efficient Cloud Resource Res...SuvomDas
In this slide, we are going to discuss a new graph colouring model for advance resource reservation with minimum energy consumption in heterogeneous IaaS cloud data centres. We will start with an exact integer linear programming (ILP) formulation which generalises the graph colouring problem mathematically and follow with a Energy Efficient Graph Pre colouring (EEGP) heuristic to address the scalability and to reduce convergence times. The results of performance evaluation and comparisons of EEGP with the exact algorithm will demonstrate the efficiency of EEGP for the energy efficient advance resource reservation problem.
We will see the efficiency of the EEGP algorithm by comparing it with the exact integer linear programming solution
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Time and Reliability Optimization Bat Algorithm for Scheduling Workflow in CloudIRJET Journal
This document describes using a meta-heuristic optimization algorithm called the Bat Algorithm (BA) to schedule workflows in cloud computing environments. The BA is applied to optimize a multi-objective function that minimizes workflow execution time and maximizes reliability while keeping costs within a user-specified budget. The BA is compared to a basic randomized evolutionary algorithm (BREA) that uses greedy approaches. Experimental results show the BA performs better by finding schedules that have lower execution times and higher reliability within the given budget constraints. The BA is well-suited for this problem because it can efficiently search large solution spaces and automatically focus on optimal regions like other metaheuristics.
IRJET- Advance Approach for Load Balancing in Cloud Computing using (HMSO) Hy...IRJET Journal
This document proposes a new hybrid multi-swarm optimization (HMSO) algorithm for load balancing in cloud computing. It aims to minimize response time and costs while improving resource utilization and customer satisfaction. The HMSO algorithm uses multi-level particle swarm optimization to find an optimal resource allocation solution. Simulation results show that the proposed HMSO technique reduces response time and datacenter costs compared to other algorithms. It also achieves a more balanced load distribution across resources.
implementation and comparision of effective area efficient architecture for CSLAvenkatesh nayakoti
This document presents a modified carry select adder (CSLA) architecture to improve efficiency over a regular CSLA. The modified design replaces one of the ripple carry adders in the CSLA with a binary-excess-1 converter to reduce the number of gates. Simulation results show the modified 16-bit CSLA has fewer gates and offers advantages of lower area, power and complexity compared to a regular CSLA design. The modified architecture provides an efficient alternative for low area and low power VLSI implementations.
Performance Analysis and Comparison of Transmission Line Varying the Capacito...ijtsrd
In this paper, performance analysis of transmission line 11 KV with thyristor controlled series capacitor providing stability and power enhancement under the application of PI and PID controllers is compared after varying the capacitance of transmission line capacitor. Simulation results of uncompensated and also for compensated transmission line of 11 KV are compared with PI and PID controllers working with the transmission line system for improving the real power as well as reactive power in the supportive MATLAB environment self tuning is applied through MATLAB PID TUNER for both PID and PI controllers. Sameer Khan | Dr. Aziz Ahmad "Performance Analysis and Comparison of Transmission Line (Varying the Capacitor Value) with (PI and PID) Controllers using TCSC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-2 , February 2021, URL: https://www.ijtsrd.com/papers/ijtsrd38401.pdf Paper Url: https://www.ijtsrd.com/engineering/electrical-engineering/38401/performance-analysis-and-comparison-of-transmission-line-varying-the-capacitor-value-with-pi-and-pid-controllers-using-tcsc/sameer-khan
GRAPH MATCHING ALGORITHM FOR TASK ASSIGNMENT PROBLEMIJCSEA Journal
Task assignment is one of the most challenging problems in distributed computing environment. An optimal task assignment guarantees minimum turnaround time for a given architecture. Several approaches of optimal task assignment have been proposed by various researchers ranging from graph partitioning based tools to heuristic graph matching. Using heuristic graph matching, it is often impossible to get optimal task assignment for practical test cases within an acceptable time limit. In this paper, we have parallelized the basic heuristic graph-matching algorithm of task assignment which is suitable only for cases where processors and inter processor links are homogeneous. This proposal is a derivative of the basic task assignment methodology using heuristic graph matching. The results show that near optimal assignments are obtained much faster than the sequential program in all the cases with reasonable speed-up.
White paper: How to build a real-time vehicle route optimiserPhilip Welch
This document discusses the development of a real-time vehicle route optimization system called ODL Live. It highlights 5 key technical challenges addressed: 1) Using incremental processing to optimize routes in real-time. 2) Mapping real-time problems to static problems that can be solved periodically. 3) Simulating historic data to accurately test the system. 4) Estimating accurate travel times using free map data. 5) Adapting the system to a cloud-based architecture. Addressing these challenges was necessary to build a system that can efficiently optimize routes in real-time as new information is received.
ANSYS SCADE Usage for Unmanned Aircraft VehiclesAnsys
SCADE on-board the UAS P.1HH HammerHead
The Use of SCADE to develop the P.1HH Vehicle Control & Management System (Integrated Modular Avionics System) greatly reduced development time and effort.
Learn more about ANSYS SCADE Solutions for Aerospace & Defense http://bit.ly/1EdcsOJ
SparkNet implements a scalable, distributed algorithm to train deep neural networks that can be applied to existing batch processing frameworks like MapReduce and Spark.
Work by researchers at UC Berkeley.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Research Summary: Scalable Algorithms for Nearest-Neighbor Joins on Big Traje...Alex Klibisz
Research summary for my STAT645 course fall 2016. Paper Scalable Algorithms for Nearest-Neighbor Joins on Big Trajectory Data by Fang, Cheng, Tang, Maniu, Yang. http://ieeexplore.ieee.org/document/7498408/
A Study on Video Steganographic Techniquesijceronline
Data hiding techniques have taken important role with the rapid growth of intensive transfer of multimedia content and secret communications. The method of Steganography is used to share the data secretly and securely. It is the science of embedding secret information into the cover media with the modification to the cover image, which cannot be easily identified by human eyes. Steganography algorithms can be applied in audio, video and image file. Hiding secret information in video file is known as video steganography. Video Steganography means hiding a secret message that can be either a secret text message or an image within a larger one in such a way that just by looking at it, an unwanted person cannot detect the presence of any hidden message. For hiding secret information in the video, there are many Steganography techniques which are further explained in this paper along with some of the research works done in some fields under video steganography by some authors. The paper describes the progress in the field of video Steganography and intends to give the comparison between its different uses and techniques
Rocker arms are part of the valve-actuating mechanism. A rocker arm is designed to pivot on a pivot
pin or shaft that is secured to a bracket. The bracket is mounted on the cylinder head. One end of a
rocker arm is in contact with the top of the valve stem, and the other end is actuated by the camshaft.
In installations where the camshaft is located below the cylinder head, the rocker arms
are actuated by pushrods. The lifters have rollers which are forced by the valve springs to follow the
profiles of the cams. Failure of rocker arm is a measure concern as it is one of the important
components of push rod IC engines.Present work finds the various stresses under extreme load
condition. For this we are modeling the arm using design software and the stressed regions are
found out usingAnsys software. Here in this thesis we are observing that by changing different
materials how the stresses are varying in the rocker arm under extreme load condition. And after
comparing results we are proposing best suitable material for the rocker arm under extreme load conditions.
Study on groundwater quality in and around sipcot industrial complex, area cu...ijceronline
STATE INDUSTRIES PROMOTION CORPORATION OF TAMIL NADU(SIPCOT) cuddalore phase 1 has estabilished in 1984 at an extent of 518.79 acres. currently between 26 and 29 functional units are lie within phase1 of the industrial estates.At least 10 villages lie within or in the vicinity of the industrial complex. Till date no sites has been developed for secure storage of hazardous wastes generated by the industries in the estate. In absence of such facilities factories have dumped these wastes on neighbouring lands and in open pits. By the industries own admission,out of the 20 million litres of fresh water required by the companies, 18 million litres (90%) of the water is released back to their environment as toxic effluents.These poisons have leached into the ground water and contaminated the water resources of communities living around the factory. This study was carried out to asses the Quality of ground water in and around SIPCOT industrial complex in cuddalore district. The Quality was assessed in terms of physico chemical parameters.Ground water samples were collected from 30 locations in and around the study area and analyzed (APHA,1998) to know the present status of the Ground water Quality. The results were compared with standards prescribed by ISI 10500-91.It was found that the ground water was contaminated at few sampling locations.The remaining locations shows that the parameters are within the desirable limits and fit for drinking purpose
Development of a Cassava Starch Extraction Machineijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Strong (Weak) Triple Connected Domination Number of a Fuzzy Graphijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
The Myth of Softening behavior of the Cohesive Zone Model Exact derivation of...ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Engendering sustainable socio-spatial environment for tourism activities in t...ijceronline
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The advantage of compressing the air is that it lets the engine squeeze more air into a cylinder, and more air means that more fuel can be added. Therefore, you get more power from each explosion in each cylinder. Here in this project we are designing the compressor wheel by using Pro-E and doing
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structural analysis has been carried out to investigate the stresses, strains and displacements of the blade. An attempt is also made to suggest the best material for an blade of a turbocharger by comparing the results obtained for different materials. Based on the results best material is recommended for the blade of a turbocharger
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This paper introduces two architectures for modulo 2n+1 adders. The first architecture is based on a sparse carry computation unit that computes only some carries, enabled by a new inverted circular idempotency property. This sparse approach reduces area and power compared to prior proposals while maintaining speed. The second architecture unifies the design of modulo 2n+1 and 2n-1 adders by showing 2n+1 addition can be treated as a subcase of 2n-1 addition with minor extra logic.
Design and Implementation of Different types of Carry skip adderIRJET Journal
The document describes the design and implementation of different types of carry skip adders. It begins with an introduction to carry skip adders and their advantages over other adder types in terms of speed, area usage, and transistor count. It then reviews existing carry skip adder designs and their limitations. A new design called the Common Boolean Logic (CBL) carry skip adder is proposed that aims to reduce area and power consumption by eliminating redundant adder cells through shared logic. Simulation results show that an 8-bit CBL carry skip adder has 64.6% lower power and 18.7% smaller area than a conventional carry skip adder. In conclusion, the CBL carry skip adder achieves improved performance and efficiency.
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Modified CSKA Application in the Floating Point Adder using Carry Skip Adder ...IJMTST Journal
In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy
consumption compared with the conventional one. The speed enhancement is achieved by applying
concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv
CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of
AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure maybe
realized with both fixed stage size and variable stage size styles, wherein the latter further improves the
speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed
structure, which lowers the power consumption without considerably impacting the speed, is presented.
This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling
further voltage reduction. The proposed structures are assessed by comparing their speed, power, and
energy parameters with those of other adders using a 45-nmstatic CMOS technology for a wide range of
supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and
38%improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In
addition, the power–delay product was the lowest among the structures considered in this paper, while its
energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with
considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency
CSKA reveal reduction in the power consumption compared with the latest works in this field while having
a reasonably high speed.
Design and Implementation of an Efficient Carry Skip AdderIRJET Journal
1) The document describes a design for an efficient 32-bit carry skip adder to achieve high speed and low area consumption.
2) It proposes using a Knowles adder in the middle stage and an optimized ripple carry adder instead of a Brent-Kung adder and normal RCA to improve speed and reduce area.
3) Simulation results show the proposed hybrid carry skip adder has a 38% reduced delay compared to a conventional carry skip adder and 16% reduced delay compared to a previous hybrid design. It is coded in Verilog and tested on a Xilinx FPGA.
Reverse converter design via parallel prefix adders novel components, methodo...jpstudcorner
This document proposes a new methodology for implementing reverse converters in residue number systems using parallel-prefix adders. Experimental results show that using parallel-prefix adders significantly increases speed but also area and power consumption, making the converters impractical. To address this, the document presents two new hybrid parallel-prefix adders that provide better tradeoffs between delay, power, and area. This new approach leads to reductions in power-delay product and improvements in area-time squared metrics compared to previous reverse converter designs.
Iaetsd multioperand redundant adders on fpg asIaetsd Iaetsd
This paper presents efficient implementations of redundant multi-operand adders on FPGAs. Previous work avoided redundant adders on FPGAs due to the efficient carry propagate adders (CPAs) and area overhead of redundant adders. The paper proposes carry-save compressor tree approaches that achieve fast critical paths independent of bit width with little to no area overhead compared to CPA trees. It presents a classic carry-save compressor tree and a novel linear array structure that efficiently uses fast carry chains. Compared to binary and ternary CPA trees, the approaches achieve speedups of up to 3.81 times for 64-bit width additions.
High –Speed Implementation of Design and Analysis by Using Parallel Prefix Ad...IOSRJECE
The binary adder is the critical element in most digital circuit designs including the digital signal processors (DSP) and microprocessor data unit path. As such as extensive research continues to be focused on improving the power, delay, improvement of the adder. The design and analysis of the parallel prefix adders (carry select adders) is to be implemented by using Verilog. In VLSI implementations, parallel prefix adders are very high speed performance. Binary adders are one of the most essential logic elements within a digital system. Therefore, binary addition is essential that any improvement in binary addition can result in a performance boost for any computing system and hence, help improve the performance of the entire system. Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. This paper investigates (the Kogge-Stone, sparse Kogge-Stone, Ladner fischer adder, Brent-Kung adder) and compares them to the simple Ripple Carry Adder (RCA) for high number of binary bits.
Review on optimized area,delay and power efficient carry select adder using n...IRJET Journal
This document discusses optimized area, delay, and power efficient carry select adders using NAND gates. Carry select adders are commonly used fast adders but require more area due to using two ripple carry adders and a multiplexer. The proposed design aims to significantly reduce area, power, and redundant logic in carry select adders by developing a new logic formulation technique using only NAND gates. NAND gates have advantages including lower delay than NOR gates, easier fabrication, and better power performance. The design aims to optimize area, delay, and power over conventional carry select adder designs.
Design and implementation of Parallel Prefix Adders using FPGAsIOSR Journals
Abstract: Adders are known to have the frequently used in VLSI designs. In digital design we have half adder and full adder, main adders by using these adders we can implement ripple carry adders. RCA use to perform any number of addition. In this RCA is serial adder and it has commutation delay problem. If increase the ha&fa simultaneously delay also increase. That’s why we go for parallel adders(parallel prefix adders). IN the parallel prefix adder are ks adder(kogge-stone),sks adder(sparse kogge-stone),spaning tree and brentkung adder. These adders are designd and implemented on FPGA sparton3E kit. Simulated and synthesis by model sim6.4b, Xilinx ise10.1.
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...IJMER
This document summarizes research on implementing various parallel prefix adders (Kogge-Stone, sparse Kogge-Stone, spanning tree, Brent-Kung) on FPGAs. It describes the structures of the different parallel prefix adders and discusses related work comparing adder performance on FPGAs. The adders were designed and tested on a Spartan 3E FPGA using VHDL simulation and Xilinx synthesis tools. Simulation waveforms and device utilization results are presented for the different adders. Measurement data from a logic analyzer was also used to compare actual performance to simulation results. In general, the research found that parallel prefix adders do not necessarily outperform ripple carry adders on FPGAs
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the
design of this basic adder unit. The speed of operation of a circuit is one of the important performance
criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many
research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The
improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the
previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for
comparative analysis. The coding is done in Verilog hardware description language (HDL) and the
simulation is carried out in Xilinx ISE 13.1 environment.
Design of high speed adders for efficient digital design blocksBharath Chary
This document discusses the design of high-speed adders for efficient digital design blocks. It compares parallel-prefix adders like Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. The Kogge-Stone Ling adder is found to perform most efficiently. Different tree adder structures are designed using CMOS logic and transmission gate logic and compared in terms of area, delay, and power consumption. Ling adders are analyzed, and it is shown that they reduce dependency on previous bit additions compared to other adders.
Implementation and Estimation of Delay, Power and Area for Parallel Prefix Ad...IJMTST Journal
This document compares the performance of four types of parallel prefix adders (Kogge-Stone, sparse Kogge-Stone, spanning tree, and Brent Kung) implemented on a Xilinx Spartan 3E FPGA. It finds that the parallel prefix adders have better performance than ripple carry and carry skip adders for widths above 56 bits. For the FPGA implementation, the Brent Kung adder requires the smallest area while the Kogge-Stone adder is largest. Simulation results show the Brent Kung adder has the fastest delay. Measurements using logic analysis equipment confirm the simulation results.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
This document summarizes the delay and area analysis of a regular 16-bit square root carry select adder (SQRT CSLA) architecture and a proposed modified architecture. The regular design contains five groups of ripple carry adders of different sizes. The delay and area of each group is evaluated based on the delays of basic blocks like full adders and multiplexers. The proposed design aims to reduce area and power by replacing one ripple carry adder in each group with a binary to excess-1 converter, which requires fewer logic gates. Implementation results show the proposed design has lower area and power with a slight increase in delay compared to the regular SQRT CSLA architecture.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This document discusses the performance evaluation of a low power carry save adder (CSA) for VLSI applications. It begins with an abstract that examines subthreshold leakage in CSA circuits and how reducing threshold voltage can lower power consumption. The document then reviews previous work on CSA design. It presents the architecture of a proposed 4-bit CSA designed using gate diffusion input cells to reduce area and power. Simulation results show the CSA has total average power of 4.93μW, propagation delay of 16.3ns, and 37% reduced area due to using GDI cells. The CSA operates as intended in subthreshold regions with low static leakage current.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount
of leakage current which confine increases the power consumption of the devices. Adders are the basic
building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
An Improved Optimization Techniques for Parallel Prefix Adder using FPGAIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
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International Journal of Computational Engineering Research(IJCER)
1. International Journal of Computational Engineering Research||Vol, 03||Issue, 8||
||Issn 2250-3005 || ||August||2013|| Page 58
Design and Testing Of Prefix Adder for High Speed Application
by Using Verilog HDL
1,
Rajitha Chandragiri, 2,
P. Venkata Lavanya
1,
Research Scholar, ECE Dept, TKR College of Engineering & Technology, Hyderabad, AP-
INDIA
2
Assoc Prof, ECE Dept, TKR College of Engineering & Technology, Hyderabad, AP-INDIA
I. INTRODUCTION
Addition is a timing critical operation in today's floating point units. In order to develop faster
processing, an end-around carry (EAC) was proposed as a part of fused-multiply-add unit which performs
multiplication followed by addition [5]. The proposed EAC adder was also investigated through other pre fix
adders in FPGA technology as a complete adder [6]. In this thesis, we propose a 128-bit standalone adder with
parallel prefix end around carry logic and conditional sum blocks to improve the critical path delay and provide
flexibility to design with different adder architectures. In previous works, CLA logic was used for EAC logic.
Using a modified structure of a parallel prefix 2n + 1 adder provides flexibility to the design and decreases the
length of the carry path. After the architecture is tested and verified, critical path is analyzed using
FreePDK45nm library. Full custom design techniques are applied carefully during critical path optimization.
Critical path analysis provides fast comparison of the total delay among different architectures without
designing the whole circuit and a simpler approach to size the transistors for lowest delay possible. As a final
step, datapath is designed as a recurring bitslice for fast layout entry. The results show that the proposed adder
shows 142ps delay, 2.42mW average power dissipation, and 3,132 sq. micron area assuming there is not much
routing area overhead in the estimated area.
Binary addition is the most fundamental and frequently used arithmetic operation. A lot of work on
adder design has been done so far and much architecture have been proposed. When high operation speed is
required, tree structures like parallel-prefix adders are used [1] - [10]. In [1], Sklansky proposed one of the
earliest tree-prefix is used to compute intermediate signals. In the Brent-Kung approach [2], designed the
computation graph for area-optimization. The KS architecture [3] is optimized for timing. The LF architecture
[4], is proposed, where the fan-out of gates increased with the depth of the prefix computation tree. The HC
adder architecture [5], is based on BK and KS is proposed. In [6], an algorithm for back-end design is proposed.
The area minimization is done by using bitwise timing constraints [7]. In [8], which is targeted to minimize the
total switching activities under bitwise timing constraints. The architecture [9], saves one logic level
implementation and reduces the fan-out requirements of the design. A fast characterization process for Knowles
adders is proposed using matrix representation [10].The Parallel Prefix addition is done in three steps.
which is shown in fig1. The fundamental generate and propagate signals are used to generate the carry
input for each adder. Two different operators black and gray are used here. The aim of this paper is to propose a
new approach for the basic operators and make use of these operators in various parallel prefix adders to
evaluate their performance with newly redesigned operators The rest of the paper is organized as follows: In
section II, some background information about Parallel Prefix architecture is given. New design approach of
ABSTRACT:
Parallel prefix adder is the most flexible and widely used for binary addition. Parallel
Prefix adders are best suited for VLSI implementation. Numbers of parallel prefix adder
structures have been proposed over the past years intended to optimize area, fan-out, and logic
depth and inter connect count. This paper presents a new approach to redesign the basic
operators used in parallel prefix architectures. The number of multiplexers contained in each
Slice of an FPGA is considered here for the redesign of the basic operators used in parallel
prefix tree. The experimental results indicate that the new approach of basic operators make
some of the parallel prefix adder’s architectures faster and area efficient.
Keywords: Ripple Carry Adder, Parallel Prefix, Kogge Stone, ASIC, Sparse Adders
2. Design And Testing Of Prefix…
||Issn 2250-3005 || ||August||2013|| Page 59
basic operators is discussed in section III. Experimental results are presented in section IV. Conclusions are
drawn in section V.
Several papers have attacked the problem of designing efficient diminished adders. The majority of
them rely on the use of an inverted end around carry (IEAC) n-bit adder, which is an adder that accepts two n-
bit operands and provides a sum increased by one compared to their integer sum if their integer addition does
not result in a carry output. Although an IEAC adder can be implemented by using an integer adder in which its
carry output is connected back to its carry input via an inverter, such a direct feedback is not a good solution.
Since the carry output depends on the carry input, a direct connection between them forms a combinational loop
that may lead to an unwanted race condition [21]. To this end, a number of custom solutions have been proposed
for the design of efficient IEAC adders. Considering the diminished-1 representation for modulo 2n þ 1
addition, [4], [5] used an IEAC adder which is based on an integer adder along with an extra carry lookahead
(CLA) unit. The CLA unit computes the carry output which is then inverted used as the carry input of the
integer adder. Solutions that rely on a single carry computation unit have also been proposed. Zimmermann
[22], [23] proposed IEAC adders that make use of a parallel-prefix carry computation unit along with an extra
prefix level that handles the inverted end-around carry.
Although these architectures are faster than the carry lookahead ones proposed in [24], for sufficiently
wide operands, they are slower than the corresponding parallel prefix integer adders because of the need for the
extra prefix level. In [24], it has been shown that the recirculation of the inverted end around carry can be
performed within the existing prefix levels, that is, in parallel with the carries’ computation. In this way, the
need of the extra prefix level is canceled and parallel-prefix IEAC adders are derived that can operate as fast as
their integer counterparts, that is, they offer a logic depth of log2 n prefix levels. Unfortunately, this level of
performance requires significantly more area than the solutions of [22], [23], since a double parallel-prefix
computation tree is required in several levels of the carry computation unit. For reducing the area complexity of
the parallel-prefix solutions, select-prefix [25] and circular carry select [26] IEAC adders have been proposed.
Unfortunately, both these proposals achieve a smaller operating speed than the parallel-prefix ones of [24].
Recently, very fast IEAC adders that use the Ling carry formulation of parallel-prefix addition [27] have
appeared in [28], that also suffer from the requirement of a double parallel-prefix computation tree. Although a
modulo 2n þ 1 adder that follows the ðn þ 1Þ-bit weighted representation can be designed following the
principles of generic modulo adder design [29], specialized architectures for it have appeared in [30], [31].
However, it has been recently shown [32] that a weighted adder can be designed efficiently by using an IEAC
one and a carry save adder (CSA) stage. As a result, improving the design for an IEAC adder would improve the
weighted adder design as well.
III.PARALLEL-PREFIX ADDITION BASICS
The binary adder is the critical element in most digital circuit designs including digital signal
processors (DSP) and microprocessor datapath units. As such, extensive research continues to be focused on
improving the power delay performance of the adder. In VLSI implementations, parallel-prefix adders are
known to have the best performance. Reconfigurable logic such as Field Programmable Gate Arrays (FPGAs)
has been gaining in popularity in recent years because it offers improved performance in terms of speed and
power over DSP-based and microprocessor-based solutions for many practical designs involving mobile DSP
and telecommunications applications and a significant reduction in development time and cost over Application
Specific Integrated Circuit (ASIC) designs. The power advantage is especially important with the growing
popularity of mobile and portable electronics,which make extensive use of DSP functions. However, because of
the structure of the configurable logic and routing resources in FPGAs, parallel-prefix adders will have a
different performance than VLSI implementations.
In particular, most modern FPGAs employ a fast-carry chain which optimizes the carry path for the
simple Ripple Carry Adder (RCA).In this paper, the practical issues involved in designing and implementing
tree-based adders on FPGAs are. An efficient testing strategy for evaluating the performance of these adders is
discussed. Several tree-based adder structures are implemented and characterized on a FPGA and compared
with the Ripple Carry Adder (RCA) and the Carry Skip Adder (CSA). Finally, some conclusions and
suggestions for improving FPGA designs to enable better tree-based adder performance are given.
IV. CARRY-TREE ADDER DESIGNS
Parallel-prefix adders, also known as carry-tree adders, pre-compute the propagate and generate signals
[1]. These signals are variously combined using the fundamental carry operator (fco) [2].
(gL, pL) ο (gR, pR) = (gL + pL•gR, pL • pR) (1)
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Due to associative property of the fco, these operators can be combined in different ways to form various adder
structures. For, example the four-bit carry-lookahead generator is given by:
c4 = (g4, p4) ο [ (g3, p3) ο [(g2, p2) ο (g1, p1)] ] (2)
A simple rearrangement of the order of operations allows parallel operation, resulting in a more efficient tree
structure for this four bit example:
c4 = [(g4, p4) ο (g3, p3)] ο [(g2, p2 ) ο (g1, p1)] (3)
It is readily apparent that a key advantage of the tree structured adder is that the critical path due to the
carry delay is on the order of log2N for an N-bit wide adder. The arrangement of the prefix network gives rise to
various families of adders. For a discussion of the various carry-treestructures, see [1, 3]. For this study, the
focus is on the Kogge-Stone adder [4], known for having minimal logic depth and fanout (see Fig 1(a)). Here we
designate BC as the black cell which generates the ordered pair in equation (1); the gray cell (GC) generates the
left signal only, following [1]. The interconnect area is known to be high, but for an FPGA with large routing
overhead to begin with, this is not as important as in a VLSI implementation. The regularity of the Kogge-Stone
prefix network has built in redundancy which has implications for fault-tolerant designs [5]. The sparse Kogge-
Stone adder, shown in Fig 1(b), is also studied. This hybrid design completes the summation process with a 4 bit
RCA allowing the carry prefix network to be simplified. Another carry-tree adder known as the spanning tree
carry-lookahead (CLA) adder is also examined [6]. Like the sparse Kogge-Stone adder, this design terminates
with a 4- bit RCA. As the FPGA uses a fast carry-chain for the RCA, it is interesting to compare the
performance of this adder with the sparse Kogge-Stone and regular Kogge-Stone adders. Also of interest for the
spanning-tree CLA is its testability features [7].
V. RELATED WORK
Xing and Yu noted that delay models and cost analysis for adder designs developed for VLSI
technology do not map directly to FPGA designs [8]. They compared the design of the ripple carry adder with
the carry-lookahead, carry-skip, and carry-select adders on the Xilinx 4000 series FPGAs. Only an optimized
form of the carry-skip adder performed better than the ripple carry adder when the adder operands were above
56 bits. A study of adders implemented on the Xilinx Virtex II yielded similar results [9]. In [10], the authors
considered several parallel prefix adders implemented on a Xilinx Virtex 5 FPGA. It is found that the simple
RCA adder is superior to the parallel prefix designs because the RCA can take advantage of the fast carry chain
on the FPGA.Kogge-Stone The Kogge-Stone tree [22] Figure 1.5 achieves both log2N stages and fan-out of 2 at
each stage. This comes at the cost of long wires that must be routed between stages. The tree also contains more
PG cells; while this may not impact the area if the adder layout is on a regular grid, it will increase power
consumption. Despite these cost, Kogge-Stone adder is generally used for wide adders because it shows the
lowest delay among other structures.
Another carry-tree adder known as the spanning tree carry-lookahead (CLA) adder is also examined
[6]. Like the sparse Kogge-Stone adder, this design terminates with a 4-bit RCA. As the FPGA uses a fast carry-
chain for the RCA, it is interesting to compare the performance of this adder with the sparse Kogge-Stone and
regular Kogge-Stone adders. Also of interest for the spanning-tree CLA is its testability features [7].
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This study focuses on carry-tree adders implemented on a Xilinx Spartan 3E FPGA. The distinctive
contributions of this paper are two-fold. First, we consider tree-based adders and a hybrid form which combines
a tree structure with a ripple-carry design. The Kogge-Stone adder is chosen as a representative of the former
type and the sparse Kogge Stone and spanning tree adder are representative of the latter category. Second, this
paper considers the practical issues involved in testing the adders and provides actual measurement data to
compare with simulation results
VI. RESULTS
Fig.6.1 synthesis of 128 bit ripple carry adder
Fig.6.2 synthesis of 128 bit kogge stone adder
Fig.6.2 synthesis of 128 bit sparse-kogge adder
VII. CONCLUSIONS
This paper presents a new approach for the basic operators of parallel prefix tree adders. In KS, Sparse
Kogge delay is reduced by this new approach, The same can be understood with reference to number of logic
levels of implementation, as the logic levels are more delay increases. The area requirement can be considered
from the utilization of LUTs, Slices and over all gate count. KS and Knowles adders occupies more area in new
approach.
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The KS adders are proven even faster than Skalansky adder but they occupy large area compared to
Skalansky adder. Finally it can be concluded that the new approach for the redesign of basic operators will
speed up the addition process of parallel prefix addition with some area overhead. The performance of these
adders can be estimated for high bit-widths. This can be further used in Cryptographic applications, where the
addition of more number of bits is necessary. The new approach for the parallel prefix adders can also be used to
speed up the addition process in FIR filter and arithmetic operations like multipliers, etc.
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