This document presents a novel design for a 4:1 multiplexer circuit using reversible logic gates. The design uses a combination of the basic TKS reversible gate and a newly proposed reversible gate called VSMT. The optimized design uses only one VSMT gate, producing 5 garbage outputs, compared to the previous design using three TKS gates producing 6 garbage outputs. The new design achieves optimization by reducing the number of gates and garbage outputs. Reversible logic circuit design is gaining attention for applications in low power computing such as nanotechnology and quantum computing.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
The document describes a proposed design for implementing Booth's multiplier in reversible logic to reduce power consumption. It presents reversible logic gates that can perform the functions of a multiplier cell (B cell) and control cell (C cell). These cells are combined into an n×n reversible Booth's multiplier array. The design is proven to be efficient from a reversible logic perspective by establishing theoretical lower bounds on the number of gates, garbage outputs, circuit delay, and quantum cost compared to existing reversible multiplier designs. An example 4×4 multiplication is also shown to demonstrate the proposed design.
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Design of Multiplexers, Decoder and a Full Subtractor using Reversible GatesIJLT EMAS
This paper shows an effective design of combinational circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage outputs in implementing each combinational circuit.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
Design and Implementation of High Speed Area Efficient Double Precision Float...IOSR Journals
The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
The document discusses combinational logic circuits. It covers sum-of-products and product-of-sums forms for representing logic functions. Methods for analyzing and simplifying logic circuits are presented, including Boolean algebra, Karnaugh maps, and deriving truth tables from logic diagrams. Examples of common logic circuits like adders, decoders, and converters are provided along with steps for designing combinational logic circuits.
The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
The document describes a proposed design for implementing Booth's multiplier in reversible logic to reduce power consumption. It presents reversible logic gates that can perform the functions of a multiplier cell (B cell) and control cell (C cell). These cells are combined into an n×n reversible Booth's multiplier array. The design is proven to be efficient from a reversible logic perspective by establishing theoretical lower bounds on the number of gates, garbage outputs, circuit delay, and quantum cost compared to existing reversible multiplier designs. An example 4×4 multiplication is also shown to demonstrate the proposed design.
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Design of Multiplexers, Decoder and a Full Subtractor using Reversible GatesIJLT EMAS
This paper shows an effective design of combinational circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage outputs in implementing each combinational circuit.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
Design and Implementation of High Speed Area Efficient Double Precision Float...IOSR Journals
The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
The document discusses combinational logic circuits. It covers sum-of-products and product-of-sums forms for representing logic functions. Methods for analyzing and simplifying logic circuits are presented, including Boolean algebra, Karnaugh maps, and deriving truth tables from logic diagrams. Examples of common logic circuits like adders, decoders, and converters are provided along with steps for designing combinational logic circuits.
The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
An Efficient Design for Data Encryption and Decryption using Reconfigurable R...IRJET Journal
This document presents a design for data encryption and decryption using reconfigurable reversible logic gates. The design uses a cascade of 16 4-input reversible gates to encrypt or decrypt a 9-bit data block. Each gate in the cascade is determined by a main encryption key. The same key is used for both encryption and decryption, with the order of gates reversed for decryption. A reconfigurable reversible logic gate is proposed that can implement any of the 32 possible 4-input reversible gates through configuration. Verilog HDL simulation results are presented to validate the encryption/decryption scheme works as intended on Xilinx FPGAs.
Combinational logic circuits by Tahir YasinTAHIR YASIN
This research paper defines the digital electronics and its one type combinational circuits.
Combinational circuits is based on the Boolean expression so also gives the brief introduction about Boolean algebra and also describes the different forms of circuits and also describes the minimization techniques of combinational logic circuits and some general application of combinational circuit
Follow me on twitter @Tahiryasin971
Email: tahiryasin758@gmail.com
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
The document discusses digital circuits including combinational and sequential circuits. It describes various combinational logic circuits such as half adders, full adders, comparators, multiplexers, encoders, decoders. It also discusses sequential circuits and how they employ memory elements. Arithmetic circuits, binary adders, subtractors, and BCD to 7-segment decoders are explained in detail through diagrams and examples.
This document summarizes research on improving the performance of multiplier and accumulator (MAC) circuits used in digital signal processing. It presents four architectures for carry-select adders (CSLA) that can be used in MACs: 1) a regular CSLA, 2) a CSLA that replaces full adders with binary-to-excess converters (BEC) to reduce area, 3) a CSLA that uses D-latches to store intermediate values and reduce the number of adders, and 4) a modified CSLA architecture. The document analyzes the delay and area of each group of bits for the different CSLA architectures. It finds that BEC and D-latch based C
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Delay Optimization of Low Power Reversible Gate using MOS Transistor Level de...IJERA Editor
In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base
application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the
power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI
circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using
the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce
energy loss due to the information bits lost during the operation information loss occurs because the total number
of output signals generated is less than total number of input signals applied. In reversible if the input vector can
be uniquely recovered from the output vector and if there is a one to one correspondence between its input and
output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS
transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future
in design of low power consumption circuits and high speed application.
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECESeshaVidhyaS
The document discusses the design of various combinational logic circuits including multiplexers. It begins by defining combinational circuits as those whose outputs depend only on the current inputs and not prior inputs. Half adders, full adders, half subtractors, and full subtractors are designed using truth tables and Karnaugh maps. Larger multiplexers can be implemented using smaller multiplexers, such as an 8x1 multiplexer using two 4x1 multiplexers. Boolean functions can also be implemented using multiplexers by treating the minterms as inputs.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
This document contains notes on combinational logic circuits including multiplexers, demultiplexers, encoders, and decoders. It provides circuit diagrams, truth tables, and explanations of the working principles for various digital components such as 2:1 and 4:1 multiplexers, 1:2 and 1:4 demultiplexers, priority encoders, decimal to BCD encoders, 3:8 decoders, and 2-bit comparators. Advantages of using multiplexers are also discussed, such as reducing the number of wires and circuit complexity.
The document provides an overview of digital circuits and microcomputers. It defines key digital logic terms and concepts like binary numbers, logic gates, Boolean algebra, and Karnaugh maps. It also describes the functional blocks of a microcomputer like CPU, memory, and I/O. Memory types like RAM, ROM, and mass storage are discussed. Assembly language programming and compilers are briefly covered.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
This is a classroom presentation for the basic concepts of HDL, using Verilog as the programming language. Module 3 deals with programmable logic devices.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
This document describes implementing combinational logic circuits using multiplexers and decoders. It provides examples of using multiplexers and decoders to realize Boolean functions from truth tables. Specifically, it shows how multiplexers can be used to implement functions with 1, 2, 4, 8, or 16 inputs and how decoders can implement multiple Boolean functions at once by connecting minterm outputs to OR gates. It also describes using 7-segment displays with multiplexers and decoders to display hexadecimal values from a 4-bit input.
The document provides information about the course objectives and outcomes of the Digital Electronics subject taught at Matrusri Engineering College. The course aims to introduce principles of digital hardware, Boolean algebra, logic gates and various number systems. Students will learn to design combinational circuits, implement circuits using programmable logic devices and Verilog HDL. They will also learn about sequential circuits, flip-flops, registers, counters and finite state machines. The syllabus is divided into five units covering topics such as logic gates, number representation, combinational circuit design, sequential circuits and finite state machines.
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
This document discusses Verilog HDL structural modeling at the gate level. It provides examples of how to model basic logic gates like AND, OR, XOR, and NOT gates using Verilog primitives. It also shows an example of modeling a half adder and full adder circuit using logic gates in Verilog. The full adder example connects the ports by ordered list and by name to instantiate the module.
This document discusses different levels of abstraction in Verilog HDL modeling including switch level, gate level, register transfer level (RTL), and behavioral level. It describes modeling techniques like switch-level modeling, gate-level modeling, dataflow modeling, and behavioral modeling. The document also covers key concepts in Verilog like modules, module components, module ports, port assignments, hierarchical design, and module instances. Modules are the basic building blocks in Verilog and allow designers to mix abstraction levels and hierarchically interconnect components.
Drupal is an open source content management system written in PHP. It is free to install and use, with strong built-in functionality and thousands of add-on features. Drupal can be used to build a wide variety of websites, including blogs, forums, e-commerce sites, and more. Many well-known sites such as whitehouse.gov and data.gov.uk use Drupal. PixelCrayons offers Drupal integration, development, theming, maintenance and customization services.
An Efficient Design for Data Encryption and Decryption using Reconfigurable R...IRJET Journal
This document presents a design for data encryption and decryption using reconfigurable reversible logic gates. The design uses a cascade of 16 4-input reversible gates to encrypt or decrypt a 9-bit data block. Each gate in the cascade is determined by a main encryption key. The same key is used for both encryption and decryption, with the order of gates reversed for decryption. A reconfigurable reversible logic gate is proposed that can implement any of the 32 possible 4-input reversible gates through configuration. Verilog HDL simulation results are presented to validate the encryption/decryption scheme works as intended on Xilinx FPGAs.
Combinational logic circuits by Tahir YasinTAHIR YASIN
This research paper defines the digital electronics and its one type combinational circuits.
Combinational circuits is based on the Boolean expression so also gives the brief introduction about Boolean algebra and also describes the different forms of circuits and also describes the minimization techniques of combinational logic circuits and some general application of combinational circuit
Follow me on twitter @Tahiryasin971
Email: tahiryasin758@gmail.com
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
The document discusses digital circuits including combinational and sequential circuits. It describes various combinational logic circuits such as half adders, full adders, comparators, multiplexers, encoders, decoders. It also discusses sequential circuits and how they employ memory elements. Arithmetic circuits, binary adders, subtractors, and BCD to 7-segment decoders are explained in detail through diagrams and examples.
This document summarizes research on improving the performance of multiplier and accumulator (MAC) circuits used in digital signal processing. It presents four architectures for carry-select adders (CSLA) that can be used in MACs: 1) a regular CSLA, 2) a CSLA that replaces full adders with binary-to-excess converters (BEC) to reduce area, 3) a CSLA that uses D-latches to store intermediate values and reduce the number of adders, and 4) a modified CSLA architecture. The document analyzes the delay and area of each group of bits for the different CSLA architectures. It finds that BEC and D-latch based C
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Delay Optimization of Low Power Reversible Gate using MOS Transistor Level de...IJERA Editor
In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base
application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the
power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI
circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using
the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce
energy loss due to the information bits lost during the operation information loss occurs because the total number
of output signals generated is less than total number of input signals applied. In reversible if the input vector can
be uniquely recovered from the output vector and if there is a one to one correspondence between its input and
output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS
transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future
in design of low power consumption circuits and high speed application.
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECESeshaVidhyaS
The document discusses the design of various combinational logic circuits including multiplexers. It begins by defining combinational circuits as those whose outputs depend only on the current inputs and not prior inputs. Half adders, full adders, half subtractors, and full subtractors are designed using truth tables and Karnaugh maps. Larger multiplexers can be implemented using smaller multiplexers, such as an 8x1 multiplexer using two 4x1 multiplexers. Boolean functions can also be implemented using multiplexers by treating the minterms as inputs.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
This document contains notes on combinational logic circuits including multiplexers, demultiplexers, encoders, and decoders. It provides circuit diagrams, truth tables, and explanations of the working principles for various digital components such as 2:1 and 4:1 multiplexers, 1:2 and 1:4 demultiplexers, priority encoders, decimal to BCD encoders, 3:8 decoders, and 2-bit comparators. Advantages of using multiplexers are also discussed, such as reducing the number of wires and circuit complexity.
The document provides an overview of digital circuits and microcomputers. It defines key digital logic terms and concepts like binary numbers, logic gates, Boolean algebra, and Karnaugh maps. It also describes the functional blocks of a microcomputer like CPU, memory, and I/O. Memory types like RAM, ROM, and mass storage are discussed. Assembly language programming and compilers are briefly covered.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
This is a classroom presentation for the basic concepts of HDL, using Verilog as the programming language. Module 3 deals with programmable logic devices.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
This document describes implementing combinational logic circuits using multiplexers and decoders. It provides examples of using multiplexers and decoders to realize Boolean functions from truth tables. Specifically, it shows how multiplexers can be used to implement functions with 1, 2, 4, 8, or 16 inputs and how decoders can implement multiple Boolean functions at once by connecting minterm outputs to OR gates. It also describes using 7-segment displays with multiplexers and decoders to display hexadecimal values from a 4-bit input.
The document provides information about the course objectives and outcomes of the Digital Electronics subject taught at Matrusri Engineering College. The course aims to introduce principles of digital hardware, Boolean algebra, logic gates and various number systems. Students will learn to design combinational circuits, implement circuits using programmable logic devices and Verilog HDL. They will also learn about sequential circuits, flip-flops, registers, counters and finite state machines. The syllabus is divided into five units covering topics such as logic gates, number representation, combinational circuit design, sequential circuits and finite state machines.
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
This document discusses Verilog HDL structural modeling at the gate level. It provides examples of how to model basic logic gates like AND, OR, XOR, and NOT gates using Verilog primitives. It also shows an example of modeling a half adder and full adder circuit using logic gates in Verilog. The full adder example connects the ports by ordered list and by name to instantiate the module.
This document discusses different levels of abstraction in Verilog HDL modeling including switch level, gate level, register transfer level (RTL), and behavioral level. It describes modeling techniques like switch-level modeling, gate-level modeling, dataflow modeling, and behavioral modeling. The document also covers key concepts in Verilog like modules, module components, module ports, port assignments, hierarchical design, and module instances. Modules are the basic building blocks in Verilog and allow designers to mix abstraction levels and hierarchically interconnect components.
Drupal is an open source content management system written in PHP. It is free to install and use, with strong built-in functionality and thousands of add-on features. Drupal can be used to build a wide variety of websites, including blogs, forums, e-commerce sites, and more. Many well-known sites such as whitehouse.gov and data.gov.uk use Drupal. PixelCrayons offers Drupal integration, development, theming, maintenance and customization services.
El resumen del documento es:
1) Un científico necesita formar un grupo de 20 criaturas de 5 razas diferentes de un planeta para ayudarlo en sus investigaciones.
2) Cada raza tiene diferentes habilidades y requerimientos de alimentos y climas.
3) Se debe formular un modelo de programación entera para seleccionar las razas que minimicen los costos de alimentos y preservantes durante un viaje de 10 meses, cumpliendo con los requisitos de habilidades, climas, alimentos y restricciones de las razas.
This document summarizes a study of CEO succession events among the largest 100 U.S. corporations between 2005-2015. The study analyzed executives who were passed over for the CEO role ("succession losers") and their subsequent careers. It found that 74% of passed over executives left their companies, with 30% eventually becoming CEOs elsewhere. However, companies led by succession losers saw average stock price declines of 13% over 3 years, compared to gains for companies whose CEO selections remained unchanged. The findings suggest that boards generally identify the most qualified CEO candidates, though differences between internal and external hires complicate comparisons.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This document summarizes a research paper that presents a codec scheme to optimize power in VLSI interconnects using bus encoding. The scheme detects different types of crosstalk couplings between wires and encodes the data to reduce switching activity. It was implemented using Cadence tools in 0.18um technology. Simulation results found a maximum power of 6.44uW for an input combination, showing a 38.89% power reduction over previous work. The scheme models the full custom design approach instead of semi-custom.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
IRJET- Design and Implementation of Combinational Circuits using Reversible G...IRJET Journal
This document discusses the design and implementation of combinational circuits using reversible gates to reduce power consumption. It begins with an introduction to reversible logic and discusses how reversible gates can be used to design logic circuits without information loss and zero energy dissipation. Several reversible gates are described including NOT, Feynman, Toffoli and Fredkin gates. The document then presents the design of a 2x4 decoder and 4x16 decoder using reversible gates like Peres, TR and CNOT gates. Simulation results demonstrating the outputs of the decoders are shown. Finally, a comparative study of reversible decoders in terms of quantum cost and garbage outputs is discussed. The conclusion states that reversible logic allows minimizing fan-out limitations and quantum cost in combinational
IRJET- Design and Implementation of Combinational Circuits using Reversib...IRJET Journal
This document discusses the design and implementation of combinational circuits using reversible gates to reduce power consumption. It describes various reversible gates like NOT, Feynman, Toffoli, and Fredkin gates. Reversible decoders are designed using these gates to implement 2x4, 3x8, and 4x16 decoders with lower quantum costs and garbage outputs compared to traditional designs. The reversible decoder approach allows designing combinational circuits like adders and comparators with better performance. Simulation results demonstrate the working of the designed reversible decoders.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
QUANTUM COMPUTING FOR VLSI : VERILOG IMPLEMENTATION OF REVERSIBLE LOGIC GATESDrKavitaKhare
This document discusses reversible logic gates and presents Verilog code implementations. It begins with an introduction to reversible logic and its applications in low power design. Reversible logic gates allow computations to occur with zero energy dissipation by ensuring a one-to-one mapping between inputs and outputs. The document then defines basic reversible logic concepts like reversible functions, gates, ancilla inputs, garbage outputs, and quantum cost. It proceeds to describe several important reversible logic gates - NOT, Feynman, Double Feynman, Toffoli - and provides their Verilog implementations and combinational circuit diagrams. The document focuses on presenting the theoretical foundations and hardware implementations of reversible logic gates using Verilog.
IN THIS SLIDE WE HAVE COVERED THE TOPIC OF DIGITAL ELECTRONIS MULTIPLEXER AND DE MULTIPLEXER TOPIC OF COMBINATIONAL CIRCUIT
THANKS FOR READING MY ANIMATION
Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
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Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
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AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
This document presents a novel 7-input minority gate design using carbon nanotube field-effect transistors (CNTFETs) as an alternative to complementary metal-oxide-semiconductor (CMOS) technology. The proposed gate uses only 9 CNTFETs to implement the 7-input minority function, providing over a 98% reduction in the number of transistors needed compared to conventional CMOS implementations. Simulation results show the CNTFET minority gate design has better delay, energy efficiency, and driving power compared to a conventional 4-input NAND gate. The document introduces CNTFET technology, describes the proposed 7-input minority gate structure, presents simulation results comparing it to CMOS designs, and concludes it is a promising alternative
High Speed Memory Efficient Multiplier-less 1-D 9/7 Wavelet Filters Based NED...IJERA Editor
This document proposes a new efficient distributed arithmetic (NEDA) technique for implementing high-speed memory-efficient 1-D 9/7 wavelet filters. NEDA is an area-efficient architecture that does not require ROM, multiplication, or subtraction. It can expose redundancy in adder arrays consisting of entries of 0 and 1. The document describes how NEDA can be used to compute the high pass filter output of a 1-D discrete wavelet transform using 9/7 filters through an example. It also shows the proposed NEDA architecture and processing steps to obtain the low pass and high pass filter outputs with just additions and shifts.
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology ...VLSICS Design
This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic Design Automation tools.
M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.Suchitra goudar
The document proposes designs for ternary logic gates based on single power supply voltage for CMOS technology. It describes the design of a simple ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI) using only enhancement-type MOSFETs. Transistor widths and lengths are optimized to achieve the desired voltage transfer characteristics. Basic ternary logic gates including a ternary NAND (TNAND) and ternary NOR (TNOR) are also designed using a similar single-transistor approach. The proposed gate designs aim to reduce transistor count and power consumption compared to prior ternary logic designs.
In this paper, we propose a new technique for implementing a low power high speed multiplier based on Sleepy Stack Technique and consisting of
minimum number of transistors. Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). An 4 bit x 4 bit
multiplier has also been implemented using the design of only using basic combinational circuits and its performance has been analyzed and
compared with similar multipliers designed with peer combinational design available in literature. The explored method of implementation achieves
a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional
CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
This document summarizes research on basic reversible logic gates and their implementation in Quantum-dot Cellular Automata (QCA). It begins with an introduction to reversible logic and its advantages in reducing power dissipation compared to traditional irreversible logic. It then defines key concepts in reversible logic like garbage outputs and quantum cost. The document describes several important reversible logic gates - the Feynman gate, Fredkin gate, DKG gate, and MRG gate - and provides their truth tables and quantum implementations in QCA. It presents simulation results for these gates in QCA and compares their complexity, area, delay, and simulation time. The document concludes that reversible logic gates can help in designing circuits for quantum computing and other low power applications
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International Journal of Computational Engineering Research(IJCER)
1. International Journal of Computational Engineering Research||Vol, 03||Issue, 10||
Novel Design of A 4:1 Multiplexer Circuit Using Reversible Logic
Vandana Shukla1, O. P. Singh1, G. R. Mishra1, R. K. Tiwari2
1
Amity School Of Engineering & Technology, Amity University, Lucknow
2
Dr. R. M. L. University, Faizabad
ABSTRACT:
Area of reversible logic is attracting much attention of researchers nowadays. Reversible logic
concept of digital circuit designing is gaining wide scope in the area of nanotechnology, quantum
computing, signal processing, optical computing etc due to its ability to design low power loss digital
circuits. This paper presents an optimized multiplexer circuit based on reversible logic using various
available basic reversible gates. Optimization of the multiplexer circuit is achieved on the basis of total
number of gates used in the circuit and total number of outputs generated. These circuits are useful for
further circuit designing with low power loss.
KEYWORDS: Reversible circuit design, Basic reversible gates, Multiplexer circuit.
I.
INTRODUCTION
An integrated circuit containing many identical cells which can be electrically programmed to become
almost any kind of digital circuit or system is called as Field Programmable Gate Arrays (FPGAs) [1].
Multiplexers play the key role in the functionalities of FPGAs, so to design a multiplexer with reversible logic
will generate the concept of designing low power loss circuits for FPGAs.Earlier digital circuits were made up
of conventional logic gates. These gates were irreversible in nature. Reversible circuit designing is the way of
today’s digital circuit designing. In 1961, R. Landauer has shown that these conventional irreversible circuits
dissipate some energy due to the information loss during the operation of the circuit [2]. After that in 1973,
Benette has shown that this energy loss can be minimized or even removed if the circuits are designed using
reversible gates [3].
II.
REVERSIBLE LOGIC CIRCUIT DESIGN
[2.1] Reversible Logic- conventional logic gates were generally (n:1) in nature. Where n represents the number
of input signals applied and 1 indicated the single output generated from the gate. Whereas reversible logic gates
are (n,n) logic gates. Here both, the number of input signals and the number of output signal are equal to n. In
conventional logic gates output signals are less in number as compared to the number of input signals. But in
reversible gates input and output signals are equal in number. The combination of output signal at any instance
can provide the exact status of input combination. This is the main reason to name these (n,n) gates, reversible
logic gates[4,5,6].
[2.2] Basic Reversible Gates- There are various basic reversible (n,n) gates[7,8,9,10,11,12,13]. For designing
multiplexer TKS gate[14] is the optimum choice. TKS gate is a (3,3) reversible gate. Its block diagram is shown
in figure 1 and output equations are given below the diagram.
Figure 1: TKS Gate
Where ||Issn 2250-3005 ||
||October||2013||
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2. Novel Design Of A 4:1 Multiplexer…
In any reversible gate if we know the status of output signals (P, Q, R in case of TKS Gate) we can deduct the
instance combination of input stage (A, B, C in case of TKS Gate).
[2.3] Proposed Reversible Gate (VSMT Gate)- VSMT is a new proposed (6,6) reversible gate. This gate
conforms to the necessary characteristics of the reversible logic gates. These characteristics are as follows(a) Number of inputs = Number of outputs.
(b) One to one mapping between input and output.
(c) Zero feedback.
(d) Individual output bits are high for a total of half the number of total input combinations.
The block diagram of VSMT gate is shown in figure 2. Here input signals are A, B, C, D, E and F, whereas
output signals are P, Q, R, S, T and U.
Figure 2: Block diagram of VSMT gate
Output equations of above gate is given as below-
The truth table of this gate has a total of 64 input combinations. Here in this gate each input combination
produce unique output combination. This VSMT gate is a reversible gate for 6 input signals. This paper shows
the application of VSMT gate to design multiplexer circuit. Apart from proposed multiplexer circuit there can be
various other applications of DSM gates to design other digital circuits in optimized manner.
[2.4] Multiplexer Circuit- A multiplexer (MUX) is a device which selects any one of the several input signals
applied and provide it to the single output line according to the combination of selection lines applied.
Multiplexers are generally used for the conversion of parallel data lines into serial one. These are also called as
Data Selectors, as multiplexer selects one of the given input for the output according to the condition [15].
Figure 3 gives the block diagram of a 2 n:1 multiplexer. Here 2n refers to the total number of input signal lines
and 1 refers to the single output signal line. Total number of selection lines required is n as shown in the figure.
||Issn 2250-3005 ||
||October||2013||
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3. Novel Design Of A 4:1 Multiplexer…
Figure 3: Block Diagram of a 2n:1 Multiplexer
Where output equation isIf we name input signals of the multiplexer as I0, I1, I2, ..... I2n-1, selection lines as S0,S1, .... Sn-1 and output as Y
then truth table of a 2n:1 multiplexer can be shown as in Table 1.
Table 1: Truth Table of a 2n:1 multiplexer
Input Section Lines
Output
S. No.
Sn-1 .......... S1 S0
Y
1
0 .......... 0 0
I0
2
0 .......... 0 1
I1
----------------------------2n
1 .......... 1 1
I2n-1
As shown in the table 1 input selection lines combination decide the signal to be forwarded at the output lines
[16]. Multiplexers of different sizes can be designed by varying the number of selection lines i.e. n. Examples of
a simple multiplexer of size 4:1 is shown below4:1 MUX- a 4:1 multiplexer contains 2 selection lines and 4 input lines. Figure 5 shows the block diagram and
output equation of a 4:1 multiplexer.
Figure 4: Block Diagram of a 4:1 Multiplexer
Output equation can be written as-
III.
MULTIPLEXER DESIGN USING REVERSIBLE LOGIC GATES
Multiplexers are data selector circuits. To design a multiplexer circuit using reversible logic gates there
are few conditions of reversible circuit designing to be followed(a) There should be no feedback.
(b) There should be no fan-out.
(c) Garbage outputs should be minimum.
(d) Total number of gates should be minimum.
According to above conditions any digital circuit to be designed by reversible logic requires the optimum
selection of basic reversible gate for minimizing the said variants[17, 18, 19].
Earlier researchers have proposed to use TKS gates to design the multiplexer circuit. TKS gate is a (3,3)
reversible gate as explained in the subsection 2.2. Here we propose the designing of multiplexer circuit using the
combination of TKS and VSMT gates to achieve better circuits. Following subsection explain the designing of
4:1 multiplexers in detailDesign of 4:1 MUX using reversible gates- As explained in the earlier subsection, a 4:1 MUX has 2 selection
lines and 4 input lines. The design of this multiplexer in reversible logic requires 3 TKS gates. Input signals are
A, B, C, D and selection lines used are S1 and S0. The output variable is denoted by Y. The design approach 1 of
the same using TKS gates only is shown in the figure 5 below.
||Issn 2250-3005 ||
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4. Novel Design Of A 4:1 Multiplexer…
Figure 5: Approach 1 to design a 4:1 MUX using reversible gates
Where various output equations are given below-
Where E1 and E2 are intermediate results of the circuit. Above design produces 6 garbage outputs using a total of
3 reversible gates. Now we will design the same 4:1 MUX circuit using the proposed 6X6 reversible gate i.e.
VSMT gate. This circuit design approach 2 is shown in the figure 6 below.
Figure 6: Approach 2 to design a 4:1 MUX using VSMT gate
Here various output equations are as shown below-
In the approach 2 only one VSMT gate is used to design the 4:1 multiplexer. Input combinations applied to
VSMT gate are by connecting A, B, C, D, S1, S0 i.e. input and selection line signals to the (A, B, C, D, E and F)
input lines of the reversible gate. Output Y is taken from the P output line of the gate. Other outputs of the
VSMT gate produce the garbage outputs (G1, G2, G3, G4, G5). Here a total of 5 garbage output signals are
produced by using single reversible gate. Comparison of these design approaches for 4:1 multiplexer is shown in
the table 4 below.
Table 2: Comparison of various approaches to design a 4:1 MUX using reversible gates
S. No.
1
2
3
Variable
Total Number of Reversible Gates used
Total Number of Garbage Outputs
1-Bit XORs
||Issn 2250-3005 ||
||October||2013||
Approach 1
3
6
3
Approach 2
1
5
1
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5. Novel Design Of A 4:1 Multiplexer…
Figure 7: Comparison Chart for mux designs
Figure 8: Simulated waveform
IV.
RESULT AND ANALYSIS
As shown above in the table 2, the value of various variants to be considered in the process of
reversible circuit designing reduces when the circuit for 4:1 multiplexer using reversible gate is designed with
the help of the proposed VSMT gate. Here only one reversible gate is required to design the circuit of 4:1
multiplexer and the total number of garbage outputs produced are reduced to 5 as compared to 6 in the earlier
designs proposed.
V.
CONCLUSION AND FUTURE SCOPE
Reversible logic is becoming the modern way of digital logic circuit designing. Here in this paper we
have designed reversible circuits for 4:1 multiplexer. The optimized circuits are achieved with help of a
proposed reversible gate i.e. VSMT Gate, which is a (6,6) reversible gate. These designs can be further
expanded to achieve the reversible circuits for various other functions and devices. As multiplexers are the basic
building blocks of FPGA boards. These proposed multiplexers with reversible gates will help the researchers to
employ these FPGAs with reversible gates in low power logical design applications.
VI.
ACKNOWLEDGMENT
The authors are thankful to Mr. Aseem Chauhan (Additional President RBEF, Chancellor AUR), Maj.
General K. K. Ohri, AVSM (Retd.) Pro Vice Chancellor, AUUP, Lucknow Campus, Prof. S. T. H. Abidi
(Director, ASET) and Brig. Umesh K. Chopra (Director, AIIT, & Dy. Director, ASET) for their cooperation,
motivation and suggestive guidance.
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