This document describes the design of a reversible ripple carry adder using reversible logic gates. It discusses reversible logic gates like the Feynman, Fredkin, Toffoli and Peres gates. It then explains how to implement a reversible full adder using the Peres gate and HNG gate. A ripple carry adder is formed by cascading multiple full adders. 16-bit reversible ripple carry adders were designed using the Peres gate and HNG gate. The adder using HNG gate has fewer gates, less quantum cost but similar garbage outputs compared to the adder using Peres gate.