Unit 2 module-2

MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
SUBJECT NAME: DIGITAL ELECTRONICS
FACULTY NAME: Mrs.B J Praveena
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COURSE OBJECTIVES:
1. To introduce the principles of digital hardware, Boolean Algebra & Logic gates.
2. To learn various number system and combinational circuit building blocks.
3. To design combinational circuits for real world problems.
4. To introduce various flip-flops, registers & counters.
5. To introduce Finite State Machine and its design.
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COURSE OUTCOMES:
On successful completion of this course, the students will be able to:
1. Understand the design process of digital hardware and minimizing the logic
expressions using Boolean algebra.
2. Understand various number systems and design various combinational circuits.
3. To implement the combinational circuits using programmable logic devices and
Verilog HDL.
4. To understand the implementation of various flip-flops, registers, counters and Verilog
code for flip-flops.
5. To implement finite state machine representation using Moore and Mealy models &
its minimization.

SYLLABUS
UNIT-I:
Design Concepts: Digital Hardware, Design process, Design of digital hardware,
Introduction to logic circuits – Variables and functions, Logic gates and networks,
Boolean algebra, Synthesis using gates, Design examples. Optimized implementation
of logic functions using K-Map, Quine- McCluskey Tabular method.
UNIT-II:
Number Representation: Addition and Subtraction of signed and unsigned numbers.
Combinational circuit building blocks: Half adder, Full adder, Multiplexers.
Decoders. Encoders, Code converters, BCD to 7-segment converter, Arithmetic
comparison circuits.
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UNIT-III:
Design of combinational circuits using Programmable Logic Devices (PLDs):
General structure of a Programmable Array Logic (PAL), Programmable Logic
Arrays(PLAs), Structure of CPLDs and FPGAs, 2- input and 3-input lookup tables
(LUTs)
Introduction to Verilog HDL: Verilog code for basic logic gates, adders, decoders.
UNIT-IV:
Sequential Circuits: Basic Latch, Gated SR Latch, gated D Latch, Master-Slave edge
triggered flip-flops, T Flip-flop, JK Flip-flop, Excitation tables. Registers, Counters,
Verilog code for flip-flops
UNIT-V:
Synchronous Sequential Circuits: Basic Design Steps, Finite State machine (FSM)
representation using Moore and Mealy state models, State minimization, Design of
FSM for Sequence Generation and Detection, Algorithmic State Machine charts.
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CONTENTS:
Combinational circuit building blocks: Half adder, Full adder, Multiplexers.
Decoders. Encoders, Code converters, BCD to 7-segment converter,
Arithmetic
comparison circuits
OUTCOMES:
Understand various number systems and design various combinational circuits
(UNIT-2)MODULE-II
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Adders :
• Adders are important not only in the computer but also
in many types of digital systems in which the numeric
data are processed.
Types of adder:
• Half adder
• Full adder
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Half adder : The half adder accepts two binary digits
on its inputs and produce two binary digits outputs, a
sum bit and a carry bit.
The half adder is an example of a simple, functional
digital circuit built from two logic gates. The half
adder adds to one-bit binary numbers (AB). The
output is the sum of the two bits (S) and the carry (C).
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Note that how the same two inputs are directed to
two different gates. The inputs to the XOR gate
are also the inputs to the AND gate. The input
"wires" to the XOR gate are tied to the input wires
of the AND gate; thus, when voltage is applied to
the A input of the XOR gate, the A input to the
AND gate receives the same voltage.
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Full adder : The full adder accepts two inputs bits and
an input carry and generates a sum output and an
output carry.
• The full-adder circuit adds three one-bit binary numbers
(Cin, A ,B) and outputs two one-bit binary numbers, a sum
• (S) and a carry (Cout). The full-adder is
usually a
• component in a cascade of adders, which add
8, 16, 32, etc. binary numbers.
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If you look closely, you'll see the full adder is simply two half
adders joined by an OR.
We can implement a full adder circuit with the help of two
half adder circuits. The first half adder will be used to add A
and B to produce a partial Sum. The second half adder
logic can be used to add CIN to the Sum produced by the
first half adder to get the final S output. If any of the half
adder logic produces a carry, there will be an output carry.
Thus, COUT will be an OR function of the half-adder Carry
outputs.

Truth Table:
• 2-input Exclusive-
OR Gate
Symb
ol
Truth
Table
2-input Ex-OR
Gate
B A
S
0 0
0
0 1
1
1 0
1
1 1
0
• 2-input AND
Gate
Symb
ol
Truth
Table
2-input AND
Gate
B A C
0 0 0
0 1 0
1 0 0
1 1 1
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Half adder truthtable
S=A  B (Exclusive OR)
C=A.B (AND)
Full adder truth
table
S= A  B  Cin C=AB +
Cin (A  B)
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What is the difference between
half adder and a full adder circuit?
The main difference between a half-adder and a full-
adder is that the full-adder has three inputs and two
outputs. The first two inputs are A and B and the third
input is an input carry designated as CIN. When a full
adder logic is designed we will be able to string eight
of them together to create a byte-wide adder and
cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the
normal output is designated as S.
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Example of a Combinatorial Circuit:
A Multiplexer (MUX)
Consider an integer ‘m’, which is
constrained by the following relation:
m = 2n, where m and n are both
integers.
• A m-to-1 Multiplexer has
• m Inputs: I0, I1, I2, ................ I(m-1)
• one Output: Y
• n Control inputs: S0, S1, S2, ...... S(n-1)
• One (or more) Enable input(s)
such that Y may be equal to one of the inputs, depending upon the
control inputs.
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Example: A 4-to-1 Multiplexer
I0
A 4-to-1 Multiplexer:
I1
I2
I3
S0 S1
Y
1 output
n control inputs
2n inputs
Enable (G)
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16
Characteristic Table of a Multiplexer
• If the MUX is enabled,
s0 s1
0 0 Y=I0
0 1 Y=I1
1 0 Y=I2
1 1 Y=I3
Putting the above information in the form of a Boolean equation,
Y =G. I0. S’1. S’0 + G. I1. S’1. S0 + G. I2. S1. S’0 + G. I3. S1. S0
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Implementing Digital Functions:
by using a Multiplexer: Example 1
Implementation of F(A,B,C,D)=∑ (m(1,3,5,7,8,10,12,13,14), d(4,6,15))
By using a 16-to-1 multiplexer:
F
I0
0
0
1
0
NOTE: 4,6 and 15 MAY BE
CONNECTED to either 0 or 1
I1
I2
I3
I4
I5
I8
I6
I9
I7
I11
I10
I13
I12
I14
I15
0
0
0
0
1
1
1
1
1
1
1
1
S3 S2 S1 S0
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by using a Multiplexer: Example 2
In this example to design a 3 variable logical function, we try to use a 4-
to-1 MUX rather than a 8-to-1 MUX.
F(x, y, z)=∑ (m(1, 2, 4, 7)
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19
by using a Multiplexer: Example 2 ….2
In a canonic form:
F = x’.y’.z+ x’.y.z’+x.y’.z’ +x.y.z …… (1)
One Possible Solution:
Assume that x = S1 , y = S0 .
If F is to be obtained from the output of a 4-to-1 MUX,
F =S’1. S’0. I0 + S’1. S0. I1 + S1. S’0. I2 + S1. S0. I3 ….(2)
From (1) and (2),
I0 = I3 =Z I1 = I2 =Z’
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Z
X Y
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Another Possible Solution:
Assume that z = S1 , x = S0 .
If F is to be obtained from the output of a 4-to-1 MUX,
F = S’0 .I0 . S1 + S’0 .I1 . S’1 + S0 .I2 . S’1 + S0 .I3 . S1 ………… (3)
From (1) and (2),
I0 = y’ = I2
I1 = y = I3
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23
The diagram below shows the relation between
a multiplexer and a Demultiplexer.
I0
I1
I2
I3
S1 S0
Y out
Y0
Y1
Y2
Y4
S1 S0
Input
4 to 1
MUX
1 to 4
DEMUX
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Demultiplexer (DMUX)/ Decoder
A 1-to-m DMUX, with ACTIVE HIGH Outputs, has
• 1 Input: I ( also called as the Enable input when the
device is called a Decoder)
• m ACTIVE HIGH Outputs: Y0, Y1, Y2,
..................................... …………….Y(m-1)
• n Control inputs: S0, S1, S2, ...... S(m-1)
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Characteristic table of the 1-to-4 DMUX
with ACTIVE HIGH Outputs:
Table 2
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Characteristic Table of a 1-to-4 DMUX, with
ACTIVE LOW Outputs:
Table 3
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A Decoder is a Demultiplexer with a change in
the name of the inputs :
Y0
Y1
Y2
Y4
S1 S0
ENABLE
INPUT
2 to 4
Decoder
When the IC is used as a Decoder, the input I is called an Enable
input
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28
DECODER: In Tables 2 and 3, when Enable is 0, i.e.
when the IC is Disabled, all the Outputs remain
‘unexcited’.
• The ‘unexcited’ state of an Output is 0 for an
IC with ACTIVE HIGH Outputs.
• The ‘unexcited’ state of an Output is 1 for an
IC with ACTIVE LOW Outputs.
Enable Input:
In a Decoder, the Enable Input can be ACTIVE
LOW or ACTIVE HIGH.
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29
Characteristic Table of a 2-to-4 DECODER, with
ACTIVE LOW Outputs and with ACTIVE LOW Enable
Input:
Table 4
Logic expressions for the outputs of the Decoder of Table 4:
Y0 = E + S1 + S0 Y1 = E + S1+ S0‘
Y2 = E + S1‘ + S0 Y3 = E + S1‘ + S0‘
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30
A cross-coupled set of NAND gates
Characteristic table:
X Y Q1 Q2
0 0 1 1
0 1 1 0
1 0 0 1
1 1 For this case, the outputs can be obtained
by using the following procedure: (i) Assume a set of values for
Q1 and Q2, which exist before the inputs of X = 1 and Y =1 are
applied. (ii) Obtain the new set of values for Q1 and Q2 (iii) Verify
whether the procedure yields valid results.
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31
A cross-coupled set of NAND gates …2
X Y
OLD Outputs NEW Outputs
Q1 Q2 Q1 Q2
0 0 ----- ---- 1 1
0 1 ---- ---- 1 0
1 0 ---- ---- 0 1
1 1 1 0 1 0
0 1 0 1
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22-Sep-21 PJF - 32
Overview of Encoder and
Decoder
• MUX Gate
• Rudimentary functions
• Binary Decoders
– Expansion
– Circuit implementation
• Binary Encoders
• Priority Encoders
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Multiplexer
• “Selects” binary information from one of many
input lines and directs it to a single output line.
• Also know as the “selector” circuit,
• Selection is controlled by a particular set of inputs
lines whose # depends on the # of the data input
lines.
• For a 2n-to-1 multiplexer, there are 2n data input lines
and n selection lines whose bit combination
determines which input is selected.
22-Sep-21
Combinational
Logic
PJF - 33
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22-Sep-21
Combinational
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PJF - 34
Multiplexer (cont.)
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2-to-1-Line Multiplexer
• Since 2 = 21, n = 1
• The single selection variable S has two values:
– S = 0 selects input I0
– S = 1 selects input I1
• The equation:
Y = S’ I0 + SI1
• The circuit:
22-Sep-21
Combinational
Logic
PJF - 35
S
I0
I1
Decoder
Enabling
Circuits
Y
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Example: 4-to-1 MUX using Cell Library Based
Design
22-Sep-21
Combinational
Logic
PJF - 36
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22-Sep-21
Combinational
Logic
PJF - 37
4–to–1-Line Multiplexer
using Transmission Gates
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MUX as a Universal Gate
• We can construct AND and NOT gates using 2-to-1
MUXs. Thus, 2-to-1 MUX is a universal gate.
22-Sep-21 PJF - 38 Combinational Logic
z = 0x + 1x’ = x’ z = x1x0 + 0x0’ = x1x0
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22-Sep-21 PJF - 39
• Until now, we have examined single-bit data
selected by a MUX. What if we want to select
m-bit data/words?
 Combine MUX blocks in parallel with
common select and enable signals
• Example: Construct a logic circuit that selects
between 2 sets of 4-bit inputs (see next slide
for solution).
Multiple Bit Selection
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22-Sep-21 PJF - 40
Example: Quad 2-to-1 MUX
• Uses four 4-to-1 MUXs
with common select (S)
and enable (E).
• Select line chooses
between Ai’s and Bi’s. The
selected four-wire digital
signal is sent to the Yi’s
• Enable line turns MUX on
and off (E=1 is on).
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22-Sep-21 PJF - 41
Implementing Boolean functions with
Multiplexers
• Any Boolean function of n variables can be
implemented using a 2n-1-to-1 multiplexer. A
MUX is basically a decoder with outputs ORed
together, hence this isn’t surprising.
• The SELECT signals generate the minterms of
the function.
• The data inputs identify which minterms are
to be combined with an OR.
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22-Sep-21 PJF - 42
Example
•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)
•There are n=3 inputs, thus we need a 22-to-1 MUX
•The first n-1 (=2) inputs serve as the selection lines
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22-Sep-21 PJF - 43
Efficient Method for implementing
Boolean functions
• For an n-variable function (e.g., f(A,B,C,D)):
– Need a 2n-1 line MUX with n-1 select lines.
– Enumerate function as a truth table with consistent ordering of
variables (e.g., A,B,C,D)
– Attach the most significant n-1 variables to the n-1 select lines (e.g.,
A,B,C)
– Examine pairs of adjacent rows (only the least significant variable
differs, e.g., D=0 and D=1).
– Determine whether the function output for the (A,B,C,0) and (A,B,C,1)
combination is (0,0), (0,1), (1,0), or (1,1).
– Attach 0, D, D’, or 1 to the data input corresponding to (A,B,C)
respectively.
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22-Sep-21 PJF - 44
The Other Example
• Consider F(A,B,C) = m(1,3,5,6). We can
implement this function using a 4-to-1 MUX as
follows.
• The index is ABC. Apply A and B to the S1 and
S0 selection inputs of the MUX (A is most sig,
S1 is most sig.)
• Enumerate function in a truth table.
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22-Sep-21 PJF - 45
MUX Example (cont.)
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
When A=B=0, F=C
When A=0, B=1, F=C
When A=1, B=0, F=C
When A=B=1, F=C’
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22-Sep-21 PJF - 46
MUX implementation of F(A,B,C) =
m(1,3,5,6)
A
B
C
C
C
C’
F
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22-Sep-21 PJF - 47
A larger Example
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22-Sep-21 PJF - 48
Rudimentary Functions
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22-Sep-21 PJF - 49
Selection
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22-Sep-21 PJF - 50
Enabling
• “gating” ?
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22-Sep-21 PJF - 51
The Other Code Converter
BCD-to-Seven-Segment Converter
• Seven-segment display:
– 7 LEDs (light emitting diodes), each one controlled
by an input
– 1 means “on”, 0 means “off”
– Display digit “3”?
• Set a, b, c, d, g to 1
• Set e, f to 0
d
a
b
c
e
f
g
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22-Sep-21 PJF - 52
BCD-to-Seven-Segment Converter
• Input is a 4-bit BCD code  4 inputs (w, x, y, z).
• Output is a 7-bit code (a,b,c,d,e,f,g) that allows
for the decimal equivalent to be displayed.
• Example:
– Input: 0000BCD
– Output: 1111110
(a=b=c=d=e=f=1, g=0)
d
a
b
c
e
f g
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22-Sep-21 PJF - 53
BCD-to-Seven-Segment (cont.)
Truth Table
Digit wxyz abcdefg
0 0000 1111110
1 0001 0110000
2 0010 1101101
3 0011 1111001
4 0100 0110011
5 0101 1011011
6 0110 X011111
7 0111 11100X0
Digit wxyz abcdefg
8 1000 1111111
9 1001 111X011
1010 XXXXXXX
1011 XXXXXXX
1100 XXXXXXX
1101 XXXXXXX
1110 XXXXXXX
1111 XXXXXXX
??
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22-Sep-21 PJF - 54
Decoders
• A combinational circuit that converts binary
information from n coded inputs to a
maximum 2n coded outputs
 n-to- 2n decoder
• n-to-m decoder, m ≤ 2n
• Examples: BCD-to-7-segment decoder, where
n=4 and m=10
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22-Sep-21 PJF - 55
Decoders (cont.)
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22-Sep-21 PJF - 56
1-2 Decoder
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22-Sep-21 PJF - 57
2-to-4 Decoder
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22-Sep-21 PJF - 58
2-to-4 Active Low Decoder
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22-Sep-21 PJF - 59
3-to-8 Decoder
address
data
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22-Sep-21 PJF - 60
3-to-8 Decoder (cont.)
• Three inputs, A0, A1, A2, are decoded into eight
outputs, D0 through D7
• Each output Di represents one of the minterms of the
3 input variables.
• Di = 1 when the binary number A2A1A0 = i
• Shorthand: Di = mi
• The output variables are mutually exclusive; exactly
one output has the value 1 at any time, and the
other seven are 0.
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22-Sep-21 PJF - 61
Decoder Expansion
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22-Sep-21 PJF - 62
Decoder with enable
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22-Sep-21 PJF - 63
• Any combinational circuit can be constructed using
decoders and OR gates! Why?
• Here is an example:
Implement a full adder circuit with a decoder and two
OR gates.
• Recall full adder equations, and let X, Y, and Z be the
inputs:
– S(X,Y,Z) = X+Y+Z = m(1,2,4,7)
– C(X,Y,Z) = m(3, 5, 6, 7).
• Since there are 3 inputs and a total of 8 minterms, we
need a 3-to-8 decoder.
Implementing Boolean functions using
decoders
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22-Sep-21 PJF - 64
Implementing a Binary Adder
Using a Decoder
S(X,Y,Z) = SUM m(1,2,4,7)
C(X,Y,Z) = SUM m(3,5,6,7)
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22-Sep-21 PJF - 65
Encoders
• An encoder is a digital circuit that performs
the inverse operation of a decoder. An
encoder has 2n input lines and n output lines.
• The output lines generate the binary
equivalent to the input line whose value is 1.
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22-Sep-21 PJF - 66
Encoders (cont.)
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22-Sep-21 PJF - 67
Encoder Example
• Example: 8-to-3 binary encoder (octal-to-binary)
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
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22-Sep-21 PJF - 68
Encoder Example (cont.)
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22-Sep-21 PJF - 69
Encoder Design Issues
• There are two ambiguities associated with the
design of a simple encoder:
1. Only one input can be active at any given time. If two
inputs are active simultaneously, the output produces an
undefined combination (for example, if D3 and D6 are 1
simultaneously, the output of the encoder will be 111.
2. An output with all 0's can be generated when all the
inputs are 0's,or when D0 is equal to 1.
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22-Sep-21 PJF - 70
Priority Encoders
• Solves the ambiguities mentioned above.
• Multiple asserted inputs are allowed; one has
priority over all others.
• Separate indication of no asserted inputs.
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22-Sep-21 PJF - 71
Example: 4-to-2 Priority Encoder
Truth Table
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22-Sep-21 PJF - 72
4-to-2 Priority Encoder (cont.)
• The operation of the priority encoder is such
that:
• If two or more inputs are equal to 1 at the
same time, the input in the highest-numbered
position will take precedence.
• A valid output indicator, designated by V, is
set to 1 only when one or more inputs are
equal to 1. V = D3 + D2 + D1 + D0 by inspection.
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22-Sep-21 PJF - 73
K-Maps
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22-Sep-21 PJF - 74
Logic Diagram
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22-Sep-21 PJF - 75
8-to-3 Priority Encoder
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22-Sep-21 PJF - 76
Uses of priority encoders (cont.)
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22-Sep-21 PJF - 77
Link Between Multiplexer and Decoder
• Note the regions of the multiplexer
– 1-to-2-line Decoder
– 2 Enabling circuits
– 2-input OR gate
• In general, for an 2n-to-1-line multiplexer:
– n-to-2n-line decoder
– 2n AND gates
S
I0
I1
Decoder
Enabling
Circuits
Y
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22-Sep-21 PJF - 78
Summary of Encoder and
Decoder
• MUX Gate
• Rudimentary functions
• Binary Decoders
– Expansion
– Circuit implementation
• Binary Encoders
• Priority Encoders
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1
Arithmetic Circuits
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In This Lecture
 Why are arithmetic circuits so important
 Adders
 Adding two binary numbers
 Adding more than two binary numbers
 Circuits Based on Adders
 Multipliers
 Functions that do not use adders
 Arithmetic Logic Units
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Motivation: Arithmetic Circuits
 Core of every digital circuit
 Everything else is side-dish, arithmetic circuits are the heart of the digital
system
 Determines the performance of the system
 Dictates clock rate, speed, area
 If arithmetic circuits are optimized performance will improve
 Opportunities for improvement
 Novel algorithms require novel combinations of arithmetic circuits, there
is always room for improvement
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Example: ARM Microcontroller
 Most popular embedded
micro controller.
 Contains:
 Multiplier
 Accumulator
 ALU/Adder
 Shifter
 Incrementer
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Example: ARM Instructions
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Arithmetic Based
Instructions of ARM
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Types of Arithmetic Circuits
 In order of complexity:
 Shift / Rotate
 Compare
 Increment / Decrement
 Negation
 Addition / Subtraction
 Multiplication
 Division
 Square Root
 Exponentation
 Logarithmic / Trigonometric Functions
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Relation Between Arithmetic Operators
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Addition
 Addition is the most important operation in computer
arithmetic. Our topics will be:
 Adding 1-bit numbers : Counting bits
 Adding two numbers : Basics of addition
 Circuits based on adders : Subtractors, Comparators
 Adding multiple numbers : Chains of Adders
 Later we will also talk about fast adder architectures
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Half-Adder (2,2) Counter
 The Half Adder (HA) is the simplest arithmetic block
 It can add two 1-bit numbers, result is a 2-bit number
 Can be realized easily
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Full-Adder (3,2) Counter
 The Full Adder (FA) is the essential
arithmetic block
 It can add three 1-bit numbers, result
is a 2-bit number
 There are many realizations both at
gate and transistor level.
 Since it is used in building many
arithmetic operations, the
performance of one FA influences the
overall performance greatly.
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Adding Multiple 1-bit Numbers
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Adding Multiple Digits
 Similar to decimal addition
 Starting from the right, each digit is added
 The carry from one digit is added to the digit to the left
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Ripple Carry Adder (RCA)
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Curse of the Carry
The most significant outputs of the adder
depends on the least significant inputs
94
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Adding Multiple Numbers
 Multiple fast adders not a good idea
 If more than 2 numbers are to be added, multiple fast adders are not
really efficient
 Use an array of ripple carry adders
 Popular and efficient solution
 Use carry save adder trees
 Instead of using carry propagate adders (the adders we have seen so far),
carry save adders are used to reduce multiple inputs to two, and then a
single carry propagate adder is used to sum up.
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Array of Ripple Carry Adders
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Carry Save Principle
 Reduces three numbers to two with a single gate delay
C + S = E + F + G
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Carry Save Principle
Z = D + E + F + G + H
An array of carry save
adders reduce the inputs to
two
A final (fast) carry propagate
adder (CPA) merges the two
numbers
Performance mostly
dictated by CPA
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Multipliers
 Largest common arithmetic block
 Requires a lot of calculation
 Has three parts
 Partial Product Generation
 Carry Save Tree to reduce partial products
 Carry Propagate Adder to finalize the addition
 Adder performance (once again) is important
 Many optimization alternatives
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Decimal Multiplication
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Binary Multiplication
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For n-bit Multiplier m-bit Multiplicand
 Generate Partial Products
 For each bit of the multiplier the partial product is either
 when ‘0’: all zeroes
 when ‘1’: the multiplicand achieved easily by AND gates
 Reduce Partial Products
 This is the job of a carry save adder
 Generate the Result (n + m bits)
 This is a large, fast Carry Propagate Adder
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Parallel
Multiplier
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Operations Based on Adders
 Several well-known arithmetic operation are based on adders:
 Negator
 Incrementer
 Subtracter
 Adder Subtracter
 Comparator
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Negating Two’s Complement
Numbers
 To negate a two’s
complement number
-A = A + 1
 All bits are inverted
 One is added to the result
 Can be realized easily by an
adder.
 B input is optimized away
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Incrementer
 B input is zero
 Carry In (Cin) of the adder
can be used as the
Increment (Inc) input
 Decrementer similar in
principle
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Subtracter
 B input is inverted
 Cin of the adder is usedto
complement B
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Subtracter
 B input is inverted
 Cin of the adder is used to
complement B
 It can be made
programmable so that both
additions and subtractions
can be performed at the
same time
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Comparator
 Based on a Subtractor
(A = B) = EQ
(A != B) = EQ
(A > B) = GE EQ
(A >= B) = GE
(A < B) = GE
(A <= B) = GE + EQ
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Functions Realized Without Adders
 Not all arithmetic functions are realized by using adders
 Shift / Rotate Units
 Binary Logic functions are also used by processors
 AND
 OR
 XOR
 NOT
These are implemented very easily
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Shifters
 Logical shifter: shifts value to left or right and fills empty
spaces with 0’s
 Ex: 11001 >> 2 = ??
 Ex: 11001 << 2 = ??
 Arithmetic shifter: same as logical shifter, but on right shift,
fills empty spaces with the old most significant bit (msb).
 Ex: 11001 >>> 2 = ??
 Ex: 11001 <<< 2 = ??
 Rotator: rotates bits in a circle, such that bits shifted off one
end are shifted into the other end
 Ex: 11001 ROR 2 = ??
 Ex: 11001 ROL 2 = ??
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35
Shifters
 Logical shifter: shifts value to left or right and fills empty
spaces with 0’s
 Ex: 11001 >> 2 = 00110
 Ex: 11001 << 2 = 00100
 Arithmetic shifter: same as logical shifter, but on right shift,
fills empty spaces with the old most significant bit (msb).
 Ex: 11001 >>> 2 = 11110
 Ex: 11001 <<< 2 = 00100
 Rotator: rotates bits in a circle, such that bits shifted off one
end are shifted into the other end
 Ex: 11001 ROR 2 = 01110
 Ex: 11001 ROL 2 = 00111
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Shifter Design
A3:0 3:0
shamt1:0
>>
2
4 4 Y
Y3
2
Y1
Y0
00
01
Y
10
11
S1:0
S1:0
1:0
S1:0
00 S
01
10
11
00
01
10
11
00
01
10
11
A3 A2 A1 A0 shamt1:0
2
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Shifters as Multipliers and Dividers
 A left shift by N bits multiplies a number by 2N
 Ex: 00001 << 2 = 00100 (1 ×
 Ex: 11101 << 2 = 10100 (-3 ×
22 = 4)
22 = -12)
 The arithmetic right shift by N divides a number by 2N
 Ex: 01000 >>> 2 = 00010
 Ex: 10000 >>> 2 = 11100
(8 ÷ 22 = 2)
(-16 ÷ 22 = -4)
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Other Functions
 We have covered 90% of the arithmetic functions commonly
used in a CPU
 Division
 Dedicated architectures not very common
 Mostly implemented by existing hardware (multipliers, subtractors
comparators) iteratively
 Exponential, Logarithmic, Trigonometric Functions
 Dedicated hardware (less common)
 Numerical approximations:
exp(x) = 1 + x2/2! + x3/3! + …
 Look-up tables (more common)
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Arithmetic Logic Unit
The reason why we study digital circuits:
the part of the CPU that does something (other than copying data)
Defines the basic operations that the CPU can perform directly
 Other functions can be realized using the existing ones iteratively. (i.e.
multiplication can be realized by shifting and adding)
Mostly, a collection of resources that work in parallel.
 Depending on the operation one of the outputs is selected
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Example: Arithmetic Logic Unit
(ALU), pg243
ALU
N N
A B
N
Y
3 F
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
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Example: ALU Design
+
2
0
1
Cout
0
1
F2
1:0
[N-1] S
A B
N N
N
N
N N
N
N
N
Y
2 F
Zero
Extend
3
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
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Set Less Than (SLT) Example
 Configure a 32-bit ALU for the set if
less than (SLT) operation. Suppose
A = 25 and B = 32.
 A is less than B, so we expect Y to be the
32-bit representation of 1
(0x00000001).
+
2
0
1
Cout
3
0
1
F2
F1:0
[N-1] S
B
N
A
N
N
N
N N
N
N
N
Y
2
Zero
Extend
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43
Set Less Than (SLT)
Example
 Configure a 32-bit ALU for the set if
less than (SLT) operation. Suppose
A = 25 and B = 32.
 A is less than B, so we expect Y to be
the 32-bit representation of 1
(0x00000001).
 For SLT, F2:0 = 111.
 F2 = 1 configures the adder unit as a
subtracter. So 25 - 32 = -7.
 The two’s complement
representation of
• -7 has a 1 in the most significant bit,
so S31 = 1.
 With F1:0 = 11, the final multiplexer selects
Y = S31 (zero extended) =0x00000001
+
2
0
1
Cout
Y
3
0
1
F2
F1:0
[N-1] S
B
N
A
N
N
N
N N
N
N
N
2
Zero
Extend
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Unit 2 module-2

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