The document provides a comprehensive overview of a 1:4 demultiplexer, detailing its function as a device that routes a single input to one of four outputs based on selection lines. It includes descriptions of various configurations, applications such as memory selection in computer systems, and provides VHDL code examples for implementation. Additionally, it highlights commonly used integrated circuits (ICs) and the operational principles of demultiplexers.

1. Title: 1:4 Demultiplexer using Xilinx
Software: Xilinx ISE
I. Introduction
Demultiplexer (Demux)
The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the
MUX , demux is a one-to-many circuit. With the use of a demultiplexer , the binary data can be
bypassed to one of its many output data lines.
Demultiplexers are mainly used in Boolean function generators and decoder circuits. Different
input/output configuration demultiplexers are available in the form of single integrated circuits
(ICs).
Also, the facility of cascading two or more IC circuits helps to generate multiple output
demultiplexers. Let us get a brief idea of demultiplexers and its types.
II. What is Demultiplexer?
The process of getting information from one input and transmitting the same over one of many
outputs is called demultiplexing. A demultiplexer is a combinational logic circuit that receives
the information on a single input and transmits the same information over one of 2n possible
output lines.
The bit combinations of the select lines control the selection of specific output line to be
connected to the input at given instant. The below figure illustrates the basic idea of
demultiplexer , in which the switching of the input to any one of the four outputs is possible at a
given instant.

2. Demultiplexers are also called as data distributors, since they transmit the same data which is
received at the input to different destinations.
Thus, a demultiplexer is a 1-to-N device where as the multiplexer is an N-to-1 device. The figure
below shows the block diagram of a demultiplexer or simply a DEMUX.
It consists of 1 input line, n output lines and m select lines. In this, m selection lines are required
to produce 2m possible output lines (consider 2m = n). For example, a 1-to-4 demultiplexer
requires 2 (22) select lines to control the 4 output lines.
There are several types of demultiplexers based on the output configurations such as 1:4, 1:8 and
1:16.
These are available in different IC packages and some of the most commonly used demultiplexer
ICs includes 74139 (dual 1:4 DEMUX), 73136 (1:8 DEMUX), 74154 (1:16 DEMUX), 74159
(1:16 DEMUX open collector type), etc.
III. 1-to-4 Demultiplexer
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and four outputs
(Y0 to Y3). The input data goes to any one of the four outputs at a given time for a particular
combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer which means that two select lines and
4 output lines. The block diagram of 1:4 DEMUX is shown below.

3. The truth table of this type of demultiplexer is given below. From the truth table it is clear that,
when S1=0 and S0= 0, the data input is connected to output Y0 and when S1= 0 and s0=1, then
the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of select lines.
From the table, the output logic can be expressed as min terms and are given below.
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.

4. From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented by using four
3-input AND gates and two NOT gates as shown in figure below. The two selection lines enable
the particular gate at a time.
So depends on the combination of select inputs, input data is passed through the selected gate to
the associated output.
This type of demultiplexer is available in IC form and a typical IC 74139 is most commonly used
dual 1-to-4 demultiplexer. It has two independent demultiplexers and each DEMUX accepts two
binary inputs as select lines and four mutually exclusive active-low outputs.
Both demultiplexers share a common set of selection lines so they are selected in parallel. Also,
each demultiplexer consists of enable pin or data input, for one demultiplexer it is active high
data input and for other it is active low data input.
IV. Applications of Demultiplexer
Since the demultiplexers are used to select or enable the one signal out of many, these are
extensively used in microprocessor or computer control systems such as
 Selecting different IO devices for data transfer
 Choosing different banks of memory
 Depends on the address, enabling different rows of memory chips
 Enabling different functional units.

5. Other than these, demultiplexers can be found in a wide variety of application such as
 Synchronous data transmission systems
 Boolean function implementation (as we discussed full subtractor function above)
 Data acquisition systems
 Combinational circuit design
 Automatic test equipment systems
 Security monitoring systems (for selecting a particular surveillance camera at a time), etc.

6. VHDL Code for 1 to 4 Demux
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demux_1to4 is
port(
F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end demux_1to4;
architecture bhv of demux_1to4 is
begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
elsif (S0 ='1' and S1 = '0') then
B <= F;
elsif (S0 ='0' and S1 = '1') then
C <= F;
else
D <= F;
end if;
end process;
end bhv;
VHDL Testbench Code for 1 to 4 Demux
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_demux IS
END tb_demux;
ARCHITECTURE behavior OF tb_demux IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT demux_1to4
PORT(
F : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;

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A : OUT std_logic;
B : OUT std_logic;
C : OUT std_logic;
D : OUT std_logic
);
END COMPONENT;
--Inputs
signal F : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
--Outputs
signal A : std_logic;
signal B : std_logic;
signal C : std_logic;
signal D : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: demux_1to4 PORT MAP (
F => F,
S0 => S0,
S1 => S1,
A => A,
B => B,
C => C,
D => D
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
F <= '1';
S0 <= '0'; S1 <= '0';
wait for 100 ns;
S0 <= '1'; S1 <= '0';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;

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S0 <= '1'; S1 <= '1';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
Testbench waveform for 1 to 4 Demux