In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
Design of 4:16 decoder using reversible logic gatesIJERA Editor
Reversible logic has received great importance in the recent years because of its feature of reduction in power
dissipation. It finds application in low power digital designs, quantum computing, nanotechnology, DNA
computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using
reversible logic. Decoders are one of the most important circuits used in combinational logic. Different
approaches have been proposed for their design. In this article, we have proposed a novel design of 4:16.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywords— advanced computing, Reversible logic circuits, reversible logic gates and comparator
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
Design of 4:16 decoder using reversible logic gatesIJERA Editor
Reversible logic has received great importance in the recent years because of its feature of reduction in power
dissipation. It finds application in low power digital designs, quantum computing, nanotechnology, DNA
computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using
reversible logic. Decoders are one of the most important circuits used in combinational logic. Different
approaches have been proposed for their design. In this article, we have proposed a novel design of 4:16.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywords— advanced computing, Reversible logic circuits, reversible logic gates and comparator
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Design and minimization of reversible programmable logic arrays and its reali...Sajib Mitra
Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbage and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbage, quantum costs and delay.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A low power adder using reversible logic gateseSAT Journals
Abstract
Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power
VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in
the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has
the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic
gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and
their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition,
subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates.
Index Terms: Reversible logic, Quantum computing, Garbage outputs, Constant inputs
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Design and minimization of reversible programmable logic arrays and its reali...Sajib Mitra
Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbage and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbage, quantum costs and delay.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A low power adder using reversible logic gateseSAT Journals
Abstract
Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power
VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in
the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has
the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic
gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and
their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition,
subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates.
Index Terms: Reversible logic, Quantum computing, Garbage outputs, Constant inputs
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Delay Optimization of Low Power Reversible Gate using MOS Transistor Level de...IJERA Editor
In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base
application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the
power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI
circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using
the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce
energy loss due to the information bits lost during the operation information loss occurs because the total number
of output signals generated is less than total number of input signals applied. In reversible if the input vector can
be uniquely recovered from the output vector and if there is a one to one correspondence between its input and
output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS
transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future
in design of low power consumption circuits and high speed application.
FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGICBUKYABALAJI
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in fields of Digital Signal Processing, Quantum
Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main purposes
of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage outputs.
This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed architecture
Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Key Words:Quantum Computing, Reversible Logic,
Garbage outputs, Constant Inputs.
FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGICBUKYABALAJI
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in fields of Digital Signal Processing, Quantum
Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main purposes
of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage outputs.
This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed architecture
Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
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Low Power Reversible Parallel Binary Adder/Subtractor
1. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
DOI : 10.5121/vlsic.2010.1303 23
Low Power Reversible Parallel Binary
Adder/Subtractor
Rangaraju H G1
, Venugopal U2
, Muralidhara K N3
, Raja K B 2
1
Department of Telecommunication Engineering, Bangalore Institute of Technology,
Bangalore, India
rang_raju@yahoo.com
2
Department of Electronics and Communication Engineering, University Visvesvaraya
College of Engineering, Bangalore, India
venu.ubaradka@gmail.com
3
Department of Electronics and Communication Engineering, P E S College of
Engineering, Mandya, Karnataka, India
Abstract
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in
Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an
important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel
Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design
approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number reversible gates, Garbage
input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor
with Design III is efficient compared to Design I, Design II and existing design.
Keywords
Reversible Logic, Garbage Input/output, Quantum Cost, Low Power, Reversible Parallel Binary
Adder/Subtractor.
1. Introduction
Reversible computing was started when the basis of thermodynamics of information processing was
shown that conventional irreversible circuits unavoidably generate heat because of losses of
information during the computation [1]. The different physical phenomena can be exploited to
construct reversible circuits avoiding the energy losses. One of the most attractive architecture
requirements is to build energy lossless small and fast quantum computers. Most of the gates used in
digital design are not reversible for example NAND, OR and EXOR gates.
A Reversible circuit/gate can generate unique output vector from each input vector, and vice versa,
i.e., there is a one to one correspondence between the input and output vectors. Thus, the number of
outputs in a reversible gate or circuit has the same as the number of inputs, and commonly used
traditional NOT gate is the only reversible gate. Each Reversible gate has a cost associated with it
called Quantum cost. The Quantum cost of a Reversible gate is the number of 2*2 Reversible gates or
Quantum logic gates required in designing. One of the most important features of a Reversible gate is
its garbage output i.e., every input of the gate which is not used as input to other gate or as a primary
output is called garbage output.
In digital design energy loss is considered as an important performance parameter. Part of the energy
dissipation is related to non-ideality of switches and materials. Higher levels of integration and new
fabrication processes have dramatically reduced the heat loss over the last decades. The power
dissipation in a circuit can be reduced by the use of Reversible logic. Landauer’s [2] principle states
that irreversible computations generates heat of K*Tln2 for every bit of information lost, where K is
Boltzmann’s constant and T the absolute temperature at which the computation performed. Bennett
[3] showed that if a computation is carried out in Reversible logic zero energy dissipation is possible,
as the amount of energy dissipated in a system is directly related to the number of bits erased during
2. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
24
computation. The design that does not result in information loss is irreversible. A set of reversible
gates are needed to design reversible circuit. Several such gates are proposed over the past decades.
Arithmetic circuits such as Adders, Subtractors, Multipliers and Dividers are the essential blocks of a
Computing system. Dedicated Adder/Subtractor circuits are required in a number of Digital Signal
Processing applications. Several designs for binary Adders and Subtractors are investigated based on
Reversible logic. Minimization of the number of Reversible gates, Quantum cost and garbage
inputs/outputs are the focus of research in Reversible logic.
Contribution: In this paper, novel three Design types viz., Design I, Design II and Design III of
Reversible Eight-bit Parallel Binary Adder/Subtractor are proposed. The Reversible gates such as F,
FG, TR and PG are used to construct Design I, Design II and Design III Adder/Subtractor. The
performance of Design III is better in terms of number of gates, Garbage inputs/outputs and Quantum
Cost in comparison with Design I and Design II.
Organization: The paper is organized into the following sections. Section 2 is an overview of
Reversible gates. The Background work is described in section 3. Section 4 is the proposed design,
Result analysis of the proposed design is presented in section 5 and Conclusions are contained in
section 6.
2. Reversible Gates
The simplest Reversible gate is NOT gate and is a 1*1 gate. Controlled NOT (CNOT) gate is an
example for a 2*2 gate. There are many 3*3 Reversible gates such as F, TG, PG and TR gate. The
Quantum Cost of 1*1 Reversible gates is zero, and Quantum Cost of 2*2 Reversible gates is one. Any
Reversible gate is realized by using 1*1 NOT gates and 2*2 Reversible gates, such as V, V+
(V is
square root of NOT gate and V+
is its hermitian) and FG gate which is also known as CNOT gate. The
V and V+
Quantum gates have the property given in the Equations 1, 2 and 3.
V * V = NOT ……………… (1)
V * V+
= V+
* V = I ……….. (2)
V+
* V+
= NOT ……………. (3)
The Quantum Cost of a Reversible gate is calculated by counting the number of V, V+
and CNOT
gates.
2.1 NOT Gate
The Reversible 1*1 gate is NOT Gate with zero Quantum Cost is as shown in the Figure 1.
A P = A1
Figure1. NOT gate
2.2 Feynman / CNOT Gate
The Reversible 2*2 gate with Quantum Cost of one having mapping input (A, B) to output (P = A, Q
= A ⊕ B) is as shown in the Figure 2.
3. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
25
A P = A
B Q = A ⊕ B
Figure2. Feynman/CNOT gate
2.3 Toffoli Gate
The 3*3 Reversible gate with three inputs and three outputs. The inputs (A, B, C) mapped to the
outputs (P=A, Q=B, R=A.B ⊕ C) is as shown in the Figure 3.
A P = A
B Q = B
C R = A.B ⊕ C
Figure3. Toffoli gate
Toffoli gate [4] is one of the most popular Reversible gates and has Quantum Cost of 5. It requires
2V, 1 V+
and 2 CNOT gates. Its Quantum implementation is as shown in Figure 4.
A P = A
B Q = B
C R = A.B C
Figure4. Quantum implementation of Toffoli gate
2.4 Peres Gate
The three inputs and three outputs i.e., 3*3 reversible gate having inputs (A, B, C) mapping to outputs
(P = A, Q = A ⊕ B, R = (A.B) ⊕ C). Since it requires 2 V+
, 1 V and 1 CNOT gate, it has the Quantum
cost of 4. The Peres gate and its Quantum implementation are as shown in the Figure 5 and 6
respectively.
A P = A
B Q = A ⊕ B
C R = (A.B) ⊕ C
Figure5. Peres gate
TG
PG
V V V+
4. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
26
A P = A
B Q = A ⊕ B
C R = (A.B) ⊕ C
Figure6. Quantum implementation of Peres gate
2.5 Fredkin Gate
Reversible 3*3 gate maps inputs (A, B, C) to outputs (P=A, Q=A'B+AC, R=AB+A'C) having
Quantum cost of 5 and it requires two dotted rectangles, is equivalent to a 2*2 Feynman gate with
Quantum cost of each dotted rectangle is 1, 1 V and 2 CNOT gates. Fredkin gate and its Quantum
implementations are shown in Figure 7 and 8 respectively.
A P = A
B Q = A1
B + A C
C R = A B + A1
C
Figure7. Fredkin gate
A P = A
B Q = A1
B+A C
C R = A B + A1
C
Figure8. Quantum implementation of Fredkin gate
2.6 TR Gate
The gate has 3 inputs and 3 outputs having inputs (A, B, C) mapped to the outputs (P=A, Q=A ⊕ B,
R= (A.B1
) ⊕ C). TR gate is shown in Figure 9.
A P = A
B Q = A ⊕ B
C R = (A. B1
) ⊕ C
Figure9. TR gate
F
TR
V V
V+
V
V
V+
5. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
27
The Quantum cost of TR gate can be estimated by realizing from 1 Toffoli gate, 2 NOT gates and 1
CNOT gate as shown in the Figure 10. Thus the Quantum cost of TR gate will be Quantum cost of
CNOT gate plus Quantum cost of 1 Toffoli gate which is equal to 6.
A P = A
B Q = A ⊕ B
C R = (AB1
) ⊕ C
Figure10. Quantum implementation of TR gate
3. Literature Survey
Thapliyal and Ranganathan [5] proposed the design of Reversible Binary Subtractor using TR Gate.
The particular function like Binary Subtraction is implemented using TR gate effectively by reducing
number of Reversible gates, Garbage outputs and Quantum Cost. Thapliyal and Ranganathan [6]
presented a design of Reversible latches viz., D Latch, JK latch, T latch and SR latch that are
optimized in terms of quantum cost, delay and garbage outputs.. Lihui Ni et al., [7] described general
approach to construct the Reversible full adder and can be extended to a variety of Reversible full-
adders with only two Reversible gates. Irina Hashmi and Hafiz Hasan Babu [8] designed an efficient
reversible barrel shifter which is capable of left shift/rotate used for high speed ALU applications.
Robert Wille et al., [9] explored two techniques from irreversible equivalence checking applied in the
reversible circuit domain. (i) Decision diagram Technique equivalence checking for quantum circuits
and (ii) Boolean satifiability checking for garbage input/outputs. Noor Muhammed Nayeem et al.,
[10] presented designs of Reversible shift registers such as serial-in serial-out, serial-in parallel-out,
parallel-in serial-out, parallel-in parallel-out and universal shift registers. Majid Mohammadi,
Mohammad Eshghi et al., [11] proposed a synthesis method to realize a Reversible Binary Coded
Decimal adder/subtractor circuit. Genetic algorithms and don’t care concepts used to design and
optimize all parts of a Binary Coded Decimal adder circuit in terms of number of garbage
inputs/outputs and quantum cost.
Majid Mohammadi and Mohammad Eshghi [12] explained about the behavioral description and
synthesis of quantum gates. To synthesize reversible logic circuits, V and V+ gates are shown in the
truth table form and shown that bigger circuits with more number of gates can be synthesized. Rekha
James et al., [13] proposed an implementation of Binary Coded Decimal adder in Reversible logic,
which is basis of ALU for reversible CPU. VLSI implementations using one type of building block
can decrease system design and manufacturing cost. Himanshu Thapliyal and Vinod [14] presented
the Transistor realization of a new 4*4 Reversible TSG gate. The gate alone operates as a Reversible
full adder. The Transistor realizations of 1-bit Reversible full adder, ripple carry adder and carry skip
adder are also discussed. Himanshu Thapliyal and Srinivas [15] proposed a 3x3 Reversible TKS gate
with two of its outputs working as 2:1 multiplexer. The gate used to design a Reversible half adder
and further used to design multiplexer based Reversible full adder. The multiplexer based full adder is
further used to design Reversible 4x4 Array and modified Baugh Woolley multipliers.
Yvan Van Rentergem and Alexis De Vos [16] presented four designs for Reversible full-adder
circuits and the implementation of these logic circuits into electronic circuitry based on C-MOS
technology and pass-transistor design. The chip containing three different Reversible full adders are
discussed. Mozammel Khan [17] proposed realizations of ternary half and full-adder circuits using
V V V+
6. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
28
generalized ternary gates. Mozammel Khan [18] discussed quantum realization of ternary Toffoli gate
which requires fewer gates than the existing literature. Abhinav Agrawal and Niraj Jha [19] presented
the first practical synthesis algorithm and tool for Reversible functions with a large number of inputs.
It uses positive-polarity Reed-Muller decomposition at each stage to synthesize the function as a
network of Toffoli gates. Pawel Kerntopf [20] explained multipurpose Reversible gates and example
of efficient binary multipurpose reversible gates.
4. Proposed Model
4.1 Adder/Subtractor – Design I
4.1.1 Half Adder/Subtractor
Reversible half Adder/Subtractor–Design I is implemented with four Reversible gates of which two F
and two FG gates is shown in the Figure 11. The numbers of Garbage outputs are three represented as
g1 to g3, Garbage inputs are two represented by logical zero and Quantum Cost is twelve as it requires
two FG gates each costing one and two F gates each costing five each.
Figure11. Reversible Half Adder/Subtractor – Design I
4.1.2 Full Adder/Subtractor
The Design I Reversible Full Adder/Subtractor with five FG, two F and a TR gate is as shown in the
Figure 12. The three inputs are A, B and Cin and the outputs are Sum/Difference (S/D) and
Carry/Borrow (C/B). The Control (Ctrl) input differentiates the Addition and Subtraction
functionalities. For Ctrl value zero i.e., Logical low the circuit performs addition and Subtraction for
Ctrl value one i.e., Logical high. The numbers of Garbage inputs are 3 represented by logical zero.
The Garbage outputs are 5 represented by g1 to g5. The Sum/Difference function is realized from FG4
gate, and the Carry/Borrow function is realized from the output of TR gate. The Quantum Cost for
five FG gates are five as each gate costs one, for two F gates is ten as each gate costs five, one TR
gate costs six and total design Quantum Cost is 21.
Figure12. Reversible Full Adder/Subtractor – Design I
g3
g5
g4
g2
g1
0 C/B
Ctrl
S/D
A
B
0
Cin
0
FG4
F1
FG1
FG2
FG3
F2 TR
FG5
A
S/D
C/B
Ctrl
B
0
0
g1 g2
g3
FG1
FG2
F1 F2
7. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
29
4.2 Adder/Subtractor – Design II
4.2.1 Half Adder/Subtractor
Figure13. Reversible Half Adder/Subtractor – Design II
Reversible half Adder/Subtractor–Design II is implemented with three Reversible gates of which two
are FG gates with each having Quantum cost of one and a TR gate with six Quantum cost is as shown
in the Figure 13. The number of Garbage outputs is two i.e., g1 and g2, Garbage inputs one denoted by
logical zero and total Quantum Cost is eight.
4.2.2 Full Adder/Subtractor
Figure14. Reversible Full Adder/Subtractor – Design II
Two TR gates and two FG gates are used to realize Deign II Reversible Full Adder/Subtractor unit is
shown in Figure 14. The three inputs are A, B and Cin, the outputs are S/D and C/B. For Ctrl value
zero the circuit performs addition and Subtraction for Ctrl value one. The numbers of Garbage inputs
are 1 represented by logical zero. The Garbage outputs are 3 represented by g1 to g3. The Quantum
Cost for the design is 14. A Quantum Cost advantage of 7 is obtained when compared to
Adder/Subtractor Design I. Quantum Cost advantage is due to the realization of Arithmetic blocks
(Adder and Subtractor) using two TR gates as against three numbers of 3*3 gates for Design I.
4.3 Adder/Subtractor – Design III
4.3.1 Half Adder/Subtractor
Reversible half Adder/Subtractor–Design III is implemented with three Reversible gates of which two
are FG gates each having Quantum cost of one and a PG gate with Quantum cost four is as shown in
the Figure 15. The numbers of Garbage outputs is two i.e., g1 and g2, Garbage inputs are one denoted
by logical zero and Quantum Cost is six.
Ctrl
S/D
0
C/B
g3
g2
g1
Cin
B
A
FG1 FG2
TR1 TR2
g2
S/D
0 C/B
g1
B
A
Ctrl
FG1 FG2
TR
8. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
30
Figure15. Reversible Half Adder/Subtractor – Design III
4.3.2 Full Adder/Subtractor
The Reversible Full Adder/Subtractor Design III consists of two FG, two PG gates, and their
interconnections are shown in the Figure 16. The three inputs are A, B, and Cin, The outputs are S/D
and C/B. For Ctrl value zero the circuit performs addition and Subtraction for Ctrl value one. The
numbers of Garbage inputs are 1 represented by logical zero. The Garbage outputs are 3 represented
by g1 to g3. The Quantum Cost for the design is 10. A Quantum Cost advantage of 11 is obtained
when compared to Adder/Subtractor Design I and of 4 when compared to Adder/Subtractor Design II.
Quantum Cost advantage is due to the realization of Arithmetic blocks using two PG gates as against
two F and one TR gate for Design I and two TR gates for Design II.
Figure16. Reversible Full Adder/Subtractor – Design III
4.4 Reversible Eight-bit Parallel Binary Adder/Subtractor
Figure17. Reversible Eight-bit parallel Binary Full Adder/Subtractor
Cin
C/B
g2
S/D
A
Ctrl
B
0
g1
g3
FG1 FG2
PG1 PG2
C/B
g2
Ctrl
A
B
0
g1 S/D
FG1 FG2
PG
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The Half and Full Adder/Subtractor Design I, Design II and Design III are used to construct
Reversible eight-bit Parallel Binary Adder/Subtractor is shown in the Figure 17. The ctrl input is used
to differentiate eight-bit addition and subtraction functions. The two eight-bit binary numbers are A0
to A7 and B0 to B7. Carry/Borrow is obtained after Addition/Subtraction is represented by C_B1 to
C_B7. The outputs Sum/Difference and Carry are shown as S_D0 to S_D7 and C_B8 respectively.
The implementation requires seven Full Adder/Subtractor units and one half Adder/Subtractor units in
which first stage is half Adder/Subtractor.
5. Results
5.1 Reversible Full Adder/Subtractor
The comparison of Reversible Full Adder/Subtractor Design I, Design II and Design III in terms of
the number gates, number of Garbage inputs/outputs and Quantum Cost of the logics is shown in the
Table 1.
It is observed that Design III has better performance compared to Design II and Design I. The number
of Reversible gates required for Design III is only 4 as compared to 8 and 4 in the cases of Design I
and II respectively, which indicates that the improvement of 100% compared to Design I. The
Garbage outputs are 5 in the case of Design I, whereas 3 in the case of Design II and Design III, i.e.,
the improvement is 65% in Design III compared to Design I. The Garbage inputs are 3 in the case of
Design I and one in case of Design II and Design III, gives 200% improvement in Design III
compared to Design I. Quantum Cost of Design III, Design II and Design I are 21, 14 and 10
respectively, resulting in improvement of Design III over Design II and Design I are 40% and 110%
respectively.
Table1. Comparison of Reversible Full Adder/Subtractor
Reversible
Gates
Garbage
outputs
Garbage inputs Quantum Cost
Add/Sub–Design I 08 05 03 21
Add/Sub–Design II 04 03 01 14
Add/Sub–Design III 04 03 01 10
5.2 Reversible eight-bit Parallel Binary Adder/Subtractor
The number of gates, Garbage inputs/outputs and Quantum Cost for Reversible eight-bit parallel
binary Adder/Subtractor Design I, Design II and Design III are compared as shown in the Table 2.
Table2. Comparison of Reversible eight-bit Parallel Binary Adder/Subtractor design
Reversible Gates Garbage outputs Garbage inputs Quantum Cost
Add/Sub– Design I 60 38 23 159
Add/Sub–Design II 31 23 08 106
Add/Sub- Design III 31 23 08 76
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It is seen that Design III has better performance compared to Design II and Design I. The number of
Reversible gates required for Design III is 31 as compared to 60 and 31 in the cases of Design I and II
respectively, which is an improvement of 93.5% compared to Design I. The Garbage outputs are 38 in
the case of Design I, whereas 23 in the case of Design II and Design III, yields an improvement of
65.21% in Design III compared to Design I. The Garbage inputs are 23 in the case of Design I and 8
in case of Design II and Design III, resulting 187.5% improvement in Design III compared to Design
I. Quantum Cost of Design III, Design II and Design I are 76, 106 and 159 respectively, hence an
improvement of Design III over Design II and Design I are 39.47% and 109.20% respectively.
The existing Reversible Binary Subtractor based on Reversible gate [5] to implement full Subtraction
requires Quantum Cost of 12, Garbage inputs of one and Garbage outputs of two. The proposed
Reversible eight-bit Parallel Binary Adder/Subtractor Design III is better compared to the existing
design in terms of Quantum Cost, Garbage inputs and Garbage outputs and also in our design the Full
Subtraction and Addition function is implemented together as compared to only Subtractor in the
existing design. Hence we claim that Design III is better in terms of performance compared to the
existing designs.
5.3 Simulation Results
Reversible Half, Full Adder/Subtractor and Reversible eight-bit Parallel Binary Adder/Subtractor with
Design I, Design II and Design III are implemented using VHDL code and Simulated using Modelsim
Simulator. The individual gate functionality is implemented using Behavioral style of Modeling, the
overall logic is implemented using Structural style of Modeling and simulation results are shown in
shown in Figure 18, 19 and 20.
Figure18. Simulation result of Reversible Half Adder/Subtractor
Figure19. Simulation result of Reversible Full Adder/Subtractor
Figure20. Simulation result of Reversible eight-bit Parallel Binary Adder/Subtractor
11. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
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6. Conclusions
The Reversible gates are used to implement Full Adder/Subtractor and Reversible eight-bit Parallel
Binary Adder/Subtractor. In this paper, we proposed Reversible eight-bit Parallel Binary
Adder/Subtractor unit. The Design I, Design II and Design III are used to implement half and full
Adder/Subtractor. The Reversible eight-bit Parallel Binary Adder/Subtractor is built using three
designs. The Design III implementation of Reversible eight-bit Parallel Binary Adder/Subtractor has
better performance as compared to Design I, Design II and existing design in terms of number of
gates used, Garbage inputs/outputs and Quantum Cost, hence can be used for low power applications.
The full Adder/Subtractor is implemented in a single unit in our design as compared to only full
Subtractor in the existing design [5]. In future, the design can be extended to any number of bits for
Parallel Binary Adder/Subtractor unit and also for low power Reversible ALUs, Multipliers and
Dividers.
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Authors Short Biography
H G Rangaraju is a Senior Grade Lecturer in the Department of
Telecommunication Engineering, Bangalore Institute of Technology, Visvesvaraya
Technological University, Belgaum. He obtained his Bachelor degree in Electronics
and Communication Engineering from Siddaganga Institute of Technology,
Bangalore University and Master degree in Electronics and Communication
Engineering from University Visvesvaraya College of Engineering, Bangalore
University. He is pursuing Ph.D. in Electronics and Communication Engineering,
Visvesvaraya Technological University, Belgaum. His research interest includes
VLSI design and Wireless Communication.
U Venugopal obtained his Diploma in Electronics and Communication
Engineering from Karnataka Technical Education Board and AMIE digree from
Institution of Engineering (India), Calcutta. Presently He is studying M. E. in
Electronics and Communication Engineering at University Visveswaraya College
of Engineering, Bangalore University. He is working as Engineer in ISRO Satellite
Center, Bangalore since 1990 and he has contributed to various satellite
programmes of ISRO. He has around three research papers to his credit. His area of
interest is VLSI and EMI/EMC.
K N Muralidhara obtained his BE degree in Electronics and Communication from
University of Mysore in 1981. He completed the ME and Ph.D. degrees in 1990 and
1998 respectively from University of Roorkee, Uttaranchal (now known as Indian
Institute of Technology, Roorkee). At present, he is working as Professor and Head
of the Dept. of Electronics and Communication Engineering, PES College of
Engineering, Mandya, Visvesvaraya Technological University. His research
interests includes in the areas of Electronic Devices, VLSI, Microprocessor and
Microcontroller applications, Embedded systems and Wireless Communication.
K B Raja is an Assistant Professor, Dept. of Electronics and Communication
Engineering, University Visvesvaraya College of Engineering, Bangalore
University, Bangalore. He obtained his BE and ME in Electronics and
Communication Engineering from University Visvesvaraya College of
Engineering, Bangalore. He was awarded Ph.D. in Computer Science and
Engineering from Bangalore University. He has over 45 research publications in
refereed International Journals and Conference Proceedings. His research interests
include Image Processing, Biometrics, VLSI Signal Processing, computer
networks.