A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C.
This document discusses parity generators and checkers, which are used to detect errors in digital data transmission. It explains that a parity generator adds an extra parity bit to binary data to make the total number of 1s either even or odd. This allows a parity checker circuit at the receiver to detect errors if the number of 1s is the wrong parity. It provides truth tables and logic diagrams for 3-bit even and odd parity generators and an even parity checker. The boolean expressions for the parity generator and checker circuits are also derived.
Shift registers are digital circuits composed of flip-flops that can shift data from one stage to the next. They can be configured for serial-in serial-out, serial-in parallel-out, parallel-in serial-out, or parallel-in parallel-out data movement. Common applications include converting between serial and parallel data, temporary data storage, and implementing counters. MSI shift registers like the 74LS164 and 74LS166 provide 8-bit shift register functionality.
PLC Ladder Diagram basics, with two solved examples
For more information go to
http://shrutizpresentations.blogspot.in/2014/04/plc-ladder-diagram-basics.html
The fundamentals and implementation of digital electronics are essential to understanding the design and working of consumer/industrial electronics, communications, computers, security and military equipment. Digital electronics includes many applications in real life. Here are three different and most important application of Digital Electronics.
1. Memory testing is an important part of embedded system development to ensure proper functionality.
2. Basic memory tests include data bus testing, address bus testing, and device testing.
3. Data bus testing uses techniques like walking 1's to write all possible data values and verify each bit. Address bus testing uses power-of-two addresses to isolate each address bit. Device testing writes data to addresses and checks for overwrites to test for overlapping addresses.
This document discusses using a 4:1 multiplexer to create half adder and half subtractor combinational circuits. It defines half adders, half subtractors, and multiplexers. It then shows the logic diagrams and transistor-level implementations of half adders and half subtractors using a 4:1 multiplexer. The document concludes that combinational circuits like these produce outputs only based on present inputs and have no memory elements, resulting in no delay in producing outputs.
A multiplexer has multiple inputs and a single output line, using select lines to determine which input is connected to the output. It is used to increase the amount of data that can be sent over a network. A demultiplexer is the reverse, with one input and multiple output lines, using select lines to send a signal to one of the output lines. Both are used in communication systems, computer memory, and other applications to efficiently transmit data or connect parts of a system.
Group members for the project are Falah Hassan, Maidah Malik, and Maria Khan. The document discusses half adders and full adders. A half adder adds two binary digits and produces a sum and carry output. It is built from two logic gates. A full adder accepts two input bits and a carry input, and produces a sum and carry output. It is implemented using two half adders joined by an OR gate. The main difference between a half adder and full adder is that a full adder has three inputs and two outputs, allowing multiple adders to be chained to add more bits.
This document discusses parity generators and checkers, which are used to detect errors in digital data transmission. It explains that a parity generator adds an extra parity bit to binary data to make the total number of 1s either even or odd. This allows a parity checker circuit at the receiver to detect errors if the number of 1s is the wrong parity. It provides truth tables and logic diagrams for 3-bit even and odd parity generators and an even parity checker. The boolean expressions for the parity generator and checker circuits are also derived.
Shift registers are digital circuits composed of flip-flops that can shift data from one stage to the next. They can be configured for serial-in serial-out, serial-in parallel-out, parallel-in serial-out, or parallel-in parallel-out data movement. Common applications include converting between serial and parallel data, temporary data storage, and implementing counters. MSI shift registers like the 74LS164 and 74LS166 provide 8-bit shift register functionality.
PLC Ladder Diagram basics, with two solved examples
For more information go to
http://shrutizpresentations.blogspot.in/2014/04/plc-ladder-diagram-basics.html
The fundamentals and implementation of digital electronics are essential to understanding the design and working of consumer/industrial electronics, communications, computers, security and military equipment. Digital electronics includes many applications in real life. Here are three different and most important application of Digital Electronics.
1. Memory testing is an important part of embedded system development to ensure proper functionality.
2. Basic memory tests include data bus testing, address bus testing, and device testing.
3. Data bus testing uses techniques like walking 1's to write all possible data values and verify each bit. Address bus testing uses power-of-two addresses to isolate each address bit. Device testing writes data to addresses and checks for overwrites to test for overlapping addresses.
This document discusses using a 4:1 multiplexer to create half adder and half subtractor combinational circuits. It defines half adders, half subtractors, and multiplexers. It then shows the logic diagrams and transistor-level implementations of half adders and half subtractors using a 4:1 multiplexer. The document concludes that combinational circuits like these produce outputs only based on present inputs and have no memory elements, resulting in no delay in producing outputs.
A multiplexer has multiple inputs and a single output line, using select lines to determine which input is connected to the output. It is used to increase the amount of data that can be sent over a network. A demultiplexer is the reverse, with one input and multiple output lines, using select lines to send a signal to one of the output lines. Both are used in communication systems, computer memory, and other applications to efficiently transmit data or connect parts of a system.
Group members for the project are Falah Hassan, Maidah Malik, and Maria Khan. The document discusses half adders and full adders. A half adder adds two binary digits and produces a sum and carry output. It is built from two logic gates. A full adder accepts two input bits and a carry input, and produces a sum and carry output. It is implemented using two half adders joined by an OR gate. The main difference between a half adder and full adder is that a full adder has three inputs and two outputs, allowing multiple adders to be chained to add more bits.
This document discusses interfacing a 7-segment display with an 8051 microcontroller. There are two common types of 7-segment displays - common cathode and common anode. An 8051, 7-segment display, 2-4 decoder, transistors, and power supply are needed. Lookup tables store the segment patterns for digits 0-9 depending on the display type. Assembly code samples show how to display digits on one or four 7-segment displays by selecting the correct display using a 2-4 decoder connected to ports on the 8051.
This document describes a mini project on a clap switch circuit. The circuit uses a microphone to detect the sound of clapping and triggers a transistor circuit to turn a light on or off. It consists of an audio amplifier to amplify the sound signal from the microphone. A flip-flop circuit with two transistors changes state each time a clap is detected to control a heavier transistor that switches the light. The circuit works with a 9V battery and has applications for assisting elderly or disabled individuals to remotely control lights or devices through clapping.
The document describes the instruction set of the 8051 microprocessor. It is divided into 5 groups: arithmetic, logic, data transfer, boolean, and branching instructions. The arithmetic instructions include ADD, ADDC, DA for decimal adjust, and INC/DEC. Logic instructions include ANL, ORL, and SWAP. Data transfer instructions move data between registers and memory. Boolean instructions manipulate individual bits. Branching instructions include conditional jumps, calls, and returns.
Multiplexer and demultiplexer applications.ppsx 3safia safreen
This document discusses multiplexers and demultiplexers. It defines a multiplexer as a device with multiple inputs and a single output that uses select lines to determine which input is connected to the output. Demultiplexers are defined as having a single input and multiple outputs, with the select lines determining which output receives the signal. The document discusses types of multiplexers and demultiplexers and their applications in communication systems, computer memory, telephone networks, and transmitting data from satellites and computers.
The 8051 microcontroller has an 8-bit architecture and uses 8-bit registers. It can process data larger than 8 bits by breaking it down. The DB directive is used to define byte-sized data in various formats. The ORG and EQU directives set the program origin and define constants, while END marks the end of an assembly file. The document also describes accessing individual I/O port bits and toggling or checking their states using instructions like SETB, XLR, JNB, and JB.
This document discusses numerical data representation and digital and analog systems. It notes that there are two types of numerical representation: analog and digital. It also describes two types of systems: analog systems, which use analog representations, and digital systems, which use digital representations. The document outlines several advantages of digital systems, such as being easier to design, having greater accuracy and precision, and being less affected by noise. It also notes a limitation of digital systems is that the real world is analog. To take advantage of digital techniques, analog inputs must be converted to digital forms, operations performed digitally, and digital outputs converted back to analog forms.
This document discusses counters in digital electronics. It begins by introducing counters as sequential circuits that increment their output value by one each clock cycle, wrapping back to 0 after their maximum count. There are two main types of counters: asynchronous and synchronous. Asynchronous counters have their flip-flops clocked one after another by the previous flip-flop's output, causing a ripple effect. Synchronous counters clock all flip-flops simultaneously with a common clock signal. Examples of 4-bit asynchronous and synchronous counters are also provided with their respective timing diagrams.
- Karnaugh maps are used to simplify Boolean algebra expressions by grouping adjacent 1s in a two-dimensional grid.
- Groups must contain powers of 2 cells and cannot include any 0s. They can overlap and wrap around the map.
- The simplified expression is obtained by determining which variables stay the same within each group.
The document discusses the design and analysis of a D-flip flop. It begins by introducing flip flops and their use for storing state information. It then discusses the need for a D-flip flop due to limitations in the basic SR flip flop. A D-flip flop overcomes these limitations using a gated SR flip flop with an inverter between the S and R inputs, allowing a single data input. The circuit and working of the D-flip flop are shown, noting it will store and output the data input while the clock is high.
Boolean algebra and logic circuits were introduced. Boolean algebra uses binary numbers (0,1) and logical operations like AND, OR, and NOT to simplify logic expressions. Basic logic gates like AND, OR, and NOT were explained. Logic circuits can be built using combinations of logic gates to perform complex logical functions. Boolean algebra is used to simplify logic circuits and increase the efficiency of digital devices like computers.
Keypad is a common interface with any microcontroller. This presentation gives details of keypad can be interfaced with 8051. The key pressed may be dispalyed on LCD/7 segment/LED displays.
Multiplexers and demultiplexers allow digital information from multiple sources to be routed through a single line. A multiplexer has multiple data inputs, select lines to choose an input, and a single output. A demultiplexer has a single input, select lines to choose an output, and multiple outputs. Bigger multiplexers and demultiplexers can be built by cascading smaller ones. Multiplexers can implement logic functions by using the select lines as variables and routing the input lines to the output.
Presentation on various logic families like RTL, DTL, TTL, IIL etc with diagram, advantages and limitations plus some basic concepts like fan out, noise margin, propagation delay.
This document discusses computer organization and combinational circuits. It begins by defining logic gates as basic building blocks of digital circuits. The seven basic logic gates - AND, OR, XOR, NOT, NAND, NOR, and XNOR - are described along with their truth tables. Using combinations of these logic gates in arrays allows complex operations to be performed in combinational circuits like adders and subtractors. Half adders, full adders, n-bit parallel adders and subtractors are explained as examples of combinational circuits. Boolean algebra is also discussed as it relates to describing digital logic circuits in terms of true and false values.
This document discusses microprocessors and networking. It provides details on microprocessors such as their components like the ALU, registers and control unit. It describes early microprocessors like the 4004 and 8085. It also discusses microprocessor memory, buses and different types of integrated circuits. The document also defines what a computer network is and the different ways of physically connecting computers through guided media like coaxial cable, twisted pair and fiber optic cable. It explains wireless connections using infrared, radio frequency and microwave communications.
This document describes a lab experiment on logic gates and combinational circuits conducted by students at the University of Botswana. The experiment aimed to help students understand basic logic gate behavior and wiring combinations of gates. Students used common logic gates like AND, OR, NOT, NAND and XOR gates in various circuits. While the experiment aimed to be helpful, students faced issues like outdated equipment, crowded workspaces, and lack of preparation that wasted time troubleshooting instead of conducting the experiment. Recommendations included improving equipment and preparation. Ultimately, the document concludes the students understood gate behavior and combinations through practical observation, which matched theoretical expectations.
This document provides an introduction and overview of flip flops and RS latches. It defines a flip flop as a circuit that has two stable states and can store state information. It describes the main types of flip flops as asynchronous and synchronous, and lists some examples like the RS latch and JK flip flop. It then explains the key differences between asynchronous and synchronous circuits. The document proceeds to describe the RS latch in more detail, including providing its block diagram, logical diagram using NAND gates, truth table, and descriptions of its inputs, outputs, operation, and states.
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C
A New Single-Stage Multilevel Type Full-Bridge Converter Applied to closed lo...IOSR Journals
This document describes a new single-stage multilevel full-bridge converter applied to a closed loop condition with a brushless DC motor load. The converter uses auxiliary windings on the transformer to cancel the DC bus voltage during certain operating modes, allowing the input currents to rise and minimizing harmonics. It operates by switching between four modes to transfer energy from the DC link to the output load and inductors. Simulation results showed the converter can achieve high power factor and continuous output current from maximum to half load.
This document discusses interfacing a 7-segment display with an 8051 microcontroller. There are two common types of 7-segment displays - common cathode and common anode. An 8051, 7-segment display, 2-4 decoder, transistors, and power supply are needed. Lookup tables store the segment patterns for digits 0-9 depending on the display type. Assembly code samples show how to display digits on one or four 7-segment displays by selecting the correct display using a 2-4 decoder connected to ports on the 8051.
This document describes a mini project on a clap switch circuit. The circuit uses a microphone to detect the sound of clapping and triggers a transistor circuit to turn a light on or off. It consists of an audio amplifier to amplify the sound signal from the microphone. A flip-flop circuit with two transistors changes state each time a clap is detected to control a heavier transistor that switches the light. The circuit works with a 9V battery and has applications for assisting elderly or disabled individuals to remotely control lights or devices through clapping.
The document describes the instruction set of the 8051 microprocessor. It is divided into 5 groups: arithmetic, logic, data transfer, boolean, and branching instructions. The arithmetic instructions include ADD, ADDC, DA for decimal adjust, and INC/DEC. Logic instructions include ANL, ORL, and SWAP. Data transfer instructions move data between registers and memory. Boolean instructions manipulate individual bits. Branching instructions include conditional jumps, calls, and returns.
Multiplexer and demultiplexer applications.ppsx 3safia safreen
This document discusses multiplexers and demultiplexers. It defines a multiplexer as a device with multiple inputs and a single output that uses select lines to determine which input is connected to the output. Demultiplexers are defined as having a single input and multiple outputs, with the select lines determining which output receives the signal. The document discusses types of multiplexers and demultiplexers and their applications in communication systems, computer memory, telephone networks, and transmitting data from satellites and computers.
The 8051 microcontroller has an 8-bit architecture and uses 8-bit registers. It can process data larger than 8 bits by breaking it down. The DB directive is used to define byte-sized data in various formats. The ORG and EQU directives set the program origin and define constants, while END marks the end of an assembly file. The document also describes accessing individual I/O port bits and toggling or checking their states using instructions like SETB, XLR, JNB, and JB.
This document discusses numerical data representation and digital and analog systems. It notes that there are two types of numerical representation: analog and digital. It also describes two types of systems: analog systems, which use analog representations, and digital systems, which use digital representations. The document outlines several advantages of digital systems, such as being easier to design, having greater accuracy and precision, and being less affected by noise. It also notes a limitation of digital systems is that the real world is analog. To take advantage of digital techniques, analog inputs must be converted to digital forms, operations performed digitally, and digital outputs converted back to analog forms.
This document discusses counters in digital electronics. It begins by introducing counters as sequential circuits that increment their output value by one each clock cycle, wrapping back to 0 after their maximum count. There are two main types of counters: asynchronous and synchronous. Asynchronous counters have their flip-flops clocked one after another by the previous flip-flop's output, causing a ripple effect. Synchronous counters clock all flip-flops simultaneously with a common clock signal. Examples of 4-bit asynchronous and synchronous counters are also provided with their respective timing diagrams.
- Karnaugh maps are used to simplify Boolean algebra expressions by grouping adjacent 1s in a two-dimensional grid.
- Groups must contain powers of 2 cells and cannot include any 0s. They can overlap and wrap around the map.
- The simplified expression is obtained by determining which variables stay the same within each group.
The document discusses the design and analysis of a D-flip flop. It begins by introducing flip flops and their use for storing state information. It then discusses the need for a D-flip flop due to limitations in the basic SR flip flop. A D-flip flop overcomes these limitations using a gated SR flip flop with an inverter between the S and R inputs, allowing a single data input. The circuit and working of the D-flip flop are shown, noting it will store and output the data input while the clock is high.
Boolean algebra and logic circuits were introduced. Boolean algebra uses binary numbers (0,1) and logical operations like AND, OR, and NOT to simplify logic expressions. Basic logic gates like AND, OR, and NOT were explained. Logic circuits can be built using combinations of logic gates to perform complex logical functions. Boolean algebra is used to simplify logic circuits and increase the efficiency of digital devices like computers.
Keypad is a common interface with any microcontroller. This presentation gives details of keypad can be interfaced with 8051. The key pressed may be dispalyed on LCD/7 segment/LED displays.
Multiplexers and demultiplexers allow digital information from multiple sources to be routed through a single line. A multiplexer has multiple data inputs, select lines to choose an input, and a single output. A demultiplexer has a single input, select lines to choose an output, and multiple outputs. Bigger multiplexers and demultiplexers can be built by cascading smaller ones. Multiplexers can implement logic functions by using the select lines as variables and routing the input lines to the output.
Presentation on various logic families like RTL, DTL, TTL, IIL etc with diagram, advantages and limitations plus some basic concepts like fan out, noise margin, propagation delay.
This document discusses computer organization and combinational circuits. It begins by defining logic gates as basic building blocks of digital circuits. The seven basic logic gates - AND, OR, XOR, NOT, NAND, NOR, and XNOR - are described along with their truth tables. Using combinations of these logic gates in arrays allows complex operations to be performed in combinational circuits like adders and subtractors. Half adders, full adders, n-bit parallel adders and subtractors are explained as examples of combinational circuits. Boolean algebra is also discussed as it relates to describing digital logic circuits in terms of true and false values.
This document discusses microprocessors and networking. It provides details on microprocessors such as their components like the ALU, registers and control unit. It describes early microprocessors like the 4004 and 8085. It also discusses microprocessor memory, buses and different types of integrated circuits. The document also defines what a computer network is and the different ways of physically connecting computers through guided media like coaxial cable, twisted pair and fiber optic cable. It explains wireless connections using infrared, radio frequency and microwave communications.
This document describes a lab experiment on logic gates and combinational circuits conducted by students at the University of Botswana. The experiment aimed to help students understand basic logic gate behavior and wiring combinations of gates. Students used common logic gates like AND, OR, NOT, NAND and XOR gates in various circuits. While the experiment aimed to be helpful, students faced issues like outdated equipment, crowded workspaces, and lack of preparation that wasted time troubleshooting instead of conducting the experiment. Recommendations included improving equipment and preparation. Ultimately, the document concludes the students understood gate behavior and combinations through practical observation, which matched theoretical expectations.
This document provides an introduction and overview of flip flops and RS latches. It defines a flip flop as a circuit that has two stable states and can store state information. It describes the main types of flip flops as asynchronous and synchronous, and lists some examples like the RS latch and JK flip flop. It then explains the key differences between asynchronous and synchronous circuits. The document proceeds to describe the RS latch in more detail, including providing its block diagram, logical diagram using NAND gates, truth table, and descriptions of its inputs, outputs, operation, and states.
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C
A New Single-Stage Multilevel Type Full-Bridge Converter Applied to closed lo...IOSR Journals
This document describes a new single-stage multilevel full-bridge converter applied to a closed loop condition with a brushless DC motor load. The converter uses auxiliary windings on the transformer to cancel the DC bus voltage during certain operating modes, allowing the input currents to rise and minimizing harmonics. It operates by switching between four modes to transfer energy from the DC link to the output load and inductors. Simulation results showed the converter can achieve high power factor and continuous output current from maximum to half load.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
This document describes a hybrid Single Electron Transistor (SET) - Complementary Metal-Oxide-Semiconductor (CMOS) based 4-bit parallel adder/subtractor circuit designed to operate at room temperature with low power consumption. The circuit was simulated using the MIB model for SET operation and BSIM4.6.1 for PMOS operation. Simulation results showed the hybrid circuit provides a noticeable reduction in average power consumption and power-delay product compared to a conventional CMOS-based design. This demonstrates the potential of hybrid SET-CMOS technology for future low-power, high-density integrated circuits.
LOW POWER 16-CHANNEL DATA SELECTOR FOR BIO-MEDICAL APPLICATIONSVLSICS Design
This document describes the design of a low power 16-channel data selector for bio-medical applications like electrocardiograms. The design uses a dynamic threshold MOS (DTMOS) switch logic with an on resistance of 36 ohms, switching speed of 10MHz, and power dissipation of 0.04uW. It can operate over a voltage range of 0.2V with input signals from 1uV to 0.2V. Process, voltage, and temperature corner analysis was performed to characterize the selector's performance over varying conditions. The 16-channel design incorporates a 4-to-16 decoder to select one of 16 analog inputs to pass to the output based on the selection lines.
Low power 16 channel data selector for bio-medical applications VLSICS Design
This document describes the design of a low power 16-channel data selector for bio-medical applications like electrocardiograms. The design uses a dynamic threshold MOS (DTMOS) switch logic with an on resistance of 36 ohms, switching speed of 10MHz, and power dissipation of 0.04uW. It can operate over a voltage range of 0.2V with input signals from 1uV to 0.2V. Process, voltage, and temperature corner analysis was performed to characterize the selector's performance over varying conditions. The 16-channel design incorporates a 4-to-16 decoder to select one of 16 analog inputs to pass to the output based on the selection lines.
Design & implementation of 3 bit flash adc in 0.18µm cmosIAEME Publication
This document describes the design and implementation of a 3-bit flash analog-to-digital converter (ADC) using a 0.18um CMOS technology. It includes 7 comparators and a thermometer-to-binary encoder. The ADC architecture consists of a resistive ladder, comparators that compare the input voltage to reference voltages from the ladder, and an encoder that converts the thermometer code from the comparators to a binary code. Simulation results show the ADC operates up to 4GHz and correctly converts the input signal to a 3-bit digital output. A layout is designed with common centroid layout for the comparators to reduce fabrication errors.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This document presents the design and implementation of a full adder cell using a high-performance CMOS technology to improve speed and reduce power consumption. It begins with an introduction to CMOS technology and enhancements. It then discusses the design and architecture of a traditional full adder before proposing a new design using CMOS transistors. Simulation results show the proposed design has lower power consumption of around 100 microwatts, a 35% reduction compared to the existing design. The document concludes that reducing supply voltage is an effective way to lower power dissipation for low-performance applications like sensor networks.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
This document presents a new mathematical model for analyzing a three-phase controlled rectifier using switching functions. The model derives closed-form analytical equations to compute the rectifier's steady-state performance. It is based on deriving appropriate switching functions using General Switching Matrix Circuit techniques. Once the switching functions are obtained, the output current, input current, and output DC voltage can be easily derived. The model accurately accounts for overlap effects and can derive the input voltage and current distortions as well as output voltage distortion. The model provides designers with key performance metrics like voltage and current values without simulations.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
Mathematical Modelling of Semiconductor Devices and Circuits: A Review
Sanjay Kumar Roy, Manwinder Singh, Kamal Kumar Sharma
and Brahmadeo Prasad Singh
Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This document summarizes a research paper that presents a codec scheme to optimize power in VLSI interconnects using bus encoding. The scheme detects different types of crosstalk couplings between wires and encodes the data to reduce switching activity. It was implemented using Cadence tools in 0.18um technology. Simulation results found a maximum power of 6.44uW for an input combination, showing a 38.89% power reduction over previous work. The scheme models the full custom design approach instead of semi-custom.
A LOW VOLTAGE DYNAMIC SYNCHRONOUS DC-DC BUCK-BOOST CONVERTER FOUR SWITCHES P singh
This paper presents the design and modeling of synchronous DC-DC buck-boost converter four switches controlled with PID controller for mobiles devices applications. The design of the converter circuit needs modeling and simulating its mathematical equations using MATLAB/SIMULINK. The evaluation of the output performance has been based on dynamic respond in term of rise time, settling time and peak time. Also the goal of the designer is regulated the output voltage to 3.24 regardless the variation of the input voltage, with input voltage [2.5V-5V] and switching frequency is 50 MHz. The converter is operated in Buck (step-down) and Boost (step-up) modes.
A new precision peak detector full wave rectifierVishal kakade
This document summarizes a research paper that proposes a new precision peak detector/full-wave rectifier circuit based on dual-output current conveyors. The key points are:
1) The proposed circuit uses MOS transistors, a phase shifter, and dual-output current conveyors to generate a DC output voltage equal to the peak amplitude of the input sinusoidal signal over a wide frequency range.
2) An all-pass filter is used to shift the phase of the input signal by 90 degrees. This allows the circuit to fully rectify both halves of the sinusoidal wave.
3) Simulation results show the circuit has very low ripple voltage and harmonic distortion compared to existing techniques, making it
A Single-Phase Clock Multiband Low-Power Flexible Dividerijsrd.com
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented.
This document describes a hybrid full adder design using both CMOS and transmission gate technologies that achieves low power and high speed. The design is divided into modules: 1) an XOR-XNOR module using weak inverters to reduce power, 2) a sum generation module using transmission gates, and 3) a carry generation module using strong transmission gates to reduce delay. Simulation results show the hybrid full adder achieves a power dissipation of 2.94μW and delay of 61.4ps at 1.8V in a 180nm technology, with lower power at lower voltages. This design coupled weak inverters with strong transmission gates to achieve both low power and high speed.
M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.Suchitra goudar
The document proposes designs for ternary logic gates based on single power supply voltage for CMOS technology. It describes the design of a simple ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI) using only enhancement-type MOSFETs. Transistor widths and lengths are optimized to achieve the desired voltage transfer characteristics. Basic ternary logic gates including a ternary NAND (TNAND) and ternary NOR (TNOR) are also designed using a similar single-transistor approach. The proposed gate designs aim to reduce transistor count and power consumption compared to prior ternary logic designs.
Power System Simulation Laboratory Manual Santhosh Kumar
This document outlines experiments related to power system simulation laboratory. It includes 10 experiments covering topics like computation of transmission line parameters, modeling of transmission lines, formation of bus admittance and impedance matrices, load flow analysis using different methods, fault analysis, stability analysis of single machine and multimachine systems, electromagnetic transients, load-frequency dynamics, and economic dispatch. The document provides theoretical background and procedures for conducting each experiment using MATLAB software. Sample problems are also included for some experiments to demonstrate the modeling and simulation of different power system components and analysis.
Design of up converter at 2.4GHz using Analog VLSI with 22nm Technologyijsrd.com
This document describes the design of an up converter at 2.4GHz using Analog VLSI with 22nm technology. It summarizes the design of a previous up converter at 2.4GHz using 0.18um technology. It then discusses the simulation of a Gilbert mixer up converter with different input frequencies and local oscillator signals. Parameters like width to length ratio, input common mode range, noise margin, and power dissipation are also calculated and analyzed. The goal is to design the up converter with low power dissipation using the recent 22nm technology.
Digital Twins Computer Networking Paper Presentation.pptxaryanpankaj78
A Digital Twin in computer networking is a virtual representation of a physical network, used to simulate, analyze, and optimize network performance and reliability. It leverages real-time data to enhance network management, predict issues, and improve decision-making processes.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
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A report on 2 to 1 mux using tg
1. 1
ELECTRONICS CIRCUIT LAB (EEC 752)
REPORT
ON
REALIZATION OF 2:1 MUX USING TG
Submitted for the partial fulfillment of award of the degree of
Bachelor of Technology
Of
Electronics and Communication Engineering
Submitted By
SUMIT KUMAR
1219231105
4th
year ECE, Section B
Under the Guidance of
MR. DHARMENDRA NISHAD
(Asst. Professor)
Deptt. Of ECE
Deptt. Of Electronics and Communication Engineering
G.L. BAJAJ INSTITUTE OF TECHNOLOGY AND MANAGEMENT
Plot No. 2, Knowledge Park III, Gr. Noida
Session: 2015-16
2. 2
Deptt.of Electronics and Communication Engineering
G. L. BAJAJ INSTITUTE OF TECHNOLOGY AND MANAGEMENT
[Approved by AICTE, Govt. of India & Affiliated to U.P.T.U, Lucknow]
CERTIFICATE
Certified that SUMIT KUMAR have carried out the lab project work presented
in this report entitled “REALIZATION OF 2:1 MUX USING TG” for the
award of Bachelor of Technology in Electronics and Communication
Engineering during the academic session 2015-16 from Uttar Pradesh
Technical University, Lucknow. The project embodies result of the work and
studies carried out by Student himself and the contents of the report do not form
the basis for the award of any other degree to the candidate or to anybody else.
(Mr. Dharmender Nishad) (Mr. DHARMENDRA NISHAD)
(Lab Co-ordinator) (Lab Co-ordinator)
(Asst. Professor) (Asst.Professor)
Deptt.of ECE Deptt.of ECE
H. O. D., Deptt.of ECE
Date:
3. 3
ACKNOWLEDGEMENT
I heartily express my gratitude to those who generously helped me in preparing
my report on REALIZATION OF 2:1 MUX USING TG of their knowledge
and experiences.
I would like to thank and pay my obligation to DR. AMIT SEHEGAL, HOD,
ECE DEPTT. I would also like to acknowledge with much appreciation the
crucial role of MR. DHARMENDRA NISHAD (ECE DEPTT.) for her able
guidance, invaluable suggestions, keen interest and her considerable attitude.
I pay special thanks to all my honorable teachers, my parents along with my
classmates who directly or indirectly helped me to accomplish my work.
SUMIT KUMAR
Roll No.: 1219231105
4th year ECE, Section B
4. 4
TABLE OF CONTENTS
CHAPTER NO. TITLE PAGE NO.
TITLE PAGE AND COVER PAGE i
CERTIFICATE ii
ACKNOWLEDGEMENT iii
TABLE OF CONTENTS iv
LIST OF FIGURES v
ABSTRACT 1
1. INTRODUCTION 3
1.1 Y-CHART 6
2. BEHAVIOUR 7
3. STRUCTURE 9
4. SIMULATION 12
4.1 INTRODUCTION TO PSpice 12
4.2 TYPES OF ANALYSIS 14
4.3 LIMITATION 16
4.4 SIMULATION OF TRANSMISSION GATE 17
4.5 SIMULATION OF CMOS INVERTER 18
4.6 SIMULATION OF 2:1 MUX 20
5. CONCLUSION 23
REFERENCES 27
5. 5
LIST OF FIGURES
FIGURE NO. TITLE PAGE NO.
1.2:1 MUX ……………………………………………………………01
2. 2:1 MUX TRUTH TABLE….….…………………………………..01
3. 4:1 MUX AND 8:1 MUX..………………………………………....04
4. BASIC DESIGN STEPS IN VLSI ………………………………...05
5. Y-CHART…………………...…………………..………................06
6. 8:1 MUX…………………………………………………………....07
7. TRUTH TABLE OF 8:1 MUX………..……………………..…......08
8. IMPLEMENTATION OF 8:1 MUX USING 2:1 MUX..........…......09
9. IMPLEMANTATION OF 2:1 MUX USING TG ……………........09
10. TRANSMISSION GATE SYMBOL……………………..............10
11. LAYOUT OF TRANSMISSION GATE….....................................10
12. INVERTER……………………………………………..…..........11
13. ORCAD CAPTURE LITE EDITION……………………………15
14. SIMULATION CIRCUIT OF TG ON PSpice…………………...16
15. SIMULATION OUTPUT OF TG ON PSpice…………………...17
16. CIRCUIT OF INVERTER…………………………………….....17
17. SIMULATION CIRCUIT OF INVERTER ON PSpice…………18
18. SIMULATION OUTPUT OF INVERTER ON PSpice…………18
19. Circuit and Truth Table of 2:1 MUX……………………………..19
20. SIMULATION CIRCUIT OF 2:1 MUX ON PSpice………….....20
21. SIMULATION OUTPUT OF 2:1 MUX USING STEP INPUT…21
22. SIMULATION OUTPUT OF 2:1 MUX USING sine INPUT…...21
6. 6
ABSTRACT
The metal–oxide–semiconductor field-effect transistor (MOSFET) is a type of
transistor used for amplifying or switching electronic signals. The main
advantage of a MOSFET over a regular transistor is that it requires very little
current to turn on (less than 1mA), while delivering a much higher current to a
load (10 to 50A or more). Transistors are used as switches to pass logic levels
between nodes of a circuit, instead of as switches connected directly to supply
voltages. This reduces the number of active devices, but has the disadvantage
that the difference of the voltage between high and low logic levels decreases at
each stage. Each transistor in series is less saturated at its output than at its
input. If several devices are chained in series in a logic path, a conventionally
constructed gate may be required to restore the signal voltage to the full value.
By contrast, conventional CMOS logic switches transistors so the output
connects to one of the power supply rails, so logic voltage levels in a sequential
chain do not decrease.
A transmission gate is similar to a relay that can conduct in both directions or
block by a control signal with almost any voltage potential. CMOS transmission
gate consists of one nMOS and one pMOS transistor, connected in parallel. The
gate voltages applied to these two transistors are also set to be complementary
signals. As such, the CMOS TG operates as a bidirectional switch between the
nodes A and B which is controlled by signal C. If the control signal C is logic-
high, i.e., equal to VDD, then both transistors are turned on and provide a low-
resistance current path between the nodes A and B. If, on the other hand, the
control signal C is low, then both transistors will be off, and the path between
the nodes A and B will be an open circuit. This condition is also called the high-
impedance state.
7. 7
Pass transistor logic often uses fewer transistors, runs faster, and requires less
power than the same function implemented with the same transistors in fully
complementary CMOS logic. The designers of the Z80 and many other chips
save a few transistors by implementing the XOR using pass-transistor logic
rather than simple gates.
Transmission Gate Applications are Mux XOR D Latch D Flip Flop.
MULTIPLEXER CIRCUIT is a circuit that generates an output that exactly
reflects state of one of a number of data inputs, based on value of one or more
control inputs is called “multiplexer”. A multiplexer with two data inputs is
referred as “2-to-1 or 2:1” multiplexer. A multiplexer of 2n inputs has n select
lines, which are used to select which input line to send to the output.
Multiplexers are mainly used to increase the amount of data that can be sent
over the network within a certain amount of time and bandwidth. A multiplexer
is also called a data selector. An electronic multiplexer makes it possible for
several signals to share one device or resource, for example one A/D converter
or one communication line, instead of having one device per input signal.
8. 8
CHAPTER 1
INTRODUCTION
In principle, a transmission gate made up of two field effect transistors, in
which - in contrast to traditional discrete field effect transistors - the substrate
terminal (Bulk) is not connected internally to the source terminal. The two
transistors, an n-channel MOSFET and a p-channel MOSFET are connected in
parallel with this, however, only the drain and source terminals of the two
transistors are connected together. Their gate terminals are connected to each
other via a NOT gate (inverter), to form the control terminal.
Two variants of the "bow tie" symbol commonly used to represent a
transmission gate in circuit diagrams.
As with discrete transistors, the substrate terminal is connected to the source
connection, so there is a transistor to the parallel diode (body diode), whereby
the transistor passes backwards. However, since a transmission gate must block
flow in either direction, the substrate terminals are connected to the respective
supply voltage potential in order to ensure that the substrate diode is always
operated in the reverse direction. The substrate terminal of the p-channel
MOSFET is thus connected to the positive supply voltage potential and the
substrate terminal of the n-channel MOSFET connected to the negative supply
voltage potential.
In digital circuit design, the selector wires are of digital value. In the case of a
2-to-1 multiplexer, a logic value of 0 would connect 𝑖0 to the output while a
logic value of 1 would connect 𝑖1 to the output. In larger multiplexers, the
number of selector pins is equal to log2(𝑛) where n is the number of inputs. For
example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to
9. 9
32 inputs would require no fewer than 5 selector pins. The binary value
expressed on these selector pins determines the selected input pin.
A 2-to-1 multiplexer has a Boolean equation where 𝐴 and 𝐵 are two inputs 𝑠 is
the selector input and 𝑧 is output.
𝑧 = (𝐴. 𝑆′
) + (𝐵. 𝑆)
Fig.1 2:1 MUX Fig.2 2:1 MUX TRUTH TABLE
A multiplexer is a combinational circuit that selects binary information from
one of the many input lines and directs it to a single output line. Therefore,
apart from the input lines and the output line, selection lines are used that
selects a particular input line. The multiplexer is basically a data selector
analogous to an electronic switch that selects one of the multiple sources.
Fig.3 4:1 and 8:1 MUX
10. 10
Here, 4:1 and 8:1 MUX have been shown, in 4:1 MUX there are 2 select lines
and 8:1 MUX have 3 select lines i.e. MUX have log2(𝑛) select lines where n
are the input lines present in MUX.
Designing of any Electronic Circuit goes through following steps:
Fig.4 BASIC DESIGN STEPS IN VLSI
This is the top down approach in which problem is divided from sub steps
simplifying the problem with each step and with each step more and more
information revealed by the method about the problem. Above is the Design
Flow diagram help in designing the Digital circuits. A good representation of
Design flow can be achieved through Y-Chart also:
11. 11
1.1 Y- CHART:
Fig.5 Y-CHART
Designing of 8:1 MUX can be approached through:
Now we will describe the Designing methods step by step:
12. 12
CHAPTER 2
BEHAVIOR
8:1 multiplexer is a combination circuit which can be describe in digital form
using Boolean expression and Truth Table.
Fig.6 8:1 MUX
Here, 𝐼0, 𝐼1, 𝐼2, 𝐼3, 𝐼4, 𝐼5, 𝐼6, 𝐼7 are inputs to the MUX and 𝑠0, 𝑠1, 𝑠2 are the 3 select
lines of the MUX and 𝑂𝑢𝑡 is the output of the MUX.
8:1 multiplexer is a combination circuit which can be describe in digital form
using Boolean expression and Truth Table.
𝑂𝑢𝑡 = 𝑠2
′
𝑠1
′
𝑠0
′
𝐼0 + 𝑠2
′
𝑠1
′
𝑠0 𝐼1 + 𝑠2
′
𝑠1 𝑠0
′
𝐼2 + 𝑠2
′
𝑠1 𝑠0 𝐼3 + 𝑠2 𝑠1
′
𝑠0
′
𝐼4
+ 𝑠2 𝑠1
′
𝑠0 𝐼5 + 𝑠2 𝑠1 𝑠0
′
𝐼6 + 𝑠2 𝑠1 𝑠0 𝐼7
𝐼0 𝐼1 𝐼2 𝐼3 𝐼4 𝐼5 𝐼6 𝐼7 𝑠0 𝑠1 𝑠0 𝑂𝑢𝑡
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0 𝐼0
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 1 𝐼1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1 0 𝐼2
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1 1 𝐼3
14. 14
CHAPTER 3
STRUCTURE
Structure level is the most important level in designing of the Digital circuit, it
is recommended to design as much possible at this level, helps in subsequent
designing of levels.
8:1 multiplexer can be implemented using 2:1 MUX.
Fig.8 IMPLEMENTATION OF 8:1 USING 2:1
2:1 Mux can be implemented using Transmission Gate and a inverter logic:
Fig.9 IMPLEMANTATION OF 2:1 MUX USING TRANSMISSION GATE
15. 15
Transmission Gate and Inverter can be implemented through Transistor:
Fig.10 TRANSMISSION GATE
Fig.11 LAYOUT OF TRANSMISSION GATE
16. 16
This is the CMOS Transmission gate having A as input and B as output using
two MOSFET and act as a switch controlled by C signal.
Fig12. INVERTER
This is the Inverter Logic which inverts the input signal. This is also a CMOS
circuit.
17. 17
CHAPTER 4
SIMULATION
Simulation can be done using the PSpice OrCAD capture Software suit. We
will simulate the each step of the MUX i.e. first we simulate transmission gate
then inverter then 2:1 Mux using transmission gate and at last we will simulate
the 8:1 MUX using transmission gate.
For simulation, in simulation setting we used time domain (Transient) as
analysis type
4.1 INTRODUCTION TO PSPICE
SPICE (Simulated Program with Integrated Circuit Emphasis) is a general
purpose software that simulates different circuits and can perform various
analysis of electrical and electronic circuits including time domain response,
small signal frequency response, total power dissipation, determination of nodal
voltages and branch current in a circuit, transient analysis, determination of
operating point of transistors, determinations of transfer functions etc. This
software is designed in such a way so that it can simulate different circuit
operations involving transistors, operational amplifiers (op – amp) etc. and
contains models for circuit elements (passive as well as active).
SPICE was first developed in the University of California, Berkeley, USA in
the early 1970s. Subsequently an improved version SPICE 2 was available in
the mid1970s especially to support computer aided designs. In due course of
time this program (SPICE 2 has become so versatile in the industry that people
used to call, this program itself as SPICE. PSpice is also the member of SPICE
family and it is a commercial software product based on SPICE algorithm. It is
useful for simulating all types of circuits in a variety of applications. In both
18. 18
SPICE and PSpice, the circuit is described by statements those are stored in a
file (namely Circuit File).
The SPICE simulator is assigned to read this file to run the simulation. In
PSpice, the statements are self – contained and independent; obviously they do
not interact with each other. The statements are also easy to learn and use.
PSpice includes additional features that make the program more flexible and
user friendly. Notably among other features is the graphics postprocessorprobe
which acts like a software oscilloscope and is capable of exhibiting various
waveforms. PSpice has become one of the most popular circuit simulation
programs. In order to draw the circuit and create a schematic file, schematic
editor can be used in the PSpice simulation.
PSpice is a part of larger software package called the Design Lab, originally
developed by MicroSim Corporation as the Design Centre. It is now marketed
by OrCAD.
PSpice was the first version of UC Berkeley SPICE available on a PC, having
been released in January 1984 to run on the original IBM PC. This initial
version ran from two 360 KB floppy disks and later included a waveform
viewer and analyser program called Probe. Subsequent versions improved on
performance and moved to DEC/VAX minicomputers, Sun workstations, Apple
Macintosh, and Microsoft Windows.
Version 3.06 was released in 1988, also came on two 5.25 floppy discs, and had
a "Student Version" available which would allow a maximum of up to ten
transistors to be inserted.
4.2 TYPES OF ANALYSIS
The type of simulation performed by PSpice depends on the source
specifications and control statements. The analyses usually executed in PSpice
are listed below.
DC Analysis
19. 19
It is used for circuits with time–invariant sources (e.g. steady-state dc sources).
It calculates all nodal voltages and branch currents over a range of values. The
types of dc sweep analyses and their corresponding. (Dot) commands are
described below:
• Linear sweep: .DC [LIN] <sweep variable name> <start value> <end
value> <increment value>
• Logarithmic sweep: .DC <DEC|OCT> <sweep variable name> <start
value> <end value> <points value>
• Sweep over List of values: .DC <sweep variable name> LIST <value>*
All these sweep types can also be nested by adding another set of parameter
name and values at the end.
Transient Analysis
It is used for circuits with time variant sources (e.g., sinusoidal
sources/switched dc sources). It calculates all nodes voltages and branch
currents over a time interval and their instantaneous values are the outputs. The
corresponding. (Dot) command is as follows:
.TRAN <print step value> <final time value> [no-print value [step ceiling
value]] [SKIPBP]
AC Analysis
It is used for small signal analysis of circuits with sources of varying
frequencies. It calculates the magnitudes and phase angles of all nodal voltages
and branch currents over a range of frequencies. The corresponding. (dot)
command is as follows: .
AC <LIN|DEC|OCT> <Number of points> <Start frequency value> <End
frequency value>
20. 20
Fig13. ORCAD CAPTURE LITE EDITION
4.3 LIMITATIONS
PSpice has the following limitations:
• The student (free) version of PSpice is restricted to analyses circuits up to
10 transistors only.
• PSpice does not support an iterative method of solution.
• The circuit cannot be analyzed for various component values without
editing program statements. Hence, the program is not interactive.
• The input impedance cannot be determined directly without running the
graphic post processor, Probe.
• The output impedance of a circuit cannot be printed or plotted directly.
• Distortion analysis is not possible.
21. 21
To realize the circuit we can approach to two methods one is making library file
of transmission gate and inverter second by simply adjoining transistor as per
the circuit diagram.
4.4 SIMULATION OF TRANSMISSION GATE-:
We can simulate the circuit of transmission gate by having the circuit:
Fig14. SIMULATION CIRCUIT OF TG ON PSpice
Here, we have connected nMOS and pMOS parallel to each other control signal
is applied to the gate of MOS. Input is at Drain and Source is our output.
Whenever the control signal is at low the output will be high and whenever
control signal is high the output will be low, acting as a switch.
Simulation output is shown here:
22. 22
Fig15. SIMULATION OUTPUT OF TG ON PSpice
Red line is showing the Control signal and Green line is output. Here, +5 is high
and 0 is low.
4.5 SIMULATION OF CMOS INVERTER:
CMOS Inverter can be simulating by connecting two transistors in series, pair
of switches are operated in a complementary fashion by the input voltage.
Fig16. CIRCUIT OF INVERTER
This circuit converts the high level logic of input into low level of output and
low level input to high level output.
23. 23
Fig17. SIMULATION CIRCUIT DIAGRAM OF INVERTER ON PSpice
Fig18. SIMULATION CIRCUIT DIAGRAM OF INVERTER ON PSpice
24. 24
4.6 SIMULATION OF 2:1 MUX:
Simulation of 2:1 can be simulating in PSpice using inverter and transmission
gate. We require two transmission gate and one inverter circuit. The structural
level of circuit can be representing like:
Fig.19 Circuit and Truth Table of 2:1 MUX
25. 25
PSpice circuit model can be shown like:
Fig20. SIMULATION CIRCUIT OF 2:1 MUX ON PSpice
Input and select line for the 2:1 MUX input is:
Fig21. SIMULATION OUTPUT OF 2:1 MUX ON PSpice USING STEP INPUT
26. 26
Output for the sine wave input:
Fig22.SIMULATION OUTPUT OF 2:1 MUX ON PSpice USING sine wave INPUT
27. 27
CHAPTER 5
CONCLUSION
In this paper, different multiplexers have been implemented, simulated,
analyzed and compared. Using driving capability technique this problem can be
minimized. The conventional CMOS style based designs have great output
voltage level and less noise margin. Though they suffer higher delay and
consume large area these designs can be considered for accurate and reliable
output. Transmission gate based designs consumes high power. But the main
drawback is that there is no selection pin, so these designs are not appropriate
for multiplexing where both the inputs may have identical value at any instant.
This study was made possible with the help of the Simulation and VLSI LAB.