The document discusses combinational logic circuits including decoders, encoders, multiplexers and demultiplexers. It explains that decoders convert coded inputs to coded outputs, with only one output active at a time. Examples of 2-to-4 and 3-to-8 decoders are provided along with their truth tables and logic diagrams. Encoders perform the reverse function of decoders. Multiplexers allow selecting one of several data inputs to output, while demultiplexers distribute a single input to multiple outputs. Applications in designing logic functions using decoders and multiplexers are also covered.

1. ENG 202 – Digital
Electronics 1
CHAPTER 4 – Combinational Logic Circuit

2. 2
Course Learning Outcomes, CLO
CLO 4:
explain correctly the application of
data processing circuits in digital
systems.

3. SUMMARY
School of Electrical Engineering 3
DATA PROCESSING CIRCUITS
Encoder,
Decoder,
 BCD to Seven Segment Display
 Decoder,
Multiplexer
 Demultiplexer.

4. Decoder
• Decoder: a multiple input, multiple output logic circuit which converts
coded input into coded output from n input line to a maximum of 2n
unique output lines.
• activates an output that corresponds to a binary number on the input.
• Only one output is active for any given input
4

5. Decoder
• The basic function is to detect the presence of a specified
combination of bits (code) on its inputs and to indicate the
presence of that code by a specified output level
• In other word, decoder circuit look at its inputs, determine
which binary number present there, and activates the
output that correspond to that numbers; all other outputs
remain inactive
• Some decoder do not utilize the 2n possible input codes for
example BCD to decimal decoder and Seven segment
decoder
5

6. 2-to-4 Decoder (Active HIGH)
6
2-to-4
Decoder
A
B
O0
O1
O2
O3
b) Truth table
a) Logic symbol
O0 = A’B’
O1 = A’B
O2 = AB’
O3 = AB
c) Boolean expression
O0
O1
O2
O3
A B
d) Logic diagram
@

7. 2-to-4 Decoder (Active LOW)
2 to 4
Decoder
21
20
O0
O1
O2
O3
A
B
2 to 4
Decoder
21
20
O0
O1
O2
O3
A
B
O0
O1
O2
O3
A B
O0
O1
O2
O3
A B
7
a) Logic symbol
@
b) Truth table c) Boolean expression
AB
O
B
A
O
B
A
O
B
A
O




3
2
1
0
d) Logic diagram

8. 2-to-4 Decoder with active LOW enable input
8
AB
en
D
B
A
en
D
B
A
en
D
B
A
en
D




3
1
2
0
,
,
a) Logic symbol b) Truth table
c) Boolean expression
d) Logic diagram
Enable input used to control the
operation of the decoderActive
mode is ‘0’- active low

9. The 74x139 Dual 2-to-4 Decoder
9
a) Logic symbol
b) Logic diagram
1 1 1 1
1 1 1 0
1 1 0 1
1 0 1 1
0 1 1 1
1 X X
0 0 0
0 0 1
0 1 0
0 1 1
Y3 Y2 Y1 Y0
G B A
Outputs
Inputs
Truth table for one-half of a
74x139 dual 2-to-4 decoder

10. 10
3 to 8 Binary Decoder (active HIGH)
3-to-8
Decoder
X
Y
F0
F1
F2
F3
F4
F5
F6
F7
Z
a) Logic symbol
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
F1 = x'y'z
x z
y
F0 = x'y'z'
F2 = x'yz'
F3 = x'yz
F5 = xy'z
F4 = xy'z'
F6 = xyz'
F7 = xyz
b) Truth table
c) Logic diagram & Boolean Expression

11. 11
The 74x138 3-to-8 Decoder
a) Logic symbol
(b) Logic diagram.

12. 12
The 74x138 3-to-8 Decoder
(b) Block Diagram
(c) Function table

13. 13
 The equation for the output signal Y5:
Active-low
 It has three enable inputs, G1, G2A, G2B , all of which
must be asserted for the selected output to be asserted.
The 74x138 3-to-8 Decoder
A
B
C
B
G
A
G
G
Y 2
2
1
5 

14. Exercise
• Design a decoder listing below
a) BCD to decimal decoder
b) 4 to 16 decoder
14

15. Seven Segment Display
• Used for displaying information in a form that can be
understood by user or operator.
• Information can be in alphanumeric (numbers and
letters).
• Seven segment configuration which its arrangement
uses LED for each segment.
• two ways of arrangement – common anode and
common cathode.
• Each arrangement needs different driver/ decoder to
drive each segment of seven segment display.
15

16. 16
BCD-to-7 Segment Decoder / Driver

17. A B C D a b c d e f g
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
17
FILL IN THE TRUTH FOR ACTIVE LOW BCD TO 7 SEGMENT DECODER

18. • Any combinational circuit with n inputs and m outputs can
be implemented with an n-to-2n decoder (active HIGH)
with m OR gates to generate a minterms
OR gate forms the sum
The output lines of the decoder corresponding to the
minterms of the function are used as inputs to the or
gate
• Suitable when a circuit has many outputs, and each
output function is expressed with few minterms.
• It can also use AND gates and n-to-2n decoder to generate
a Maxterm function.
18
Decoder applications

19. • Example: Full adder
• S(x, y, z) = S (1,2,4,7)
• C(x, y, z) = S (3,5,6,7)
19
Decoder applications (full adder)
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
3-to-8
Decoder
S2
S1
S0
x
y
z
0
1
2
3
4
5
6
7
S
C
a) Truth table b) Minterm Expression

20. 20
Decoder applications example
f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7)
(a) Using output or-gates. (b) Using output nor-gates.

21. 21
f1(x2,x1,x0) = Sm(0,2,6,7) and f2(x2,x1,x0) = Sm(3,5,6,7)
(a) Using output and-gates. (b) Using output nand-gates.
Application Example
Decoder applications example

22. • An encoder is a combinational logic circuit that essentially
performs a ‘reverse’ of decoder function
• Number of input lines is larger than output lines
• Decoder VS Encoder
22
Encoder
Decoder Encoder

23. • Only one of input lines is activated at a given time and
produces an N-bit output code depending on which input is
active.
• For example octal to binary encoder: if input 4 is active, the
output code should be 100 with 1 is MSB bit.
23
Encoder

24. I0
I3
I2
I1
I5
I4
I7
I6
22
21
20
24
Octal to Binary Encoder
Inputs Outputs
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
b) Truth table
a) Logic Symbol

25. 25
Octal to Binary Encoder
I0
I1
I2
I3
I4
I5
I6
I7
y0 = I1 + I3 + I5 + I7
y1 = I2 + I3 + I6 + I7
y2 = I4 + I5 + I6 + I7
c) Boolean Expression
d) Logic diagram

26. Decimal to BCD Priority Encoder
26
The priority function means that the encoder will produce
a BCD output corresponding to the highest-order decimal
digit input that is active and will ignore any other actives
input

27. Multiplexer
• A multiplexer is a device that allows digitals information
from several sources to be routed onto a single line for
transmission over that line to a common destination
• The basic multiplexer has several data-input line and a single
output line
• has data select inputs, which permit digital data on any one
of the inputs to be switched to the output line
• also known as data selector
27

28. Multiplexer
28

29. 2 - to - 1 Multiplexer
2 input
Mux
I0
I1
z
s
29
b) Truth Table
c) Boolean Expression
d) Logic Circuit
a) Logic Symbol

30. 4 - to - 1 Multiplexer
4 input
Mux
z
S1
I0
I3
I2
I1
S0
30
c) Boolean Expression
b) Truth Table
a) Logic Symbol d) Logic diagram
3
0
1
2
0
1
1
0
1
0
0
1 I
S
S
I
S
S
I
S
S
I
S
S
z 




31. The 74ALS151 8 inputs Multiplexer
31

32. 32
Multiplexer Application

33. Logic design using Mux
• Case1- number of input is equal to
number of select lines
• Design procedure
• Connect inputs to selected
lines
• Identify the decimal number
corresponding to each
minterm in the expression
• Connect logic 1 level to input
lines corresponding to these
numbers
• Connect logic 0 level to the
others
33
f(x,y,z) = Sm(0,2,3,5)
Example - 3 variable function using 8-to1 line Multiplexer

34. 34
Logic design using Mux
 Case 2: Number of inputs is
higher than number of select
lines
 Design procedure
Reduce the number of inputs to
the number of select lines by
inspection
k-map

35. xy
z
00
1
0
10
11
01
1
0
1
0
0
0
0
1
I0
I2
I3
I1
S1S0
35
Logic design using Mux
Example – implement f(x,y,z) = Sm(0,2,3,5) using 4
input mux
0
2
3
1
0




I
z
I
I
z
I
a) k-map b) Boolean Exp c) implementation

36. 36
Logic design using Mux
(Exercise)
Realize the f(a,b,c,d) =
Sm(0,2,3,5,8,9,11,12,14,15)
Using
a)8 input Mux
b)4 input Mux

37. 37
Demultiplexer (Demux)
 Basically reverses the multiplexing function
 Takes data from one line and distributes them
to a given numbers of output lines.
 Demultiplexer also known as a data distributor.
 Decoders can also be used as a
demultiplexers.

38. 38
Figure (a) shows a 1-line-to-4-line demultiplexer circuit.
The data input lines goes to all of the AND gates. The
two data lines only one gate at a time, and the data
appearing on the data-input line will pass through the
selected gated to the associated data output line.
Figure (a): 1-line-to-4-line demultiplexer

39. 39
Example:
The serial data input waveform (data in) and data selectors input (s0 and s1) are shown
in figure (b). Determine the data output waveforms on D0 through D3 for the
demultiplexer in figure (a).
Solution:
Notice that the select lines go through a binary sequence so that each successive
input bit is routed to D0, D1, D2 and D3 in sequence as shown by the output
waveforms in figure (b).
Figure (b)

40. THE END OF
CHAPTER 4
Q & A