The document provides an overview of Altera's Cyclone IV FPGA family, including features of the Cyclone IV E and GX variants such as logic elements, memory blocks, multipliers, and I/O standards. It describes the core architecture and blocks including the logic fabric, memory interfaces, clock management resources, and transceiver capabilities. Hard IP support for interfaces like PCI Express is also summarized.

1. Cyclone IV FPGAs Source: Altera Corporation

2. Introduction Purpose An overview study on the Cyclone® IV FPGA Family. Outline Features and Variants. Core Architecture. I/O Features. Clock Management. External Memory Interface. High Speed Transceiver. Hard IP for PCI Express. Content 23 pages

3. Features & Variants Built on an optimized low-power process, the Cyclone IV device family offers the following two variants: Cyclone IV E FPGAs - lowest power, high functionality with the lowest cost for a wide spectrum of general logic applications. Cyclone IV GX FPGAs - lowest power and lowest cost FPGA's with up to eight integrated 3.125-Gbps transceivers.

4. Cyclone IV E FPGA’s: Lowest Cost, Lowest Power Lowest system cost Low cost FPGAs Only 2 power supplies Cost optimized packaging Low power Up to 25% lower power consumption 1.2V and 1.0V core voltage options to optimize for power or performance Low Power process Unprecedented Combination Up to 115K LE of logic Up to 3.8 Mb of Embedded RAM Up to 266 18x18 Embedded Multipliers Up to 535 user IO

5. Cyclone IV GX: Lowest Cost, Low Power FPGAs with Transceivers High functionality Up to 150K Logic Elements Up to 6.5 Mb RAM, 360 Multipliers Up to 8 integrated 3.125Gbps transceivers Lowest system cost Smallest density FPGA with transceivers Integrated Hard IP Only low cost FPGA to support PCIe x1, x2, x4 rootport and endpoint Transceivers built from ground up for low cost Requires only two power supplies Wirebond packages Low power 60nm Low power process PCI to GbE bridge for <1.5W <150 mW per channel 15K LEs + two transceivers in 11 x 11mm package

6. Cyclone IV FPGA Block Diagram

7. FPGA Core Fabric Cyclone IV FPGAs—Logic Element LUT In1 In2 In3 In4 Carry In0 Carry In1 Carry Out0 Carry Out1 LUT chain Register chain General routing Local routing General routing Register chain Clock REG

8. Cyclone IV FPGA’s Embedded Memory Cyclone IV Device M9K Block Data Widths: Feature Cyclone IV Benefit Block size 9 Kbits Memory with parity bits Dual-port read during write behavior New data or old data Flexibility and ease of use Parity bit Yes Usability for high-reliability apps Clock enables 4 Increased flexibility and reduced power Read and write enables 4 Increased flexibility and reduced power Routing Dedicated Higher performance since routing isn’t shared with any other on-chip resource Mode Data Width Configurations Single Port or Simple Dual Port ×1, ×2, ×4, ×8/9, ×16/18, and ×32/36 True Dual Port ×1, ×2, ×4, ×8/9, and ×16/18

9. Cyclone IV FPGA’s Embedded Multipliers Input registers Output registers Supports Full-precision 18-bit or 9-bit mode One 18-bit or two 9-bit multipliers per block

10. Cyclone IV FPGA’s I/O Architecture

11. Supported I/O Standards Type I/O Standard Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X Differential I/O SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS

12. Cyclone IV GX FPGA’s Clock Networks Cyclone IV GX devices include Up to 30 global clocks per device Unused GCKL I/Os can be used as general purpose I/Os MPLLs and GPLLs can be shared if not used by transceiver or core, respectively 12 5 5 5 5 Clock control block Clock control block Clock control block Clock control block 5 5 5 4 5 5 5 4 4 Clock control block GPLL 4 GPLL1 GPLL2 GPLL 2 5 2 2 2 2 2 2 MPLL8 MPLL7 MPLL6 2 2 MPLL5 3 3

13. Cyclone IV E FPGA’s Clock Networks Up to 20 global clocks per device Unused GCKL I/Os can be used as general purpose I/Os GPLL 2 GPLL 4 GPLL 1 GPLL 3 GCLK multiplexer GCLK multiplexer GCLK multiplexer GCLK multiplexer GCLK [14:10] GCLK [9:5] GCLK [15:19] GCLK [0:4] 4 4 4 4

14. External Memory Interfaces Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces. These are on the left side of the device. Interfaces may span two or more sides of the device to allow more flexible board design. The Altera DDR SDRAM memory Interface solution consists of a PHY interface and a memory controller. Cyclone IV devices support use of ECC bits on DDR and DDR2 SDRAM interfaces. External memory Memory controller IP PHY IP / / Flexibility to use Altera or custom memory controller Auto-calibrating PHY minimizes effort for reliable timing closure / /

15. Transceiver Architecture Quad based Full duplex Ideal for clock sharing and channel bonding Flexible clocking enables multiple protocols in a single quad Independent clock-data recovery circuits for each channel Can borrow GPLL, neighboring MPLL Unused MPLLs can be powered down, or used in the core Channel 7 Channel 6 MPLL – Tx/Rx MPLL – Tx/Rx Channel 5 Channel 4 Channel 3 Channel 2 MPLL – Tx/Rx MPLL – Tx/Rx Channel 1 Channel 0 Quad Quad

16. Transceiver Clock Distribution Independent CDR in each Rx channel More granularity from MPLL clocks for tight alignment of Refclk with data Multiple MPLL outputs CLK and CLK2x from each MPLL Additional outputs can be used to feed the FPGA core PLL sharing Can borrow one MPLL from neighboring quad, or one GPLL from core (when available)

17. Protocol Supported By Cyclone-IV FPGA’s These protocols will be supported in a future version of the Quartus ® II software. Cyclone IV GX devices support PCI Express Gen1 ×2, while allowing the remaining two channels within the same transceiver block for other protocol use. Only Channel 0 and Channel 1 support PCI Express Gen1 ×2 implementation.

18. Hard IP for PCI Express Non PCI Express cores (XAUI, Gigabit Ethernet, Serial RapidIO ® , and so on) Soft PCI Express IP protocol stack Soft PCI Express IP transaction layer over hard IP data link and PHY/MAC Hard Gen 1 x1, x2, x4 endpoint/rootport hard IP protocol stack LMI- Local management interface DPRIO- Dynamic partial reconfigurable input/output Transaction layer Transaction layer over hard IP Data link layer PHY/ MAC PMA PCS PMA PCS PMA PCS PMA PCS PIPE-2.0 Hard IP bypass TL bypass PLD fabric logic User application Hard IP PCI Express block Transaction layer Data link layer PHY/MAC layer Non PCI Express applications Soft IP PCI Express protocol stack 4 3 2 1 Cyclone IV GX transceivers TL PCS: Physical coding sublayer PMA: Physical media attachment Parallel access DPRIO LMI PMA PCS PMA PCS PMA PCS PMA PCS Soft logic PCI Express hard IP PCS/PMA

19. Key Hard IP Features End-point / Root-port dual-mode core Root-port for embedded applications PCI Express base rev 2.0-compliant protocol stack Integrated transaction layer (TL), data link layer (DLL), physical interface/media access control (PHY/MAC), and transceivers x1, x2, x4 initial link width configurations Supporting down-configuration and lane reversal Configurable maximum payload size 128, 256 bytes High-performance throughput Close to the maximum theoretical bandwidth.

20. Programmable Logic is Found Everywhere! Cellular Basestations Wireless LAN Switches Routers Optical Metro Access Broadband Audio/video Video display Studio Satellite Broadcasting Medical Test equipment Manufacturing Card readers Control systems ATM Navigation Entertainment Secure comm. Radar Guidance and control Wireless Networking Wireline Entertainment Broadcast Automotive Instrumentation Military Security & Energy Management Servers Mainframe RAID SAN Copiers Printers MFP Computers Storage Office Automation Consumer Automotive Test, Measurement, & Medical Communications Broadcast Military & Industrial Computer & Storage

21. Application: Broadcast Video Capture Card

22. Application: Consumer Video Displays

23. Additional Resource For ordering Cyclone IV FPGAs, please click the part list or call our sales hotline For more product information go to http://www.altera.com/products/devices/cyclone-iv/cyiv-index.jsp Visit Element 14 to post your question For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility Newark Farnell http://www.element14.com/community/community/suppliers/altera/cycloneiv