This document discusses different types of instruction hazards in pipelines including structural hazards, data hazards, and control hazards. It focuses on control hazards caused by branches, where the destination of the branch is unknown until it is evaluated. To resolve this, it discusses different branch prediction strategies like stalling, deciding the branch in the ID stage, delayed branches using compiler reordering, and branch prediction. Branch prediction involves using a branch history table (BHT) to predict if the branch will be taken or not based on its past behavior. The document provides statistics on typical branch behavior and analyzes the accuracy of 1-bit branch prediction. It also discusses scheduling instructions into the delay slot of delayed branches.

1. For queries:
Irfan.Anjum@ucp.edu.pk
Computer Architecture~ Fall 2018 1

2.  Where one instruction cannot immediately follow another
 Types of hazards
◦ Structural hazards - attempt to use same resource twice
◦ Data hazards - attempt to use data before it is ready
◦ Control hazards - attempt to make decision before condition is
evaluated

3.  A control hazard is when we need to find the destination of a
branch, and can’t fetch any new instructions until we know
that destination.
 A branch is either
◦ Taken: PC <= PC + 4 + Immediate
◦ Not Taken: PC <= PC + 4

4.  Condition is evaluated in ALU (True/False), One clock cycle is
need to initialize PC to branch address. Meantime next three
instructions are in pipeline. Branch penalty is 3 cycles.
Fig. 6.37

5. 1. Stall? Not practical, wastes cycles.
2. Decision in ID stage? Add additional hardware, make decision and calculate
address in ID stage. (Branch penalty reduces to one CC).
3. Delayed Branch? Specify in architecture that the instruction immediately
after branch is always executed. Compiler re-arranges code to insert an
independent instruction after branch instrution.
4. Predict? Assume an outcome and continue execution normally, whenever
assumption fails flush three fetched instructions.
1. 1-bit branch prediction
2. 2-bit branch prediction

6.  Based on SPEC (Standard Performance Evaluation Corporation)
benchmarks
◦ Branches occur with a frequency of 14% to 16% in integer programs
and 3% to 12% in floating point programs.
◦ About 75% of the branches are forward branches
◦ 60% of forward branches are taken
◦ 80% of backward branches are taken
◦ 67% of all branches are taken
 Why are branches (especially backward branches) more likely
to be taken than not taken?

7.  For every branch instruction encountered, predict either it will be
taken or not taken.
 Predict Branch taken
◦ Speculatively fetch and execute instructions at the branch target address
◦ Useful only if target address known earlier than branch outcome
◦ May require stall cycles till target address known
◦ Flush pipeline if prediction is incorrect
◦ Must ensure that flushed instructions do not update memory/registers
 Predicting branch not taken:
◦ Speculatively fetch and execute in-line instructions following the branch
◦ If prediction incorrect flush pipeline of speculated instructions
◦ Convert these instructions to NOPs by clearing pipeline registers
◦ Must ensure that flushed instructions do not update memory/registers

8.  Branch History Table (BHT): Lower bits of PC address index
table of 1-bit values
◦ Says whether or not the branch was taken last time
◦ No address check (saves HW, but may not be the right branch)
◦ If prediction is wrong, invert prediction bit
a31a30…a11…a2a1a0 branch instruction
1K-entry BHT
10-bit index
0
1
1
prediction bit
Instruction memory
Hypothesis: branch will do the same again.
1 = branch was last taken
0 = branch was last not taken

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10.  Example:
Consider a loop branch that is taken 9 times in
a row and then not taken once. What is the
prediction accuracy of the 1-bit predictor for
this branch assuming only this branch ever
changes its corresponding prediction bit?
◦ Answer: 80%. Because there are two mispredictions – one on
the first iteration and one on the last iteration. Is this good
enough and Why?

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14. Delayed branches – code rearranged by
compiler to place independent instruction
after every branch (in delay slot).
add RR4,RR5,RR6
beq RR1,RR2,20
lw RR3,400(RR0)
beq RR1,RR2,20
add
RR4,RR5,RR6
lw RR3,400(RR0)

15. Scheduling the Delay Slot

16.  Stall - stop fetching instr. until result is available
◦ Significant performance penalty
◦ Hardware required to stall
 Predict - assume an outcome and continue fetching (undo if
prediction is wrong)
◦ Performance penalty only when guess wrong
◦ Hardware required to "squash" instructions
 Delayed branch - specify in architecture that following
instruction is always executed
◦ Compiler re-orders instructions into delay slot
◦ Insert "NOP" (no-op) operations when can't use (~50%)

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18. Code:
SUB R0, R0, R0
ADDi R2, R0, 0;
ADDi R1, R0, sum of last 4-digits of your registration number;
CONTINUE:
SUB R1, R1, 1
ADDi R2, R2, 0
BNE R1, R2, NEXT;
JMP CONTINUE;
NEXT:
Computer Architecture~ Fall 2018 18

19. Code:
SUB R0, R0, R0
ADDi R2, R0, 0;
ADDi R1, R0, sum of last 4-digits of your registration number;
CONTINUE:
SUB R1, R1, 1
ADDi R2, R2, 0
BEQ R1, R2, NEXT;
JMP CONTINUE;
NEXT:
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