The CPU is made up of 3 major parts: the register set, control unit, and arithmetic logic unit. The register set stores intermediate values during program execution. The control unit generates control signals and selects operations for the ALU. The ALU performs arithmetic and logic operations. Computer architecture includes instruction formats, addressing modes, instruction sets, and CPU register organization. Registers are organized in a bus structure to efficiently transfer data and perform microoperations under control of the control unit. Common instruction fields are the operation code, address fields, and addressing mode fields. Instructions can be classified by the number of address fields as zero-address, one-address, two-address, or three-address instructions. Common addressing modes specify how operands

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Unit I
CPU Organization
1. Introduction
The CPU is made up of 3 major parts:
1. Register set
2. Control unit (CU)
3. Arithmetic and logic unit (ALU)
Register set stores intermediate values used during the execution of the program.
ALU executes the microperations. CU generates the control signal related to microoperation. CU controls
the transfer of information among the registers and selects which operation to be performed by ALU.
Computer Architecture can be defined as computer structure and behaviour as seen by the programmer that
uses machine language instructions. This includes instruction formats, addressing modes, instruction set and
the general organization of CPU registers.
The design of CPU involves choosing hardware for implementing the machine instructions. Assembly
language Programmer must be aware of the register set, memory structure, the type of data supported by the
instructions, and the function that each instruction performs.
Q) Explain about General RegisterOrganization (OR) What is microprogrammed control?
Intermediate values like pointers, counters, return addresses, temporary results and partial products during
multiplication are stored in registers rather than in main memory. Accessing intermediate values is faster
when they are kept in registers. The registers communicate with each other for direct data transfers, while
performing microoperations. Hence it is most efficient if we connect them through a common bus system. A
bus organization of seven CPU registers is as shown below:

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The above diagram consists of 7 registers which are connected to 2 multiplexers (MUX) to form Bus A and
Bus B. The select lines (SELA and SELB ) are used to select the registers to input data to ALU through Bus
A and Bus B.
The ALU performs arithmetic and logical microoperations and generates output. One copy of the output is
stored in the register .
The combined value of SELA( 3bits), SELB( 3bits), SELD( 3bits), OPR (5 bits) (i.e, 3+3+3+5= 14 bits ) is
called control word.
SELA and SELB selects input registers,
SELD selects the output register.
OPR selects the operation to be performed by ALU.
Encoding of register selectionfields
Binary Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Encoding of ALU operations
OPR Select Operation Symbol
00000
00001
00010
00101
00110
Transfer A
Increment A
Add A + B
Subtract A – B
Decrement A
SFA
INCA
ADD
SUB
DECA
Example of micro operation
The following statements demonstrate the sequence of steps that are used to perform microoperation.
For Example to perform the operation R1  R2 + R3 , the sequence of steps will be
[1] MUX A selector (SELA): Here BUS A R2
[2] MUX B selector (SELB): Here BUS B R3
[3] ALU operation selector (OPR): Here 00010 is fed through OPR to perform addition by ALU.
[4] Decoder destination selector (SELD): Selects the register that must store the output. This is decided by
the SELD input given to 3x8 decoder .Here Output generated after the execution of micro operation is
loaded into R1 .
Field: SELA SELB SELD OPR
Symbol: R2 R3 R1 ADD
Control word: 010 011 001 00010

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Microoperation Symbolic Designation Control Word
SELA SELB SELD OPR
R1← R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R6 ← R6 + 1 R6 — R6 INCA 110 000 110 00001
R7 ← R1 R1 — R7 TSFA 001 000 111 00000
A memory unit that stores control word is known as control memory. By reading consecutive control words,
we can generate desired sequence of micro operations. This type of generating control words is known as
Micro programmed control.
Q) Explain about stack organization ? (or) What is stack and how stacks are organized in system
architecture.
Ans:
Stack: set of memory location in which data values are accessed using Last In First Out Technique (LIFO)
is called Stack. Stacks are
1. Very useful feature for nested subroutines, nested interrupt services.
2. Also efficient for arithmetic expression evaluation
3. Stack Pointer (SP) register holds the address of memory location containing top most data item.
4. Only PUSH and POP operations are applicable
Stacks can exist as a standalone unit (Register Stack) or can be implemented as part of main memory
(Memory Stack)
i) Register Stack organization: Stack can be organized as a collection of finite number of memory words or
registers. Below figure shows the organization of a 64-word register stack.
Here DR is a data register used to store the data popped from top of stack. DR register also holds the data to
be pushed onto the stack.
Stack Pointer (SP) register holds the address of memory location containing top most data item.
FULL and EMPTY are one bit registers or Flags. FULL is set to 1 when the stack is full and EMPTY is set
to 1 when the stack is empty. The first item stored in the stack is at address 1. The last item is stored at
address 0. If SP reaches 0, the stack is full, so FULL is set to 1
In 64-word stack, the SP contains 6 bits because 26
= 64 .The first item stored in the stack is at address 1.
The last item is stored at address 0. When SP=63 and ← 𝑆𝑃 + 1 , the result is 0 as 111111+1=1000000 in

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binary. But SP =0 as SP can hold 6 least significant bits(LSB). Also when SP=0 and 𝑆𝑃 ← 𝑆𝑃 − 1 then
000000-1=111111 therefore, SP=63.
ii) Memory Stack Organization
A portion of main memory is used as stack and processor register as SP. Below figure shows portion of
main memory divided into 3 segments -program, data and stack segments. The initial value of SP is 4001
and the stack grows with decreasing addresses.
Thus the first item stored in the stack is at address
4000, the second item is stored at address 3999, and
the last address that can be used for the stack is 3000.
A new item is inserted with push operation as follows
- PUSH operation: SP  SP - 1
M[SP]  DR
An data item is deleted using pop operations as
follows
- POP operation: DR  M[SP]
SP  SP + 1
Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty stack).
Limit checking must be done in software using 2 processor registers. One register to hold upper limit (i.e,
3000 in this case) and another to hold lower limit.
Stack Organization is good for evaluating arithmetic expressions. Common arithmetic expressions are
written in infix notation.
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or reverse Polish notation
Evaluation of Arithmetic Expressions: Any arithmetic expression can be expressed in parenthesis-free
Polish notation. The reverse Polish notation is very suitable for stack. In reverse polish notation operands
are declared first and then the operators. Multiplication and division are performed before addition and
subtraction. The following diagram represents evaluation of arithmetic expression using stack.
The above expression is evaluated from left to right. The operands are pushed onto the stack and the
arithmetic operations are performed on the top 2 elements of the stack, the result is again pushed back onto
stack.
Q) Convert the expression from infix to post fix or reverse polish notation

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Ans: Consider the expression (A + B) * [C * (D + E) + F]
 we must first perform the arithmetic inside the parentheses (A + B) and (D + E). So, AB+DE+
 Next we must calculate the expression inside the square brackets.
 The multiplication of C * (D + E) must be done prior to the addition of F since multiplication has
precedence over addition. So, AB+DE+C*F+
 The last operation is the multiplication of the two terms between the parentheses and brackets
 The converted expression is A B + D E + C * F + *
 The expression can be converted to reverse Polish notation, without the use of parentheses, by taking
into consideration the operation hierarchy.
Q) What are the common fields found in an instruction?
Ans: The bits of the instruction are divided into groups called fields. The most common fields found in
instruction formats are:
1. operation code field (op-code field) that specifies the operation to be performed.
2. An address field that has a memory address or a processor register depending on mode field.
3. A addressing mode field that specifies determines how the address field is to be interpreted (to get
effective address or the operand)
Q) Explain about the most common processor organizations. (or) What are 1-address , 2- address, 3-
address and zer-address instructions. (or) Explain about various types of instruction formats.
Ans:
Most common fields in instruction are op-code field, address field and addressing mode field. The number
of address fields in the instruction format depends on the internal organization of CPU. Most computers fall
into one of the 3 types of CPU organizations. They are
1. Single register (Accumulator) organization
2. General register organization
3. Stack organization
1. Single register (Accumulator) organization: Accumulator is the only general purpose register.
Example : ADD X /* AC  AC + M[X] */ One address instruction
here AC is the accumulator and M[X] is the memory word located at address X. Since the instruction has
one address field, ADD X is a one –address instruction
2. General register organization employs two or three address fields in their instruction format. Each address
field may specify a processor register or a memory word. Any of the registers can be used as the source or
destination for computer operations.
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2, R3 is three address instruction as it has 3 register address fields R1,R2 and R3. First address
field R1 is destination and remaining address fields(R2 and R3) are sources.
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
the above 3 instructions are 2 address instructions as they have 2 address fields.

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3. Stack organization: All operations are done using the hardware stack. have PUSH and POP instruction
which require an address field. Thus the instruction
PUSH X /* TOS  M[X] */
will push the word at address X to the top of the stack. The stack pointer is updated automatically
The instruction ADD
in stack consists of an operation code only with no address field. Hence ADD is a zero address instruction.
This operation will pop the top 2 data items from the stack, adds them and pushes the sum into the stack
Q) Write a program to execute X = (A + B) * (C + D) using zero, one, two, three address instructions
Ans:
 Three-Address Instructions
ADD R1, A, B R1 ← M[A] + M[B]
ADD R2, C, D R2 ← M[C] + M[D]
MUL X, R1, R2 M[X] ← R1 * R2
The advantage of the three-address format is that it results in short programs
The disadvantage is that the binary-coded instructions require too many bits to specify three addresses
 Two-Address Instructions
The first symbol listed in an instruction is assumed to be both a source and the destination where the result
of the operation is transferred
 One- Address Instructions
LOAD A AC  M[A]
ADD B AC  AC + M[B]
STORE T M[T]  AC
LOAD C AC  M[C]
ADD D AC  AC + M[D]
MUL T AC  AC * M[T]
STORE X M[X]  AC
T is the address of a temporary memory location required for storing the intermediate result
 Zero Address instruction
MOV R1, A R1  M[A]
ADD R1, B R1  R1+M[B]
MOV R2, C R2  M[C]
ADD R2, D R2  R2 + M[D]
MUL R1, R2 R1  R1 * R2
MOV X, R1 M[X]  R1

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TOS stands for top of stack
Q) Explain the different Addressing modes with an example
Ans: Addressing modes are used to find the mode of accessing address of operand for processing the
instruction. The most common addressing modes are:
1. Implied Addressing mode.
2. Immediate Addressing Mode.
3. RegisterAddressing Mode
4. RegisterIndirect Addressing Mode
5. Auto-increment or Auto-decrement Addressing
6. Direct Addressing Mode
7. Indirect Addressing Mode
8. Relative Addressing Mode
9. Indexed Addressing Mode
10. Base RegisterAddressing Mode
1. Implied addressing Mode:
In this mode the operands are specified implicitly in the definition of the instruction.
For example, CMA "complement accumulator“
The operand is the accumulator register and the contents of accumulator are complimented and the
complimented result is again stored in accumulator.
Zero-address instructions in a stack-organized computer are implied-mode instructions since the operands
are implied to be on top of the stack.
2. Immediate addressing Mode:
In this mode the operand is specified in the instruction itself.
In other words, an immediate-mode instruction has an operand field rather than an address field.
For example, MVI A, 50 A ←50
This instruction stores the constant value 50 in accumulator register.
3. Register Addressing Mode:
In this mode the operands are in registers that reside within the CPU.
For example, Add R1,R2 R1← R1 + R2
4. Register Indirect Mode:
In this mode the register contains the address of operand in memory i.e, the instruction specifies the registers
in CPU, these register contains the address of operand.
For example: LDA (R1) AC ← M[R1]
5. Auto increment or Auto Decrement mode:
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  (A + B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C + D)
MUL TOS  (C + D) * (A + B)
POP X M[X]  TOS

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This mode is useful to access table of data in memory. When the address stored in the register refers to a
table of data in memory, it is necessary to increment or decrement the register after every access to the table.
This mode is similar to register indirect mode except that the register is incremented or decremented after
the value of memory is accessed
An example for Auto-increment, LDA (R1)+
– AC ← M[R1]
– R1 ← R1+1
An example for Auto-decrement, LDA -(R1)
– R1 ← R1-1
– AC ← M [R1]
6. Direct addressing mode
The operand resides in memory and its address is given directly in the address field of the instruction.
— For example, LDA 4002 AC ← M[4002]
here 4002 is the value in address field of instruction
In this mode the effective address is equal to the address part of the instruction. Here
Effective address is address of operand.
7. Indirect addressing mode:
In this mode the address field of the instruction gives the address where the effective address is stored in
memory.
— For example, LDA @4002 AC ← M[ M[4002] ]
here 4002 is the value in address field of instruction
8. Relative Address Mode:
In this mode the content of the program counter is added to the address part of the instruction in order to
obtain the effective address.
— For example, LDA $ 40 AC ←M[PC+40]
here 40 is the value in address field of instruction
9. Indexed Addressing Mode:
In this mode the content of an index register XR is added to the address part of the instruction to obtain the
effective address.
— For example, LDA add(x) AC ← M[XR+address field value]
Index register is a special CPU register that contains an index value which is automatically incremented after
its contents are accessed. The address field of instruction defines the beginning address of array in memory.
10. Base Register Addressing Mode:
In this mode the content of a base register is added to the address part of the instruction to obtain the e
ffective address. This is similar to the indexed addressing mode except that the register is now called a base
register whose values are not automatically incremented.

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Unit II 8085 Microprocessor
Q) What is 8085 microprocessor? Explain the operations performed by 8085 MPU.
Ans: The 8085 MPU is programmable logic device which consists of registers, flip flops and timing
elements. Depending on internally designed instructions, the 8085 MPU can communicate with peripheral
devices and can process the data depending on the logical design known as Architecture. Categories of
functions performed by microprocessor are
1. Microprocessor initiated operations:
Memory Read and Memory Write operations are performed when the microprocessor wants to read or write
data from memory. I/O Read and Write operations are performed when input is accepted from input device
(peripheral) or output is transmitted to output device (peripheral). To communicate with peripheral or
memory, the MPU needs to perform the following steps
1. Identify the peripheral or memory location (with its address)
2. Transfer binary data
3. provide timing or synchronization signals
The above tasks are performed with the help of 3 buses which are together called system bus. The 3 buses
are
1. Address Bus
2. Data Bus
3. Control Bus
1. Address Bus: To identify a peripheral or memory location, it is provided with binary address. The
address bus is used to carry address bits through 𝐴0 𝑡𝑜 𝐴15 address lines. Using 16 bit addresses, we can
give unique addresses to 216
memory locations. Hence 8085 MPU has 64K memory (216
= 26
∗ 210
=
64𝐾). Address bus is unidirectional i.e, address bits flow from MPU.
2. DataBus: Once the required memory location is identified, the data in that memory location must be read
into MPU. Data bus is used to carry the data through 8 data lines identified by 𝐷0 𝑡𝑜 𝐷7 . Since each
memory location in 8085 can store only 8 bit data, it has. Data bus is bidirectional to allow reading and
writing to memory or peripherals.
Categories of functions performed by 8085
Microprocessor Initiated
Operations
Memory Read
Memory Write
I/O Read
I/O Write
Internal data
operations
Store 8 bit data
Perform Arithmetic
and logical
operations
Check conditions
Control Instruction Execution
Store data temporarily
External
operations
Reset
Interrupt
Ready
Hold

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3. Control Bus:Control bus provides timing and synchronization signals. Control bus is unidirectional
Microprocessor uses control bus to process data, that is what to do with the selected memory location. Some
control signals are Read, Write and Opcode fetch etc. Various operations are performed by microprocessor
with the help of control bus. This is a dedicated bus, because all timing signals are generated according to
control signal. It carries synchronization signal which acts as an handshake signals between the
microprocessor and peripheral devices.
8085 Bus Architecture is as follows
memory Read operation is as shown below
2.Internal data operations
i) To store 8 bit data coming through data lines into MPU, we need registers. The 8085 has six general
purpose 8-bit registers B, C, D, E, H, L . These registers can be combined as register pairs BC, DE and HL

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to perform 16 bit operations. The 8085 programmable registers are as shown below. These are called
programmable register as they are accessible to the programmer
ii) Accumulator register also known as register
A is part of ALU. This register can store 8 bit
data and also the result of operation.
iii) ALU includes five 1-bit flag registers that
are set to 1 or reset to 0 according to data
conditions in the accumulator.
iv) Program counter (PC) is a 16 bit register that
stores the address of memory location that
contains next byte to be fetched. This helps to
sequence the execution of instructions
v) Stack Pointer (SP) is a 16 bit register that
stores the beginning address of memory stack.
3. Peripheral or Externally initiated Operations
External/Peripheral devices can initiate the following operations
1. Reset: When Reset pin is activated, all operations are stopped and PC is reset to 0. The buses are tri-
stated and the program execution begins at zero address.
2. Interrupt: When interrupt occurs, the MPU is interrupted and asked to execute service routine (emergency
instructions). After completing the execution of service routine, the MPU starts executing the instructions
that it was executing before the interrupt.
3. Ready: is used by microprocessor to check whether a peripheral is ready to accept or transfer data.
4. Hold: Hold signal is used in Direct Memory Access( DMA). External devices will request the control of
buses through HOLD signal.
Q) Memory Classification
Ans: The primary memory is of 2 types
1. Random Access Memory (RAM)
2. Read only memory (ROM)
ROM: ROM is a non- volatile memory.
Data in the ROM is not lost when the
power is switched off.
ROM can also be accessed randomly.
Functional representation of ROM
memory cell is as shown below
Types of ROM: ROM comes in following
varieties
1. Masked ROM: contents are
programmed by the manufacturer.
The contents cannot be modified
later.
2. Programmable ROM (PROM):
can be programmed just once by

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"blowing" the fuses. Hence they are also known as one-time programmable (OTP) devices.
3. Erasable Programmable ROM(EPROM): Once programmed, an EPROM can be erased by exposing
it to strong ultraviolet light source for certain amount of time. It will erase the entire EPROM.
4. Electrically Erasable Programmable ROM(EEPROM): An EPROM usually must be removed from
the device for erasing and programming, whereas EEPROMs can be programmed and erased by
special programming signals. EEPROM can be erased one byte at a time. Reprogramming does not
require special equipment and is flexible but slow. Used in printers.
5. Flash memory: Also called Flash BIOS or flash memory. Erased and reprogrammed in blocks.
RAM
RAM is a volatile memory. Data in the RAM is lost when the power is switched off.
The cpu can access any random location in memory directly, hence it is called random access memory.
Types of RAM:
RAMs are of 2 types
1. Static RAM (SRAM) : SRAM chips does not need to be refreshed. Very fast ,Very expensive , than
DRAM. Access time of SRAM is 25 nanoseconds.
2. Dynamic RAM(DRAM): need to be refreshed. Access time is 60 nanoseconds.
Secondary memory is used to store data permanently. The secondary storage devices store huge volumes of
data. Various secondary storage devices are Floppy Disk, Hard Disk, CD-ROM, DVD-ROM, Magnetic tape
etc.
In microprocessor controlled oven, programs that run oven are permanently stored in ROM. Data such
backing period, starting time and temperature are entered in RAM through the keyboard.
Q) Draw the pin diagram of 8085 and explain each pin in detail.
Ans: The intel 8085A also known as 8085 is an 8-bit general purpose microprocessor. The microprocessor
has 40 pins. All the signals provided to the pins are classified into 6 groups
1. Address Bus
2. Data Bus
3. Control and status signals
Memory
Primary Memory
Read/Write
memory
(R/W M)
Static R/W M
(SRAM)
Dyanmic R/W M
(DRAM)
Read only
memory
(ROM)
Erasable
Memory
1) EPROM
2) EE-PROM
3)Flash memory
Permanent
Memory
1) Masked ROM
2) PROM
Secondary
memory/ Back up
storage memory
Semi- random
access
1) Floppy Disk
2) Hard Disk
3) CD-ROM
4) DVD-ROM
Serial
Access
1) Magnetic
tape
2) Magnetic
Bubble
3) CCD

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4. Power Supply and frequency signals
5. Externally initiated Signals and
6. Serial I/O
The Below figure shows the 8085 Pin diagram.
1. Address Bus: The 8085 has 8 lines, 𝐴8 − 𝐴15 used as higher order address bus. These are unidirectional.
2. Multiplexed Address/Data Bus: The lines, 𝐴𝐷0 − 𝐴𝐷7 are bidirectional and are used as lower order
address bus as well as data bus.
3. Control and Status Signals:

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There are 2 control signals ( 𝑅𝐷̅̅̅̅ and 𝑊𝑅̅̅̅̅̅ )and 3 status signals (𝐼𝑂/𝑀̅, 𝑆1, 𝑆0) and one special signal (𝐴𝐿𝐸)
i) 𝐴𝐿𝐸 - Address Latch Enable : This is a positive going pulse generated every time the 8085 begins
an operation.
Control Signals: ii) 𝑅𝐷̅̅̅̅ – This is read control signal (active low). This signal indicate that the data
must be read and must be placed on the data bus
iii) 𝑊𝑅̅̅̅̅̅ - This is Write control signal (active low). This signal indicate the data
must be written
Status Signals: iv) 𝐼𝑂/𝑀̅ – When this signal is high, it indicates I/O operation;
when it is low, it indicates memory operation.
v) 𝑆1 𝑎𝑛𝑑 𝑆0- These signals are used to identify various operations.
4. Power Supply and Frequency Signals
i) 𝑉𝑐𝑐 : +5 V power supply
ii) 𝑉𝑠𝑠: Ground
iii) 𝑋1, 𝑋2 : These are also called crystal inputs and are used to generate clock signals internally.
iv) 𝐶𝐿𝐾 𝑂𝑈𝑇 - Clock output: this signal can be used as system clock.
5. Externally initiated signals including interrupts:
i) The 8085 has 5 interrupt signals that can be used to interrupt a program exection. They are
INTR - Interrupt Request, Restart interrupts RST 7.5, RST 6.5, RST 5.5, TRAP
Interrupt type Maskable interrupt Vector Address Trigger Priority
TRAP No 0024 H (4.5*0008H) Edge and level Triggered 1
RST 7.5 Yes 003C H (7.5*0008H) Edge Triggered 2
RST 6.5 Yes 0034 H (6.5*0008H) Level Triggered 3
RST5.5 Yes 002CH (5.5*0008H) Level Triggered 4
INTR Yes Non-Vectored Level Triggered 5
ii) 𝐼𝑁𝑇𝐴̅̅̅̅̅̅̅ – Interrupt acknowledgement (active low) is used to acknowledge an interrupt.
iii) 𝑅𝐸𝑆𝐸𝑇 𝐼𝑁̅̅̅̅̅̅̅̅̅̅̅̅̅: When signal on this pin goes low, all operations are stopped and PC is reset to 0.
iv) RESET OUT: This signal can be used to reset other devices when the MPU is reset.
v) READY: is used by microprocessor to check whether a peripheral is ready to accept or transfer data.
vi) HOLD: Hold signal is used in Direct Memory Access( DMA). External devices will request the control
of buses through HOLD signal. MPU will give the control of buses by sending 𝐻𝐿𝐷𝐴̅̅̅̅̅̅̅̅
vii) 𝐻𝐿𝐷𝐴̅̅̅̅̅̅̅̅ – Hold acknowledgement is used to acknowledge the HOLD request.
6. Serial I/O : The 8085 has 2 signals to implement serial transmission
i) SID – Serial Input Device
ii)SOD – Serial Output Device.
Q) What is instruction cycle, machine cycle and T-state?
Ans: Instruction cycle is the time required to complete execution of one instruction.
Machine Cycle is the time required to complete one operation.
T-State is the subdivision of operation performed in one clock period.
Q)What are the 3 major phases in instruction cycle. How a microprocessor performs these steps?
(or)
Q) Explain Microprocessor communication and Bus Timings.

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Ans: The 3 major phases in instruction cycle are
1. Fetch the instruction from memory
2. Decode the instruction
3. Exexute the instruction
1. Fetch the instruction : The instruction is fetched from memory. For example:
The steps and timing diagram when the instruction code 0100 1111 (4FH – MOV C,A) stored in memory
location 2005H is being fetched are as shown in the below diagrams.
Step 1: The program counter places 16 bit memory address 2005H on the address bus.
At T1, the higher order memory address 20H is placed on address lines 𝐴8 − 𝐴15
ALE signal goes high and the lower order memory address 05H is placed on 𝐴𝐷0 − 𝐴𝐷7 lines.
𝐼𝑂/𝑀̅ signal is low indicating instruction code must be fetched from memory.
Step 2: The control unit sends the control signal 𝑅𝐷̅̅̅̅ to enable memory chip. 𝑅𝐷̅̅̅̅ is sent during T2.
Step 3: The instruction byte (4FH ) at memory location 2005H is placed on data bus.
Instruction byte (4FH ) is placed on 𝐴𝐷0 − 𝐴𝐷7 lines at T2
when 𝑅𝐷̅̅̅̅ goes high the 𝐴𝐷0 − 𝐴𝐷7 are disabled.
Step 4: The instruction byte (4FH ) is placed in instruction decoder and the contents of accumulator are
copied into register C. This is done during T4.

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Decoding and Executing an instruction: is as shown in the below figure.
To decode and execute the instruction (4FH – MOV C,A) the following steps are performed.
i) The contents of the data bus (4F) are placed in instruction register (𝐼𝑅) and decoded
ii) The contents of accumulator (82) are transferred to the temporary register in ALU.
ii) The contents of the temporary register are transferred to register C.
Q) Explain how the bus 𝑨𝑫 𝟎 − 𝑨𝑫 𝟕 is demultiplexed and how control signals are generated?
Ans: The high order address is placed on the address bus and is held for 3 clock periods,
The low order address is lost after the first clock period, this address needs to be held so we need to use a
latch. ALE is high only in first clock period and ALE signal will enable (G) pin of the latch.
The address AD7 –AD0 is connected as inputs to the latch 74LS373 and lower order address is passed
through 𝐴0 − 𝐴7 output lines of latch.
When ALE goes low, latch is not enabled and the instruction code passes through 𝐷0 − 𝐷7 lines.
The OC –Output control –of the latch is grounded

17. Page:17
Generating Control signals
To generate memory read ( 𝑀𝐸𝑀𝑅̅̅̅̅̅̅̅̅̅), memory write ( 𝑀𝐸𝑊𝑅̅̅̅̅̅̅̅̅̅), read from input device ( 𝐼𝑂𝑅̅̅̅̅̅), write to
ouput device ( 𝐼𝑂𝑊̅̅̅̅̅̅) control signals from 𝑅𝐷̅̅̅̅, 𝑊𝑅̅̅̅̅̅ and
𝐼𝑂/𝑀̅ we need a circuit as shown in the figure.
Truth table for bubbled NAND gates is
Inputs Output of bubbled NAND gate
0 0 0
0 1 1
1 0 1
1 1 1
𝐼𝑂/𝑀̅ 𝑅𝐷̅̅̅̅ 𝑊𝑅̅̅̅̅̅ Control Signal
generated
0 0 1 𝑀𝐸𝑀𝑅̅̅̅̅̅̅̅̅̅
0 1 0 𝑀𝐸𝑊𝑅̅̅̅̅̅̅̅̅̅
1 0 1 𝐼𝑂𝑅̅̅̅̅̅
1 1 0 𝐼𝑂𝑊̅̅̅̅̅̅
To demultiplex and generate the necessary control signals, the 8085 microprocessor requires a latch and
logic gates to build the MPU as shown in the below figure.
Q) Explain the Architecture of 8085 with a neat diagram
Ans: Below figure show the Functional Block Diagram of the 8085. It includes
1. Arithmetic and logic unit (ALU)
2. Timing and Control Unit
3. Instruction Register and Decoder
4. Register Array
5. Interrupt Control
6. Serial I/O Control
1. ALU: ALU includes the accumulator, temporary register, the arithmetic and logic circuits and flag
register.
The result of operation is stored in accumulator.

18. Page:18
Temporary Register:-It is a 8-bit register which is used to hold the data on which the accumulator is
computing operation. It is also called as operand register because it provides operands to ALU.
8-bit Flag register consists of 5 flags which change according to the result stored in accumulator.
1. Sign(S) flag
2. Zero(z) flag
3. Auxiliary carry(AC) flag
4. Parity(P) flag
5. Carry(C) flag
The bit position of the flags in flag register is as shown
i) Sign Flag: Used for indicating the sign of the data in the accumulator. The D7 bit always decides the sign
of the number. This flag is used in signed numbers.
if D7 bit in the result is 1: the result is negative and Sign Flag=1
if D7 bit in the result is 0: the result is positive and Sign Flag=0
ii) Zero Flag: is 1 if the result is 0
iii) Auxiliary carry(AC) flag: is 1 if there is carry out of 3rd bit . This flag is used only internally for Binary
coded Decimal (BCD) operations and not available to programmer.
iv) Parity(P) flag: is 1 if the number of 1’s in the result is even
is 0 if the number of 1’s in the result is odd
v)Carry(C) flag: Is set if there is a carry or borrow from arithmetic operation
2.Timing and Control Unit: It provides timing and control signal to the microprocessor to perform the
various operation. It has 2 control signals 𝑅𝐷̅̅̅̅, 𝑊𝑅̅̅̅̅̅ and 3 status signals /𝑀̅, 𝑆1 𝑎𝑛𝑑 𝑆0. It provides clock to
external circuits by 𝐶𝐿𝐾 𝑂𝑈𝑇 and provides clock to internal circuits by 𝑋1 𝑎𝑛𝑑 𝑋2 . This unit also controls
externally initiated signals (𝑅𝐸𝑆𝐸𝑇 𝐼𝑁̅̅̅̅̅̅̅̅̅̅̅̅̅̅, 𝑅𝐸𝑆𝐸𝑇 𝑂𝑈𝑇 ,HOLD) and provides acknowledgements (𝐻𝐿𝐷𝐴̅̅̅̅̅̅̅̅).
3. Instruction Register (𝐼𝑅) and Decoder: 𝐼𝑅 is a 8-bit register. When an instruction is fetched from memory,
it is stored 𝐼𝑅 register. Decoder decodes the instruction in 𝐼𝑅 register.
4. Register Array: W, Z are 8-bit temporary registers and are used to hold data during arithmetic/logic
operation. They are not used by programmer. There are six general purpose 8-bit registers B, C, D, E, H, L .
These registers can be combined as register pairs BC, DE and HL to perform 16 bit operations.
5. Interrupt Control: There are 6 interrupt pins in this unit. Generally an external hardware is connected to
these pins. These pins provide interrupt signal sent by external hardware to microprocessor and
microprocessor sends acknowledgement for receiving the interrupt signal. Generally INTA is used for
acknowledgement.
6. Serial I/O Control: There are two pins in this unit. This unit is used for serial data communication.
Example 1:
1011 0101
+ 0110 1100
---------------
Carry 1 0010 0001
Example 2:
1011 0101
- 1100 1100
---------------
Borrow 1 1110 1001

19. Page:19
Q) Instruction Set Classification
Ans: 1. Data Transfer (Copy) Operations:
These operations simply COPY the data from the source to the destination. The data in the source is
not changed.
The various types of data transfer (copy) are listed below
Type Examples
Between registers Copy the contents of register B into register D
Data Byte to a register or memory location Load Register B with data byte 32H
Between a memory location and a register From the memory location 2000H to register B
Between an IO Device and the accumulator From an input keyboard to the accumulator
2. Arithmetic Operations :
a) Addition(ADD, ADI): Any 8-bit number or the contents of a register or the contents of a memory
location can be added to the contents of the accumulator and the result is stored in the accumulator.
b) Subtraction(SUB, SUI): Any 8-bit number or the contents of a register or the contents of a memory
location can be subtracted from the contents of the accumulator. The result is stored in the
accumulator. Subtraction is performed in2’s compliment notation. Negative result is also expressed
in 2’s compliment notation.
c) Increment and Decrement : The 8-bit contents of any memory location or any register can be
directly incremented or decremented by 1. These operations can be performed in any register or in a
memory location. No need to disturb the contents of the accumulator.

20. Page:20
3. Logical Operations: These instructions perform logic operations on the contents of the accumulator.
a) AND , OR, Exclusive OR: Any 8-bit number or the contents of a register or the contents of a
memory location can be logically ANDed , ORed or Exclusive-ORed with the contents of
accumulator. The result is stored in the accumulator.
b) Rotate: Rotate the contents of the accumulator one position to the left or right.
c) Compare: Any 8-bit number or the contents of a register or the contents of a memory location can be
compared for equality, >,< with the contents of accumulator.
d) Compliment: 1’s complement the contents of the accumulator.
4. Branching Operations: alters the sequence of program execution either conditionally or unconditionally.
a) Jump: Conditional jump instructions jump to new location only if certain conditions (Zero flag or
Carry flag) is set or reset. Unconditional jump instructions jump to new location no matter what.
b) Call, Return and Restart: These instructions change the sequence of program either by calling
subroutine or returning from a subroutine. Conditional Call and Return instructions also can test
condition flags.
5. Machine Control operations: These instructions control machine functions such as Halt, Enable and
disable interrupt or do nothing.
Q) Instruction format
Each instruction has two parts. The first part is the task or operation to be performed. This part is called the
“opcode” (operation code). The second part is the data to be operated on called the “operand”. The operand
(data) can be specified in various ways. It may include 8-bit or 16-bit data, an internal register, a memory
loacation or 8-bit or 16-bit address. In some instructions operand is implicit.
Instruction Set Classification
Data Transfer (COPY)
Operations
Between
registers
Data Byte to a
register or
memory
location
Betweena
memory
locationand
a register
Betweenan
IODevice
and the
accumulator
Arithmetic
Operations
Addition
Subtraction
Increment or
decrement
Logic
Operations
AND,OR,
Exclusive-
OR
Rotate
Compare
Compliment
Branching
Operations
Jump
Call, Return
and Restart
Machine
Control
Operations
Halt
Enable/
Disable
Interrupt
NOP

21. Page:21
Q) Explain the instruction set supported by 8085
Ans: Since the 8085 is an 8-bit device it can have up to 28 (256) instructions. However, the 8085 only uses
246 combinations that represent a total of 74 instructions. Most of the instructions have more than one
format.
The following notations are used
R = 8085 8-bit register (A, B, C, D, E, H, L)
M = Memory register , it contains data at address present in HL register
Rs = Source Register (A, B, C, D, E, H, L)
Rd = Destination Register (A, B, C, D, E, H, L)
Rp = Register Pair (BC, DE, HL, SP)
[ ] = Contents of
1. Data transfer instructions
Mnemonics Tasks Addressing
mode
Instruct
ion
Size
Example
MOV Rd, Rs Copy data in Rs into Rd.
[ 𝑅𝑑] ← [𝑅𝑠]
Register 1- byte
MOV B, C
MOV R, M Copy data from M into R
[𝑅] ← [𝐻𝐿]
Register
Indirect
1-byte Instruction: LXI H, 2034H
[HL] = 2034H,
[2034] = 58H & [B] = C5H
Instruction: MOV B,M
After execution: [B] = 58H
& M = 58 H
MOV M, R Copy data from R into M.
[𝐻𝐿] ← [𝑅]
Register
Indirect
1-byte
MVI R, 8-bit data Load 8-bit data into R.
[ 𝑅] ←8-bit data
Immediate 2-byte MVI C, 05H
LXI Rp, 16 bit data Loads 16-bit data into Rp.
[ 𝑅𝑝] ←16-bit data
Immediate 3-byte LXI B, D500 H
[B] =D5H & [E]=00H

22. Page:22
LDA 16-bit address Load accumulator with data at given
16-bit address.
[ 𝐴] ← [16-bit address]
Direct 3-byte LDA 9580 H
[9580]=05H
After execution:
[A] =05H
STA 16-bit addre Store the data in accumulator at
given 16-bit address.
[16-bit address] ← [𝐴]
Direct 3-byte STA 9580 H
[A] =05H
After execution:
[9580]=05H
LDAX Rp Load accumulator with the data
present in address stored in Rp
[𝐴] ← [𝑅𝑝]
Register
Indirect
3-byte Let B = 35H & C = 45H
& 3545 location has 22H
Instruction: LDAX B
A = 22H
STAX Rp Store the data in accumulator at
address contained in Rp.
[𝑅𝑝] ← [𝐴]
Register
Indirect
3-byte Let B = 35H & C = 45H
& A = 22H
Instruction: STAX B
3545 location has 22H
OUT 8-bit port
address
Write the data in accumulator to
output device that has 8-bit port
address
Direct 2 byte OUT 07H
IN 8-bit port
address
Accept data from input device that
has 8-bit port address and store it in
accumulator
Direct 2 byte IN 02H
LHLD 16 bit
address
Load HL register with 16bit address.
L ← data stored in 16-bit address.
H ← data stored in 16-bit address+1
Direct 3 bytes Let [C050] = 28 H &
[C051] = 66 H
Instruction: LHLD C050H
After execution:
[H] = 66H & [L] = 28 H
SHLD 16 bit
address
data in 16-bit address ← L
data in 16-bit address+1 ← H
Direct 3 bytes
XCHG [H] ↔ [D]
[L] ↔ [E]
Register 1 byte
2. Arithmetic instructions:
In ADD R, ADD M, SUB R, SUB M, ADI, SUI all the flags are affected.
Mnemonics Tasks Addressing
mode
Instructi
on Size
Example
ADD R Add the contents of R with contents of
accumulator. Result is stored in
accumulator. [A]← [ 𝐴] + [𝑅]
Register 1 byte Let [C] = 05H , [A] =03H
Instruction: ADD C
After execution:
[A] =08H
ADD M Add the contents of M with contents of
accumulator. Result is stored in
accumulator. [A]← [ 𝐴] + [𝐻𝐿]
Register
Indirect
1 byte [HL] = 2034H,
[2034] = 05H & [A] = 03H
Instruction: ADD M
After execution:
[A] = 08H & M = 05 H
SUB R Subtract the contents of R from contents
of accumulator. [ 𝐴] ← [ 𝐴] − [𝑅]
Register 1 byte
SUB M Subtract the contents of R from contents
of accumulator. [ 𝐴] ← [ 𝐴] − [𝐻𝐿]
Register
Indirect
1 byte
ADI 8-bit data Add 8-bit data to contents of
accumulator. [A]← [ 𝐴] + 8-bit data
Immediate 2 bytes [A] = 03H
Instruction: ADI 05 H
After execution: [A] = 08H
SUI 8-bit data Subtract 8-bit data from the contents of
accumulator. [A]← [ 𝐴] − 8-bit data
Immediate 2 bytes
INR R Increment contents of R by 1
[𝑅] ← [ 𝑅] +1
Register 1 byte All flags except carry flag
are affected. [C] = FF H
Instruction: INR C
After execution: [C] = 00H

23. Page:23
DCR R Decrement contents of R by 1
[ 𝑅] ← [ 𝑅] −1
Register 1 byte All flags except carry flag
are affected
INR M Increment the contents of M by 1
[ 𝐻𝐿] ← [ 𝐻𝐿] +1
Register 1 byte All flags except carry flag
are affected
DCR M Decrement the contents of M by 1
[ 𝐻𝐿] ← [ 𝐻𝐿] −1
Register 1 byte All flags except carry flag
are affected.
Let [HL] = F050H &
[F050] = 05H
Instruction: DCR M
After execution: [F050] = 04H
INX Rp Increment the contents of Rp by 1
[ 𝑅𝑝] ← [ 𝑅𝑝] +1
Register 1 byte No flags effected
Let [HL] = F050H
Instruction: INX H
After execution: [HL]=F051H
DCX Rp Decrement contents of Rp by 1
[ 𝑅𝑝] ← [ 𝑅𝑝] −1
Register 1 byte No flags effected
DAD Rp [ 𝐻𝐿] ← [ 𝐻𝐿]+ [𝑅𝑝] Register 1 byte Only carry flag affected
3. Logical Instructions:
Logical instructions
 implicitly assume accumulator as one of the operand and the result is stored in accumulator.
 modifies Z, P, S flags according to the result
 resets CY flag. (except CMA instruction : CMA does not affect any flags
 Do not affects the operand register.
Mnemonics Tasks Addressing
mode
Inst.
Size
ANA R/M Logically AND [R] /[M] with [A] Register/Register
indirect
1-byte
ORA R/M Logically OR [R]/[M] with [A] Register/Register
indirect
1-byte
XRA R/M Logically Exclusive-OR [R] / [M] with [A] Register/Register
indirect
1-byte
ANI 8-bit data Logically AND 8-bit data with [A] Immediate 2-byte
ORI 8-bit data Logically OR 8-bit data with [A] Immediate 2-byte
XRI 8-bit data Logically Exclusive-OR 8-bit data with [A] Immediate 2-byte
CMA Compliment [A] Implied 1-byte
CMP R/M Compare [R/M] with [A] for < , > or =
if [A] < [R/M]: carry flag is set
if [A] = [R/M]: zero flag is set
if [A] > [R/M]:: carry and zero flags are reset.
Example:CMP B or CMP M
Register/Register
indirect
1-byte
CPI 8-bit data Compare 8-bit data with [A] for < , > or =
The values being compared remain unchanged.
The result of the comparison is shown by setting the flags
of the PSW as follows:
if [A] < data: carry flag is set
if [A] = data: zero flag is set
if [A] > data: carry and zero flags are reset
Example: CPI 89H
Immediate 2-byte
RLC Rotate accumulator left Implied 1-byte

24. Page:24
Rotate [A] to left by 1-bit
RRC Rotate accumulator right
Rotate [A] to right by 1-bit
Implied 1-byte
RAL Rotate accumulator left through carry Implied 1-byte
RAR Rotate accumulator right through carry Implied 1-byte
4. Branching Instructions:
The branching instruction are classified into 3 categories
 Jump instructions
 Call and Return instructions
 Restart instructions
i) Jump instructions: have an instruction size of 3 bytes. All these instruction have immediate addressing
mode. Jump instructions are of two types
a) Unconditional Jump instructions : Example
Mnemonics Tasks
JMP 16-bit address Jump to 16-bit address unconditionally
b) Conditional Jump instructions
Mnemonics Tasks
JC 16-bit address Jump on carry
Jump to 16-bit address if result generates carry and CY =1
JNC 16-bit address Jump on No Carry (CY=0)
JZ 16-bit address Jump on Zero

25. Page:25
Jump to 16-bit address if result is zero and Z =1
JNZ 16-bit address Jump on No Zero (Z=0)
JP 16-bit address Jump on plus (if 𝐷7 = 0 𝑎𝑛𝑑 𝑆 = 0)
JM 16-bit address Jump on minus (if 𝐷7 = 1 𝑎𝑛𝑑 𝑆 = 1)
JPE16-bit address Jump on even parity (P=1)
JPO 16-bit address Jump on Odd parity (P=0)
ii) Call and Return instruction
Mnemonics Tasks
CALL 16-bit address Change the program sequence to location of subroutine mentioned
as 16 bit address in the instruction
RET Return to calling program after completion of subroutine.
5. Machine control instructions
Mnemonics Tasks
HLT Stop processing and wait
NOP Do not perform any operation
Q) What are the different addressing modes supported by 8085
Ans:

26. Page:26

27. Page:27
Q) Write an Assembly language program(ALP) to perform 1’s compliment on 8-bit number.
Ans:
Input: is 0FH stored at memory location 4500H
Let us store the complemented number at memory location 4600H.
Source program:
LDA 4500H ; Load Accumulator with data in the location 4500H
CMA ;Complement the number
STA 4600H ;Store the result in accumulator to location 4600H
HLT ;Terminate program execution
Output: Result = F0H is stored at memory location 4600H
Q) Write an Assembly language program(ALP) to perform 2’s compliment on 8-bit number.
Ans: Input : is 0FH stored at memory location 4500H
Let us store the result at memory location 4600H.
Source program:
LDA 4500H ; Load Accumulator with data in the location 4500H [𝐴] ← 0𝐹 H
CMA ;Complement the number [𝐴] ← 𝐹0H
INR A ; Increment the contents of accumulator [𝐴] ← 𝐹1H
STA 4600H ;Store the result in accumulator to location 4600H [4600] ← 𝐹1 H
HLT ;Terminate program execution
Output: Result = F1H is stored at memory location 4600H
Q) Write an Assembly language program(ALP) to perform 2’s compliment
on 16-bit number.
Ans:Let input 16- bit number be 050FH
Address Contents
3000 05H Lower byte of input number
3001 0FH Higher byte of input number
LHLD 3000H ;Load H-L pair with operand from 3000H.
[ 𝐿] ← 𝑐𝑜𝑛𝑡𝑒𝑛𝑡𝑠 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 3000
[ 𝐻] ← 𝑐𝑜𝑛𝑡𝑒𝑛𝑡𝑠 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 3001 i.e,
[𝐻] ← 05H [𝐿] ← 0𝐹 H
MOV A, L ;Move the lower-order from reg. L to reg. A. [𝐴] ← 0𝐹 H
CMA ;Complement accumulator. [𝐴] ← 𝐹0H
MOV L, A ;Move the result from reg. A to reg. L. [𝐿] ← 𝐹0H
MOV A, H ;Move the higher-order from reg. H to reg. A. [𝐴] ← 05 H
CMA ;Complement accumulator. [𝐴] ← 𝐹𝐴 H
MOV H, A ;Move the result from reg. A to reg. H. [𝐻] ← 𝐹𝐴H
INX H ;Increment H-L pair. [𝐿] ← 𝐹1 H
SHLD 3002H ;Store the result at address 3002H. [3002H] ← [𝐿]
[3003H] ← [𝐻]
HLT ;Halt.
Output: Result : F1FAH
Address Contents
3002 F1H Lower byte of result

28. Page:28
3003 FAH Higher byte of result
Q) Write an Assembly language program(ALP) to perform 1’s compliment on 16-bit number.
Ans:Let input 16- bit number be 050FH
Address Contents
3000 05H Lower byte of input number
3001 0FH Higher byte of input number
Program:
LHLD 3000H ;Load H-L pair with operand from 3000H. [𝐻] ← 05H
[𝐿] ← 0𝐹 H
MOV A, L ;Move the lower-order from reg. L to reg. A. [𝐴] ← 0𝐹 H
CMA ;Complement accumulator. [𝐴] ← 𝐹0H
MOV L, A ;Move the result from reg. A to reg. L. [𝐿] ← 𝐹0H
MOV A, H ;Move the higher-order from reg. H to reg. A. [𝐴] ← 05 H
CMA ;Complement accumulator. [𝐴] ← 𝐹𝐴 H
MOV H, A ;Move the result from reg. A to reg. H. [𝐻] ← 𝐹𝐴H
SHLD 3002H ;Store the result at address 3002H. [3002H] ← [𝐿]
[3003H] ← [𝐻]
HLT ;Halt.
Output: Result : F0FAH
Address Contents
3002 F0H Lower byte of result
3003 FAH Higher byte of result
Q) Write an Assembly language program(ALP) to perform addition of two 8-bit numbers.
Ans:
Input: First 8-bit number is 05H stored at memory location 4500H
Second 8-bit number is 03H stored at memory location 4501H
Let us store the result at memory location 4600H.
Source program:
Label Mnemonics Comments
MVI C, 00H ;Clear C register to hold carry
[𝐶] ←00H
LDA 4500H ; [ 𝐴] ← [4500] 𝑖. 𝑒, [𝐴] ← 05H
MOV B, A ; copy the contents of A into B [𝐵] ← 05 H
LDA 4501H ;[ 𝐴] ← [4501] 𝑖. 𝑒, [𝐴] ← 03H
ADD B ; [ 𝐴] ← [ 𝐴] + [𝐵] i.e, [ 𝐴] ← 08H
JNC LOOP ; jump if no carry to label LOOP
INR C Increment carry
LOOP: STA 4600H ;Store the addition result at address 4600 i.e,
[4600] ← [𝐴]
MOV A, C ; [ 𝐴] ← [𝐶]
STA 4601H ; store carry at address 4601 i.e, [4600] ← [𝐶]
HLT ;Halt
Output: Result = 08H and Carry =00 H
Before
Execution:
After Execution:
4500H: 05H 4600H: 08H
4501H: 03H 4601H: 00H

29. Page:29
Q) Write an Assembly language program(ALP) to perform addition of two 16-bit numbers.
Ans: Let first 16- bit number be 0105H and second number be 0203H
Address Contents
3000 05H Lower byte of first number
3001 01H Higher byte of first number
3002 03H Lower byte of second number
3003 02H Higher byte of second number
Label Mnemonics Comments
MVI C, 00H ;Clear C register to hold carry
[𝐶] ←00H
LHLD 3000H ;Load H-L pair with operand from 3000H.
[ 𝐿] ← 𝑐𝑜𝑛𝑡𝑒𝑛𝑡𝑠 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 3000
[ 𝐻] ← 𝑐𝑜𝑛𝑡𝑒𝑛𝑡𝑠 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 3001 i.e,
[𝐻] ← 01H [𝐿] ← 05H
XCHG ; [H] ↔ [D] [L] ↔ [E]
[𝐷] ← 01 H [𝐸] ← 05 H
LHLD 3002H ;[ 𝐿] ← 𝑐𝑜𝑛𝑡𝑒𝑛𝑡𝑠 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 3002
[ 𝐻] ← 𝑐𝑜𝑛𝑡𝑒𝑛𝑡𝑠 𝑜𝑓 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 3003 i.e,
[𝐻] ← 02H [𝐿] ← 03H
DAD D ;Add HL pair with DE pair
[ 𝐻] ← [ 𝐻] + [ 𝐷] and [ 𝐿] ← [ 𝐿] + [ 𝐸] i.e,
[ 𝐻] ← 03H and [ 𝐿] ←08H
JNC LOOP ; jump if no carry to label LOOP
INR C ;Move the result from reg. A to reg. H. [𝐻] ← 𝐹𝐴H
LOOP: SHLD 4600H ; Store the result at address 4600H. [4600H] ← [𝐿]
[4601H] ← [𝐻]
MOV A,C ; [ 𝐴] ← [𝐶]
STA 4602 H ; store carry at address 4601 i.e, [4602] ← [𝐶]
HLT ;Halt.
Output: Result = 0308H and carry =0
Address Contents
4600 08H Lower byte of addition result
4601 03H Higher byte of addition result
4602 00H Carry
Q) Write an Assembly language program(ALP) to perform multiplication of two 8-bit numbers.
Ans: To perform 02 H * 05H the following ALP is written
Label Mnemonic Comment
MVI C, 00H ;Clear C register [𝐶] ←00H
MVI A, 02H ;[A] ←02 H
MOV B, A ; [B] ←02 H
MVI A, 05H [A] ←05 H
MOV D, A ;[D] ← [𝐴] i.e, [ 𝐷] ←05 H here D is multiplier = 05 H
MVI A, 00H ;Clear accumulator [A] ←00 H
SUM: ADD B ; [A] ← [ 𝐴] + [𝐵]
JNC DEC ;Jump if no carry to label DEC
INR C ; [ 𝐶] ← [ 𝐶]+ 1

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DEC: DCR D ; [D] ← [ 𝐷] − 1
JNZ SUM ; Jump if D is not equal to zero to Label SUM
STA 4600H ; Store the result at address 4600H
MOV A,C ;Move carry in C to A
STA 4601H ;Store carry at address 4601H
HLT ;Halt
Output: Result = 0AH and carry =00H
Q) Write an Assembly language program(ALP) to perform Multiplication of two 16-bit numbers.
Ans: 0002H * 0005H
Address Contents
3000 02H Lower byte of first number
3001 00H Higher byte of first number
3002 05H Lower byte of second number
3003 00H Higher byte of second number
Label Mnemonics Comments
MVI C, 00H ;Clear C register [𝐶] ←00H
LHLD 3000H ;Load H-L pair with operand from 3000H.
SPHL ;[ 𝑆𝑃] ← [ 𝐻𝐿]
LHLD 3002H ; Load H-L pair with operand from 3000H.
XCHG ; [H] ↔ [D] [L] ↔ [E]
MVI L, 00H
MVI H, 00H
SUM: DAD SP ;Add HL pair with SP [ 𝐻𝐿] ← [ 𝐻𝐿] + [ 𝑆𝑃]
JNC DEC ;Jump if no carry to label DEC
INX C ; [ 𝐶] ← [ 𝐶] + 1
DEC: DCX D ; [DE] ← [ 𝐷𝐸] − 1
JNZ SUM ; Jump if DE is not equal to zero to Label SUM
LOOP: SHLD 4600H ; Store the result at address 4600H. [4600H] ← [𝐿]
[4601H] ← [𝐻]
MOV A,C ; [ 𝐴] ← [𝐶]
STA 4602 H ; store carry at address 4601 i.e, [4602] ← [𝐶]
HLT ;Halt.
Output: Result = 0008H and carry =0
Address Contents
4600 08H Lower byte of addition result
4601 00H Higher byte of addition result
4602 00H Carry
Q) Write an Assembly language program (ALP) to find Sum of series.
Ans: The length of the series is in memory location 4200 H and
the series begins from memory location 4201 H.
Sample problem:
Address Contents
4600 0AH Result
4601 00H Carry
Address Content
4200 H 03 H Size of series
4201 H 02 H First element in series
4202 H 05 H Second element in series
4203 H 03 H Third element in series

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Source program:
Result =02+05+03= 0A H . The Result is stored at 4300 H = 0A H
Q) Write an Assembly language program (ALP) to perform sorting
Ans:
Before Execution:
Address Content
4200 H 03 H Size of array
4201 H 02 H First element in array
4202 H 05 H Second element in array
4203 H 03 H Third element in array
Source Program:
Label Mnemonics Comment
LXI H,4200
MOV C,M
DCR C
REPEAT: MOV D,C
LXI H,4201
LOOP: MOV A,M
INX H
CMP M
JC SKIP
MOV B,M
MOV M,A
DCX H
MOV M,B
INX H
SKIP: DCR D
JNZ LOOP
DCR C
JNZ REPEAT
HLT
After Execution:
Label Mnemonic Comment
LDA 4200H
MOV C, A ; store the size of array in C
MVI A, 00H
LXI H, 4201 H ;HL register stores the address 4201
BACK: ADD M ;M register contains the data at 4201
[ 𝑀] ← [4201]i.e, [ 𝑀] ← 02H
INX H HL register increments to 4202
DCR C
JNZ BACK
STA 4300 H
HLT
Address Content
4200 H 03 H Size of series
4201 H 02 H First element in array after sorting

32. Page:32
Q) Explain about Stack concept in 8085
Ans: Stack in 8085 is a memory stack i.e, a set of memory locations in main memory is reserved for
stack.The beginning of the stack is defined in program using the instruction.
LXI SP, 16-bit address.
Storing of data bytes begins at memory address one less than the address in stack pointer register.
For Example : If a program is running, it is placed in main memory. If program memory ranges from 2000
to 23FF, SP is initialized to 2400 i.e, (1+23FF) i.e, one address beyond the program memory. Information is
saved on the stack by PUSHing it on. It is retrieved from the stack by POPing it off. The 8085 provides two
instructions: PUSH and POP for storing information on the stack and retrieving it back. Both PUSH and
POP work with register pairs ONLY.
PUSH instructions in Stack: PUSH B, PUSH D, PUSH H, PUSH PSW instructions are 1-byte
instructions. Here PSW means program status word. Accumulator and flag register is together called PSW.
Initialization of stack pointer register to 2400H LXI SP,2400H [SP]← 2400H
LXI B, 12F3H [B] ←12H and [C] ←F3H
Decrement SP [SP] ← [SP] -1 [SP]← 23FFH
Copy the contents of register B to the memory location
pointed to by SP
PUSH B M[SP] ← 12H
Decrement SP [SP] ← [SP] -1 [SP]← 23FEH
Copy the contents of register C to the memory location
pointed to by SP
M[SP] ← F3H
PUSH PSW
Decrement SP [SP] ← [SP] -1 [SP]← 23FDH
Copy the contents of Accumulator to the memory
location pointed to by SP
M[SP] ← [A]
Decrement SP [SP] ← [SP] -1 [SP]← 23FCH
Copy the contents Flag register to the memory location
pointed to by SP
M[SP] ← [Flag register]
4202 H 03 H Second element array after sorting
4203 H 05 H Third element in array after sorting

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POP instructions in Stack: POP B, POP D, POP H, POP PSW instructions are 1-byte instructions
[SP]← 23FCH
Copy the contents of the memory location pointed to by
the SP to Flag register
POP PSW [Flag register] ← M[SP]
Increment SP [SP] ← [SP] +1 [SP]← 23FDH
Copy the contents of the memory location pointed to by
the SP to accumulator register
[A] ←M[SP]
Increment SP [SP] ← [SP] +1 [SP]← 23FEH
Copy the contents of the memory location pointed to by
the SP to E register
POP D [E]← F3H
Increment SP [SP] ← [SP] +1 [SP]← 23FFH
Copy the contents of the memory location pointed to by
the SP to D Register
[D]← 12H
Increment SP [SP] ← [SP] +1 [SP]← 2400H
The order of PUSHs and POPs must be opposite of each other in order to retrieve information back into its
original location.
PUSH B
PUSH D
...
POP D
POP B
Reversing the order of the POP instructions will result in the exchange of the contents of BC and DE.
Q) Explain about Subroutine concept in 8085
Ans: A subroutine is a group of instructions that will be used repeatedly. Instead of writing the same
instructions repeatedly, the repeated instructions are written only once as subroutine and called whenever
required. The 8085 has two instructions for dealing with subroutines. The CALL instruction is used to
redirect program execution to the subroutine. The RET instruction is used to return the execution to the
calling routine.
For Example : If a program is running, it is placed in main memory as shown in the figure. In the below
program memory ranges from 2000H to 23FFH, SP is initialized to 2400H.

34. Page:34
The main program calls subroutine located at 2070H by using CALL 2070H instruction . The address of next
instruction 2043H stored in program counter (PC) is placed on the stack as shown below.
and the program is transferred to the subroutine at 2070 H by placing 2070H in Program Counter.
Subroutine gets executed and when the microprocessor executes RET instruction in the subroutine at address
207F H, the contents of stack are popped and placed in Program Counter and PC=2043H. The main program
resumes execution from 2043H and continues till HLT instruction
Q) Passing Data to a Subroutine
Ans: In Assembly Language data is passed to a subroutine through registers.
The data is stored in one of the registers by the calling program and the subroutine uses the value from the
register.
The other possibility is to use agreed upon memory locations.
The calling program stores the data in the memory location and the subroutine retrieves the data from the
location and uses it.
Q)Conditional Call and Conditional Return instructions
Ans: The conditional Call and Return instructions are based on four data conditions (flags) : Carry, Zero,
Sign and Parity. In case of a conditional Call, the program is transferred to the subroutine if the condition is
met. In case of a conditional Return instruction, the sequence returns to main program if the condition is
met.
Conditonal Call instructions are:
Mnemonics Tasks
CC 16-bit address Call Subroutine if carry flag CY =1
CNC 16-bit address Call Subroutine if carry flag CY=0
CZ 16-bit address Call Subroutine if Zero flag Z =1
CNZ 16-bit address Call Subroutine if Zero flag Z=0
CP 16-bit address Call Subroutine if Sign flag is reset (if 𝐷7 = 0 𝑎𝑛𝑑 𝑆 = 0)
CM 16-bit address Call Subroutine if Sign flag is set(if 𝐷7 = 1 𝑎𝑛𝑑 𝑆 = 1)
CPE16-bit address Call Subroutine if parity flag P=1, even parity
CPO 16-bit address Call Subroutine if parity flag P=0, odd parity
Conditional return instructions are:
Mnemonics Tasks
RC 16-bit address Return if carry flag CY =1

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RNC 16-bit address Return if carry flag CY=0
RZ 16-bit address Return if Zero flag Z =1
RNZ 16-bit address Return if Zero flag Z=0
RP 16-bit address Return if Sign flag is reset (if 𝐷7 = 0 𝑎𝑛𝑑 𝑆 = 0)
RM 16-bit address Return if Sign flag is set(if 𝐷7 = 1 𝑎𝑛𝑑 𝑆 = 1)
RPE16-bit address Return if parity flag P=1, even parity
RPO 16-bit address Return if parity flag P=0, odd parity
Q) Advanced Subroutine concepts
Ans: 1. Nesting Subroutines is the programming technique of a subroutine calling another subroutine. This
process is limited only by the number of available stack locations. When a subroutine calls another
subroutine, all return addresses are stored on the stack. Nesting of subroutines is as shown in the below
figure. The main program calls subroutine at 2050H . The address of next instruction 2053H is placed on the
stack and the program is transferred to the subroutine at 2090H. Subroutine I calls Subroutine II from
location 209AH. The address of next instruction 209DH is placed on the stack and the program is transferred
to the subroutineII at 20C2H. The sequence of execution returns to the main program as shown in the
figure.
Multiple Ending Subroutines:
The below figure shows three possible endings to one CALL instruction. The subroutines has two
conditional returns( RZ –Return on Zero and RC – Return on Carry) and one unconditional return (RET). If
Zero Flag (Z) is set, the subroutine returns from the location 2050H. If the carry flag (CY) is set, it return
from location 2058H. If neither the Z nor the CY flag set, it returns from location 2070H.
2.
Q) Write an ALP program to convert a BCD number into binary
Ans: Assume 2-digit BCD number be 0111 0010 = 7210 stored at memory address 2200H and store the
result in memory location 2300H.
To convert we store BCD1 = 210 and BCD2 = 710 and do
7 * 10+2 i.e, BCD2 * 10 + BCD1 to get the equivalent binary number.
Source Program:
Label Mnemonics Comments
LDA 2200H Get the BCD number i.e, A=0111 0010

36. Page:36
Q) Write an ALP program to convert a binary into BCD number
Ans: Sample Problem: Let the binary number (1111 1111)2 be stored at memory location 6000 H .
(1111 1111)2 = FFH = 25510 (Decimal 255)
Example: Here we divide 255 by 100 by repetitive subtraction and store the quotient in BCD3. Once the
remainder after division becomes <100, we divide the remainder by 10 repetitive subtraction and store the
quotient in BCD2 and the remainder is stored as BCD1
Check Do Quotient
Since 255 > 100 255-100 = 155 1
Since 155 > 100 155-100 = 55 2
Since 55 < 100 Check if 55< 10 BCD3 = 2 = 0000 0010
Since 55> 10 55-10=45 1
Since 45 > 10 45-10 =35 2
Since 35 > 10 35-10 =25 3
Since 25>10 25-10=15 4
Since 15>10 15-10=5
Since 5<10 BCD2 = 5 = 0000 0101
Store BCD1=5 = 0000 0101
Program:
LDA 6000H Get the binary number in accumulator (1111 1111)2 = FFH
MVI B, 64H Load divisor 64H = decimal 100 in B register
MVI C, 0AH Load divisor0AH = decimal 10 in C register
STEP1: CMP B Check if number < Decimal 100
JC STEP 2 if yes go to step 2
SUB B Subtract decimal 100
MOV B, A B=0111 0010
ANI 0FH Mask most significant four bits A= 0000 0010
MOV C,A Save unpacked BCD1 in C i.e, C= 0000 0010
MOV A, B Get BCD again A=0111 0010
ANI F0H Mask least significant four bits A= 0111 0000
RRC Convert most significant four bits into unpacked
BCD2 i.e, A= 0011 1000
RRC A= 0001 1100
RRC A = 0000 1110
RRC A= 0000 0111
MOV D, A Save unpacked BCD2 in D register D= 0000 0111
XRA A Clear accumulator
MVI E, 0AH Set E as a multiplier of 10 E=0000 1010
SUM: ADD E Add 10 until contents of D = 0. Using this loop
E=10 is added 7 times to get 70 i.e, A=0100 0110
DCR D Decrement BCD2 by one
JNZ SUM Is multiplication complete? i if not, go back and
add again
ADD C Add BCD1 i.e, A=0100 1000
STA 2300H Store the result i.e, A= (0100 1000)2 = 7210
HLT Terminate program execution

37. Page:37
INR E update quotient
JMP STEP 1 go to step 1
STEP2: CMP C Check if number < Decimal 10
JC STEP 3 if yes go to step 3
SUB C Subtract decimal 10
INR D Update quotient
JMP STEP 2 Continue division by 10
STEP3: STA 6100H Store Digit 0
MOV A, D Get Digit 1
STA 6101H Store Digit 1
MOV A, E Get Digit 2
STA 6102H Store Digit 2
Output:
Q) Write an ALP program to convert a ASCII HEX to Binary number
Ans:
ASCII stands for American standard code for information interchange. It is a seven bit code and its 128
combinations are assigned different alphanumeric characters. For example: Hexadecimal number 30 H to 39H
represent 0 to 9 ASCII decimal numbers and 41H represents A, 42H represents B, 43H represents C, 44H
represents D, 45H represents E, 46H represents F .....5AH represents Z.
input: ASCII code 41H stored in memory location C200H
Label Mnemonics Comment
LDA C200H ;Load the accumulator with binary number A=0100 0001
SUI 30H ;Subtract immediate data 30H from the contents of
accumulator A= 0001 0001 = (decimal 11)
CPI 0AH ;Compare immediately the accumulator content with 0AH
Since (0001 0001)> (0000 1010) CY = 0
JC ST Jump if carry to label ST
SUI 07 ;Subtract immediate data 07H the contents of accumulator
0001 0001 -0000 0111 =0001 0001+1111 1001 =0000 1010= 0AH
ST: STA C202H ;Store the accumulator content at C202H
Here result = 0AH
HLT ;Halt the execution
Output: 0AH (binary output ) stored at memory location C202H
Q) Write an ALP program to convert Binary to ASCII Hex Code
Ans:
Input: 8-bit binary number 9AH stored at memory location 4050H
Main Program:
Label Mnemonics Comments
LXI SP, 4100H Initialize Stack pointer
LDA 4050H Get the binary number i.e, A=1001 1111
LXI D, 4060H Point index where ASCII code to be stored i.e, [DE] ←4060H
MOV B, A Save byte in B=1001 1010
Memory address Content
6100H
6101H
6102H

38. Page:38
RRC Shift high order nibble to lower order nibble.
A=1100 1111
RRC A= 11100111
RRC A = 1111 0011
RRC A= 1111 1001
CALL ASCII Call Conversion subroutine
STAX D Store first ASCII Hex in 4060H
INX D [DE] ←4061H
MOV A, B Get the input binary number i.e, A=1001 1111
CALL ASCII
STAX D Store Second ASCII Hex in 4061H
HLT Terminate program execution
ASCII: this subroutine converts binary digit between 0 and F to ASCII Hex code.
input: Single binary number in accumulator
output: ASCII Hex code in accumulator
Label Mnemonic Comments First byte Second byte
ANI 0FH Mask most significant four
bits
Before execution:
A=1111 1001
after execution ANI 0FH:
A= 0000 1001=09H
Before execution:
A=1001 1111
after execution ANI 0FH:
A= 0000 1111=0FH
CPI 0AH Is digit less than decimal 10 CY =1 as 09H < 0A H CY =0 as 0FH >0A H
JC CODE If digit less than decimal 10
go to label CODE and add
30 H
ADI 07 H ADD 07 to obtain code for
digits from A to F
A= 0FH +7 H = 16 H
CODE: ADI 30 H Add base number 30 H A= 30H +9 H = 39 H A= 30H +16 H = 46 H
RET Return to calling program
Output
Memory address Content
4060H 39 H ASCII Hex code 39H represents 9 ASCII decimal number
4061H 46 H ASCII Hex code 46H represents F