RISC - Reduced Instruction Set ComputingTushar Swami
A detailed presentation about what is RISC and some of the basic differences between RISC and CISC Computers.
Also enlisting some of the major applications of RISC in the field of Technology.
RISC - Reduced Instruction Set ComputingTushar Swami
A detailed presentation about what is RISC and some of the basic differences between RISC and CISC Computers.
Also enlisting some of the major applications of RISC in the field of Technology.
Interstage buffer B1 feeds the Decode stage with a newly-fetched instruction.
Interstage buffer B2 feeds the Compute stage with the two operands
Interstage buffer B3 holds the result of the ALU operation
Interstage buffer B4 feeds the Write stage with a value to be written into the register file
A brief introduction to processor organization ‒ the main examined topic is the description of processor's general characteristics and their evident impacts.
This presentation was given at the Faculty of Informatics of Masaryk University in 2018 within the PA174 Design of Digital Systems II course.
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated cycle
There are three classes of hazards
Structural hazard
Data hazard
Branch hazard
The topic focuses on different aspects of processor organization and architecture such as architecture models, register organization, instruction formats, addressing modes etc.
Interstage buffer B1 feeds the Decode stage with a newly-fetched instruction.
Interstage buffer B2 feeds the Compute stage with the two operands
Interstage buffer B3 holds the result of the ALU operation
Interstage buffer B4 feeds the Write stage with a value to be written into the register file
A brief introduction to processor organization ‒ the main examined topic is the description of processor's general characteristics and their evident impacts.
This presentation was given at the Faculty of Informatics of Masaryk University in 2018 within the PA174 Design of Digital Systems II course.
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated cycle
There are three classes of hazards
Structural hazard
Data hazard
Branch hazard
The topic focuses on different aspects of processor organization and architecture such as architecture models, register organization, instruction formats, addressing modes etc.
Introduction
CPU performance factors
Instruction count
Determined by ISA and compiler
CPI and Cycle time
Determined by CPU hardware
We will examine two MIPS implementations
A single cycle version
A multiple cycles version
Simple subset, shows most aspects
Memory reference: lw, sw
Arithmetic/logical: add, sub, and, or, slt
Control transfer: beq, j
§4.1 Introduction
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
1
Instruction Execution
PC instruction memory, fetch instruction
Register numbers register file, read registers
Depending on instruction class
Use ALU to calculate
Arithmetic result
Memory address for load/store
Branch target address
Access data memory for load/store
PC target address or PC + 4
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
2
CPU Overview
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
3
Multiplexers
Can’t just join wires together
Use multiplexers
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
4
Control
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
5
Logic Design Basics
§4.2 Logic Design Conventions
Information encoded in binary
Low voltage = 0, High voltage = 1
One wire per bit
Multi-bit data encoded on multi-wire buses
Combinational element
Operate on data
Output is a function of input
State (sequential) elements
Store information
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
6
Combinational Elements
AND-gate
Y = A & B
A
B
Y
I0
I1
Y
M
u
x
S
Multiplexer
Y = S ? I1 : I0
A
B
Y
+
A
B
Y
ALU
F
Adder
Y = A + B
Arithmetic/Logic Unit
Y = F(A, B)
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
7
Sequential Elements
Register: stores data in a circuit
Uses a clock signal to determine when to update the stored value
Edge-triggered: update when Clk changes from 0 to 1
D
Clk
Q
Clk
D
Q
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
8
Sequential Elements
Register with write control
Only updates on clock edge when write control input is 1
Used when stored value is required later
D
Clk
Q
Write
Write
D
Q
Clk
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
9
Clocking Methodology
Combinational logic transforms data during clock cycles
Between clock edges
Input from state elements, output to state element
Longest delay determines clock period
Morgan Kaufmann Publishers
9 April, 2013
Chapter 4 — The Processor
10
Instruction Processing Cycle
Instruction Fetch: using value in program counter (PC) to fetch “next” instruction from main memory into the processor
Decode instruction and update PC
Compute operand address from operand specification in instruction
Fetch operands
Execute instruction
Store Result
Go to I
ICyle Compressed Version
Send PC value to fetch instruction
Read one .
4bit pc report[cse 08-section-b2_group-02]shibbirtanvin
Report on Very Simple Computer Design & Implementation_
4bit PC_DSD_report[CSE-08_Section-B2_Group-02]
Courtesy:
Tanvir Al Amin Popel
Tanvir Ahmed Khan
Imtiaz Ahmad
This presentation includes basic of PCOS their pathology and treatment and also Ayurveda correlation of PCOS and Ayurvedic line of treatment mentioned in classics.
Normal Labour/ Stages of Labour/ Mechanism of LabourWasim Ak
Normal labor is also termed spontaneous labor, defined as the natural physiological process through which the fetus, placenta, and membranes are expelled from the uterus through the birth canal at term (37 to 42 weeks
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
• The Committee on Ways and Means has been investigating several universities since November 15, 2023, when the Committee held a hearing entitled From Ivory Towers to Dark Corners: Investigating the Nexus Between Antisemitism, Tax-Exempt Universities, and Terror Financing. The Committee followed the hearing with letters to those institutions on January 10, 202
How to Add Chatter in the odoo 17 ERP ModuleCeline George
In Odoo, the chatter is like a chat tool that helps you work together on records. You can leave notes and track things, making it easier to talk with your team and partners. Inside chatter, all communication history, activity, and changes will be displayed.
it describes the bony anatomy including the femoral head , acetabulum, labrum . also discusses the capsule , ligaments . muscle that act on the hip joint and the range of motion are outlined. factors affecting hip joint stability and weight transmission through the joint are summarized.
Safalta Digital marketing institute in Noida, provide complete applications that encompass a huge range of virtual advertising and marketing additives, which includes search engine optimization, virtual communication advertising, pay-per-click on marketing, content material advertising, internet analytics, and greater. These university courses are designed for students who possess a comprehensive understanding of virtual marketing strategies and attributes.Safalta Digital Marketing Institute in Noida is a first choice for young individuals or students who are looking to start their careers in the field of digital advertising. The institute gives specialized courses designed and certification.
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Thinking of getting a dog? Be aware that breeds like Pit Bulls, Rottweilers, and German Shepherds can be loyal and dangerous. Proper training and socialization are crucial to preventing aggressive behaviors. Ensure safety by understanding their needs and always supervising interactions. Stay safe, and enjoy your furry friends!
This slide is special for master students (MIBS & MIFB) in UUM. Also useful for readers who are interested in the topic of contemporary Islamic banking.
Executive Directors Chat Leveraging AI for Diversity, Equity, and InclusionTechSoup
Let’s explore the intersection of technology and equity in the final session of our DEI series. Discover how AI tools, like ChatGPT, can be used to support and enhance your nonprofit's DEI initiatives. Participants will gain insights into practical AI applications and get tips for leveraging technology to advance their DEI goals.
Strategies for Effective Upskilling is a presentation by Chinwendu Peace in a Your Skill Boost Masterclass organisation by the Excellence Foundation for South Sudan on 08th and 09th June 2024 from 1 PM to 3 PM on each day.
1. Chapter 4 The Processor Cheng-Jung Tsai Assistant Professor Department of Mathematics, National Changhua University of Education, Taiwan, R.O.C. Email: [email_address] Modified from the instructor’s teaching material provided by Elsevier inc. Copyright 2009
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6. FIGURE 4.1 An abstract view of the implementation of the MIPS subset branch on equal beq $1,$2,25 if ($1 == $2) go to PC+4+100 This figure showing the major functional units and the major connections between them . All instructions start by using the program counter to supply the instruction address to the instruction memory . After the instruction is fetched, the register operands used by an instruction are specified by fields of that instruction . Once the register operands have been fetched, they can be operated on by ALU to compute a memory address (for a load or store), to compute an arithmetic result (for an integer arithmetic-logical instruction), or a compare (for a branch). If the instruction is an arithmetic-logical instruction, the result from the ALU must be written to a register . If the operation is a load or store, the ALU result is used as an address to either store a value from the registers or load a value from memory into the registers . The result from the ALU or memory is written back into the register file . Branches require the use of the ALU output to determine the next instruction address , which comes either from the ALU (where the PC and branch offset are summed) or from an adder that increments the current PC by 4 . The thick lines interconnecting the functional units represent buses , which consist of multiple signals.
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9. FIGURE 4.2 The basic implementation of the MIPS subset, including the necessary multiplexors and control lines . The top multiplexor (“Mux”) controls what value replaces the PC ( PC + 4 or the branch destination address ); the multiplexor is controlled by the gate that “ANDs ” together the Zero output of the ALU and a control signal that indicates that the instruction is a branch . The middle multiplexor , whose output returns to the register file, is used to steer the output of the ALU (in the case of an arithmetic-logical instruction) or the output of the data memory (in the case of a load) for writing into the register file . Finally, the bottommost multiplexor is used to determine whether the second ALU input is from the registers (for an arithmetic-logical instruction OR a branch) or from the offset field of the instruction (for a load or store). The added control lines are straightforward and determine the operation performed at the ALU, whether the data memory should read or write, and whether the registers should perform a write operation. The control lines are shown in color to make them easier to see.
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11. Recall in Computer Science: Logic operations at the bit level Truth table: a truth table defines the values of the output for each possible input or inputs. exclusive-or
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23. FIGURE 4.9: The datapath for a branch Just re-routes wires Sign-bit wire replicated PC+4 or branch target
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26. Figure 4.11 in p.315 Full Datapath PC+ 4 or branch target Arithmetic or address calculation load or ALU result Give you 5 minutes to be familiar with this datapath & Please try the “Check Yourself” in P.315 What is missed in this Figure? Control Unit
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32. FIGURE 4.16 & 4.18: The effect of each of the seven control signals 0 1
33. FIGURE 4.17: The simple datapath with the control unit. The PCsrc control line should be set if the instruction is branch on equal and the Zero output of ALU is true. Used to decide which operation is performed Used to decide if a branch is taken rs rt rd op address or f-code
55. Pipeline Performance : Fig. 4.27 in P.333 Single-cycle (T c = 800ps) Pipelined (T c = 200ps) Unbalanced stage length reduce the speedup of pipeline
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60. Structural Hazard: Single Memory Mem I n s t r. O r d e r Time Load Instr 1 Instr 2 Instr 3 Instr 4 Reg Mem Reg Reg Mem Reg ALU Mem ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg ALU ALU Mem Reg Mem Reg
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70. MIPS with Predict Not Taken Prediction correct Prediction incorrect
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76. MIPS Pipelined Datapath WB MEM Right-to-left flow leads to hazards FIGURE 4 . 33 Each step of the instruction can be mapped onto the datapath from left to right . The only exceptions (left-to-right) are the update of the PC and the write-back step, which sends either the ALU result (can lead to control hazard) or the data from memory to the left to be written into the register file (can lead to data hazard) Control hazard data hazard
81. ID for Load, Store, … FIGURE 4.36 Although the load needs only the top register in stage 2, the processor doesn’t know what instruction is being decoded , so it sign-extends the 16-bit constant and reads both registers into the ID/EX pipeline register.
82. EX E for Load FIGURE 4.37 The register is added to the sign-extended immediate, and the sum is placed in the EX/MEM pipeline register.
83. MEM for Load FIGURE 4.38 Data memory is read using the address in the EX/MEM pipeline registers, and the data is placed in the MEM/WB pipeline register.
84. WB for Load FIGURE 4.38 Next, data is read from the MEM/WB pipeline register and written into the register file in the middle of the datapath. Note: there is a bug in this design that is repaired in Figure 4.41. Who will supply this address?
85. FIGURE 4 . 41 Corrected Datapath for Load The write register number now comes from the MEM/WB pipeline register along with the data. The register number is passed from the ID pipe stage until it reaches the MEM/WB pipeline register, adding 5 more bits to the last three pipeline registers . I-type
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87. FIGURE 4.40 MEM for Store In the fourth stage, the data is written into data memory for the store . Note that the data comes from the EX/MEM pipeline register and that nothing is changed in the MEM/WB pipeline register.
88. FIGURE 4.40 WB for Store Once the data is written in memory, there is nothing left for the store instruction to do, so nothing happens in stage 5 .
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93. Recall: FIGURE 4.17: The simple datapath with the control unit. The PCsrc control line should be set if the instruction is branch on equal and the Zero output of ALU is true. Used to decide which operation is performed rs rt rd op address or f-code Used to decide if a branch is taken
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96. FIGURE 4.51 The pipelined datapath of Figure 4.46 with the control signals connected to the control portions of the pipe line registers. The control values for the last three stages are created during the ID stage and then placed in the ID/EX pipeline register . The control lines for each pipe stage are used, and remaining control lines are then passed to the next pipeline stage.
112. FIGURE 4.54 Forwarding Paths hardware On the top are the ALU and pipeline registers before adding forwarding. On the bottom, the multiplexors have been expanded to add the forwarding paths , and we show the forwarding unit. This figure is a stylized drawing, how ever, leaving out details from the full datapath such as the sign extension hardware. Note that the ID/EX. RegisterRt field is shown twice, once to connect to the mux and once to the forwarding unit, but it is a single signal.
113. FIGURE 4 . 55 The control values for the forwarding multiplexors
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117. FIGURE 4 . 56 The datapath modified to resolve hazards via forwarding
163. Dynamically Scheduled CPU Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Preserves dependencies Hold pending operands
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169. The Opteron X4 Microarchitecture §4.11 Real Stuff: The AMD Opteron X4 (Barcelona) Pipeline 72 physical registers
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Editor's Notes
20 May 2010
20 May 2010
20 May 2010 OK, let get on with today lecture by looking at the simple add instruction. In terms of Register Transfer Language, this is what the Add instruction need to do. First, you need to fetch the instruction from Memory. Then you perform the actual add operation. More specifically: (a) You add the contents of the register specified by the Rs and Rt fields of the instruction. (b) Then you write the results to the register specified by the Rd field. And finally, you need to update the program counter to point to the next instruction. Now, let take a detail look at the datapath during various phase of this instruction. +2 = 10 min. (X:50)
20 May 2010
20 May 2010
20 May 2010
20 May 2010
20 May 2010
20 May 2010
20 May 2010 Well, the last slide pretty much illustrate one of the biggest disadvantage of the single cycle implementation: it has a long cycle time. More specifically, the cycle time must be long enough for the load instruction which has the following components: Clock to Q time of the PC, .... Having a long cycle time is a big problem but not the the only problem. Another problem of this single cycle implementation is that this cycle time, which is long enough for the load instruction, is too long for all other instructions. We will show you why this is bad and what we can do about it in the next few lectures. That all for today. +2 = 79 min (Y:59)
20 May 2010
20 May 2010
20 May 2010
20 May 2010 What happened if we try to pipeline the R-type instructions with the Load instructions? Well, we have a problem here!!! We end up having two instructions trying to write to the register file at the same time! Why do we have this problem (the write ubble?? Well, the reason for this problem is that there is something I have not yet told you. +1 = 16 min. (X:56)
20 May 2010 I already told you that in order for pipeline to work perfectly, each functional unit can ONLY be used once per instruction. What I have not told you is that this (1st bullet) is a necessary but NOT sufficient condition for pipeline to work. The other condition to prevent pipeline hiccup is that each functional unit must be used at the same stage for all instructions. For example here, the load instruction uses the Register File Wr port during its 5th stage but the R-type instruction right now will use the Register File port during its 4th stage. This (5 versus 4) is what caused our problem. How do we solve it? We have 2 solutions. +1 = 17 min. (X:57)
20 May 2010 As shown here, each of these five steps will take one clock cycle to complete. And in pipeline terminology, each step is referred to as one stage of the pipeline. +1 = 8 min. (X:48)
20 May 2010 The main control here is identical to the one in the single cycle processor. It generate all the control signals necessary for a given instruction during that instruction Reg/Decode stage. All these control signals will be saved in the ID/Exec pipeline register at the end of the Reg/Decode cycle. The control signals for the Exec stage (ALUSrc, ... etc.) come from the output of the ID/Exec register. That is they are delayed ONE cycle from the cycle they are generated. The rest of the control signals that are not used during the Exec stage is passed down the pipeline and saved in the Exec/Mem register. The control signals for the Mem stage (MemWr, Branch) come from the output of the Exec/Mem register. That is they are delayed two cycles from the cycle they are generated. Finally, the control signals for the Wr stage (MemtoReg & RegWr) come from the output of the Exec/Wr register: they are delayed three cycles from the cycle they are generated. +2 = 45 min. (Y:45)
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