This document compares the power usage of 4x4 Wallace tree multipliers designed using different types of full adders. It first describes a conventional design using a 28-transistor full adder that has high power consumption due to its large transistor count. A second design using a 16-transistor full adder is then presented, which reduces power but still has issues. Finally, the document proposes a new design using an 11-transistor full adder that achieves up to 50% lower power usage compared to the conventional 28-transistor design. The 11-transistor full adder design overcomes previous voltage degradation issues. Simulation results in Cadence show the proposed 11-transistor design