The document presents a method for reducing the maximum height of the partial product array in a 64-bit radix-16 booth multiplier, achieving an improvement in design efficiency without increasing delay. This reduction facilitates more flexible design options for pipelined multipliers and can extend to other multiplier types. The study emphasizes the importance of optimizing binary multiplication for low power and high-performance applications.

1. PARTIAL PRODUCT ARRAY HEIGHT REDUCTION USING
RADIX-16 FOR 64-BIT BOOTH MULTIPLIER
PRESENTED BY(A11 Batch):
G. NIRMALA (18MG1A0404)
M.LAKSHMI (18MG1A0416)
D.SURYA TEJA (18MG1A0432)
SK.MUJEEB (18MG1A0449)
G.TEJESH REDDY (18MG1A0435)
INTERNAL GUIDE:
Mr. K. RAMESH, M. TECH.
ASSISTANT PROFESSOR.
SREE VAHINI INSTITUTE OF SCIENCE AND TECHNOLOGY, TIRUVURU
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERNG

2. CONTENTS
o ABSTRACT
o INTRODUCTION
o EXISTING SYSTEM
o PROPOSED SYSTEM
o BLOCK DIAGRAM
o SCHEMATIC
o WORKING
o SOFTWARE DEVELOPMENT
o EXPERIMENTAL RESULT
o ADVANTAGES
o APPLICATIONS
o FUTURE SCOPE
o CONCLUSION
o REFERENCES

3. ABSTRACT
 Reduce the maximum height of the partial product columns to [n/4] for n = 64-bit unsigned
operand. This is in contrast to the conventional maximum height of [(n + 1)/4].
 Therefore, a reduction of one unit in the maximum height is achieved.
 It may allow further optimizations of the partial product array reduction stage in terms of
area/delay/power
 Additional addends to be included in the partial product array without increasing the delay.
 The multiplier algorithm is normally used for higher bit length applications and ordinary
multiplier is good for lower order bits.
 These two methods are combined to produce the high speed multiplier for higher bit length.
 The main objective of this research paper is to design architecture for radix-4 complex
 Multiplier by rectifying the problems in the existing method and to improve the speed by using
the common Boolean logic (cbl).

4. INTRODUCTION
 Binary multipliers are widely used building block element in the design of microprocessors
 Embedded systems, and therefore, they are an important target for implementation
optimization.
 Current implementations of binary multiplication follow the steps of
 1) Recoding of the multiplier in digits in a certain number system
 2) Digit multiplication of each digit by the multiplicand, resulting in a certain number of
partial products
 3) Reduction of the partial product array to two operands using multi operand addition
techniques and
 4) Carry propagate addition of the two operands to obtain the final result.

5. EXISTING SYSTEM
 The problem of existing architecture is reduced by removing bits from the remainders. To
reduce the maximum height of the partial product bit array we perform a short carry
propagate addition in parallel to the regular partial product generation.
 This short addition reduces the maximum height by one row and it is faster than the
regular partial product generation.
 The elements of the bit array to be added by the short adder the resulting partial product bit
array after the short addition.
 Comparing both figures, we observe that the maximum height is reduced from 17 to 16 for
n = 64.

6. PROPOSED SYSTEM
 In this work, we have presented a method to reduce by one the maximum height of the
partial product array for 64-bit radix-16 Booth recoded magnitude multipliers.
 This reduction may allow more flexibility in the design of the reduction tree of the
pipelined multiplier.
 We have shown that this reduction is achieved with no extra delay for n ≥ 32 for a cell-
based design.
 The method can be extended to Booth recoded radix-8 multipliers, signed multipliers
and combined signed/unsigned multipliers

7. BLOCK DIAGRAM
High level view of the recoding and partial product generation stage
including our proposed scheme

8. WORKING
 Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed
binary numbers in two’s complement notation
 Partial product for multiplying two or three digit numbers in columns that can be easier
by making use of standard algorithm of multiplication.
 In a large number multiplication grouping the number to multiply into parts, multiply
the parts separately, and then add.
 A product formed by multiplying the multiplicand by one digit of the multiplier when
the multiplier has more than one digit.
 Partial products are used as intermediate steps in calculating larger products. The partial
product to solve a multiplication equation can set it up like a traditional long
multiplication equation.

9. SCHEMATIC
Overall Schematic view of 64-bit Booth algorithm

10. SOFTWARE DEVELOPMENT
XILINX ISE SOFTWARE
The Integrated Software Environment (ISE™) is the Xilinx® design software suite that allows you to take your
design from design entry through Xilinx device programming. The ISE Project Navigator manages and
processes your design through the following steps in the ISE design flow.
1.DESIGN ENTRY: Design entry is the first step in the ISE design flow. During design entry, you create your
source files based on your design objective.
2. SYNTHESIS: After design entry and optional simulation you run synthesis
3. IMPLEMENTATION: After synthesis, you run design implementation, which converts the logical design
into a physical file format that can be downloaded to the selected target device.
4.VERIFICATION: You can verify the functionality of your design at several points in the design flow.
You can use simulator software to verify the functionality and timing of your design or a portion of your design
5.DEVICECONFIGURATION: After generating a programming file, you configure your device.
During configuration, you generate configuration files and download the programming files from a host
computer to a Xilinx device.

11. BOOTH MULTIPLIER

12. EXPERIMENTAL RESULT

13. SIMULATION RESULTS

15. ADVANTAGES
 This technique is general, but its impact (reduction of one row without increasing
the critical path of the partial product generation stage) depends on the specific
timing of the different components.
 Therefore, it cannot claim a successful result for all practical values of r and n
and different implementation technologies.
 Thus, it concentrates on a specific instance: a 64-bit radix-16 Booth recoded
unsigned multiplier implemented with a synthesis tool and a standard-cell library.
 Therefore by using radix-16 since it is the most complex case, among the practical
values of the radix, for the design of our scheme.

16. APPLICATIONS
 It has the most basic advantage in digital signal processing.
 It is used along with multiplier-accumulator (MAC)that reduces the partial
derivatives of multiplication product with ease in circuitry.
 It increases the efficiency of the system by enhancing its speed.
 Better performance in low cost at low power consumption.

17. FUTURE SCOPE
 we will extend an optimization for binary radix-32 (modified) Booth recoded
multipliers to reduce the maximum height of the partial product columns to [n/4]
for n = N-bit unsigned operands.
 This is in contrast to the conventional maximum height of [(n + 1)/4]. Therefore, a
reduction of one unit in the maximum height is achieved.
 This reduction may add flexibility during the design of the pipelined multiplier to
meet the design goals, it may allow further optimizations of the partial product
array reduction stage in terms of area/delay/power and/or may allow additional
addends to be included in the partial product array without increasing the delay.
 The method can be extended to Booth recoded radix-8 multipliers, signed
multipliers, combined signed/unsigned multipliers, and other values of n.

18. CONCLUSION
 Pipelined large word length digital multipliers are difficult to design under the constraints of
core cycle time (for nominal voltage), pipeline depth, power and energy consumption and area.
Low level optimizations might be required to meet these constraints.
 In this work, we have presented a method to reduce by one the maximum height of the partial
product array for 64-bit radix-16 Booth recoded magnitude multipliers.
 This reduction may allow more flexibility in the design of the reduction tree of the pipelined
multiplier. We have shown that this reduction is achieved with no extra delay for n ≥ 32 for a
cell-based design.
 The method can be extended to Booth recoded radix-8 multipliers, signed multipliers and
combined signed/unsigned multipliers. Radix-8 and radix-16 Booth recoded multipliers are
attractive for low power designs, mainly to the lower complexity and depth of the reduction tree,
and therefore they might be very popular in this era of power-constrained designs with
increasing overheads due to wiring.

19. REFERENCES
 [1] Weiqiang Liu, Liangyu Qian, Chenghua Wang, and Jie Han “Design of Approximate Radix
4 Booth Multipliers for Error-Tolerant Computing ,” IEEE Trans
 [2] F. Lamberti et al., “Reducing the computation time in (short bit-width) twos complement
multipliers,” IEEE Trans. Comput., vol. 60, no. 2, pp. 148– 156, Feb. 2011.
 [3] N. Petra et al., “Design of fixed-width multipliers with linear compensation function,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 947–960, May 2011.
 [4] S. Galal et al., “FPU generator for design space exploration,” in Proc. 21st IEEE Symp.
Comput. Arithmetic (ARITH), Apr. 2013, pp. 25–34.
 [5] K. Tsoumanis et al., “An optimized modified booth recoder for efficient design of the add-
multiply operator,” IEEETrans.Circuits Syst.I,Reg. Papers, vol. 61, no. 4, pp. 1133–1143, Apr.

20. THANK YOU