This document is a project report submitted by four students on the design of a clock generator circuit using a 555 timer IC. The circuit uses a potentiometer to vary the clock frequency from 10 kHz to 50 kHz. The report includes the block diagram, circuit diagram, calculations for determining frequency and duty cycle, simulation results from Multisim, and hardware test results from a breadboard prototype and oscilloscope measurements. The project involved designing, simulating, building and testing a clock generator circuit that successfully produces a variable frequency clock signal as required.

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Project Report on
Clock Generator
Submitted By
Chaitanya Deshpande T187001
Kaustubh Wankhede T187003
Nikhil Patil T187010
Omkar Rane T187014
A report submitted to an autonomous institute affiliated to Savitribai Phule Pune
University in partial fulfillment of the requirements for the course DIGITAL
COMMUNICATION in ELECTRONICS & TELECOMMUNICATION
SCHOOL OF ELECTRICAL ENGINEERING
ALANDI (D), PUNE
2018 - 19

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SCHOOL OF ELECTRICAL ENGINEERING
CERTIFICATE
This is to certify that,
Chaitanya Deshpande T187001
Kaustubh Wankhede T187003
Nikhil Patil T187010
Omkar Rane T187014
of B. Tech (E&TC) have submitted a Project Report on,
Clock Generator
The said work is completed as per the prescribed curriculum during the academic
year 2018 – 19. The report is submitted in partial fulfillment of the requirements for
the course of Digital Communication in Electronics & Telecommunication Engg.
Ashish Srivastava Dr. Debashis Adhikari
Course Faculty Dean – SEE

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Contents
Topic Page No.
1. Problem Statement 4
2. Block Diagram and Circuit Diagram
2.1 Block Diagram
2.2 Circuit Diagram
5
3. Working 10
4. Calculations 7
5. Results
5.1 Simulation Results
5.2 Hardware Implementation Results
13
6. Conclusion 17
7. References 18

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1.Problem Statement
Design a clock generator using 555 timer IC where you are supposed to design a stable
clock signal. The clock frequency is to be varied using potentiometer and the provided range for
clock frequency is 10 KHz to 50 KHz and output should be in the form of rectangular pulses. It
must include PCB design, simulation results on simulation software like multisim and final product
(PCB) must be in closed box.

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2.Block Diagram and Circuit Diagram
2.1 Block Diagram
Fig 2.2 Block diagram [1]
1) Input:
In Our circuit we have input to system is nothing but battery of 9 volts.
2) Timer IC:
The 555 timer IC is an integrated circuit used in a variety of timer, pulse generation,
and oscillator applications. The 555 can be used to provide time delays, as an
oscillator, and as a flip-flop element. Derivatives provide two or four timing circuits
in one package.
3) Potentiometer:
It is variable resistor connected between pin 7 and 2 of IC pins 555. It is connected
in voltage divider configuration. Varying potentiometer resistance changes output
frequency of clock signal.
4) Output (square Wave):
As output is square wave can be observed on Digital Storage Oscilloscope or Crystal
Oscilloscope.

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2.1 Circuit Diagram
Fig 2.1 Schematic [2]
Fig 2.1 Circuit diagram [3]

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Fig 2.2 PCB Layout [4]

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PIN Description of IC 555:
Fig 2.2 Circuit diagram [4]
1) 555 supply (pins 1 and 8)
The 555 timer can be used with a supply voltage (Vs) in the range 4.5V to 15V
(18V is the absolute maximum)
Pin1 connects to 0V.
Pin 8 connects to the positive supply +Vs.
2) 555 trigger input (pin 2)
When less than 1/3 Vs ('active low') this makes the output high (+Vs). It has a high input
impedance of at least 2M . It monitors the discharging of the timing capacitor in an astable
circuit.
3) 555 threshold input (pin 6)
When greater than 2/3 Vs ('active high') this makes the output low (0V)*. It has a high input
impedance of about 10M . It monitors the charging of the timing capacitor in astable and
monostable circuits.
4) 555 reset input (pin 4)
When less than about 0.7V this makes the output low (0V), overriding the other inputs. When
not required it should be connected to +Vs.
5) 555 control input (pin 5)
This can be used to adjust the threshold voltage which is set internally to be 2/3 Vs. Usually
this function is not required and the control input is often left unconnected. If electrical noise

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is likely to be a problem a 0.01µF capacitor can be connected between the control input and
0V to provide some protection.
6) 555 discharge (pin 7)
When the 555 output (pin 3) is low the discharge pin is connected to 0V internally. Its function
is to discharge the timing capacitor in astable and monostable circuits
7) 555 output (pin 3)
The pin 3 is the output pin of IC555. The maximum output current is 200mA, this is more than
most IC’s

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3.Working
A clock generator is an electronic oscillator that produces a timing signal for use in
synchronizing a circuit's operation. The signal can range from a simple symmetrical square wave to
more complex arrangements. A clock circuit is a circuit that can produce clock signals. These
signals are digital square waveforms, which alternate between on and off. With a 555 timer, we can
produce clock signals of varying frequencies based on the values of the external resistors and
capacitor that we choose.
For the 555 timer to work, it must be operated in Astable mode. Astable mode is a mode
in which there is no one stable state. The circuit switches constantly from low to high, which is
representative of a digital square waveform that goes constantly high to low, high to low over and
over again. So the astable mode switches constantly between HIGH and LOW states. This is in
contrast to the other 2 modes, monostable mode and Bistable mode. Monostable mode has one
state, either HIGH or LOW. Bistable mode has 2 stable states that it can be in. Like astable mode,
Bistable mode has 2 states but they're stable; in astable mode, they constantly fluctuate back and
forth between the 2 states.
A Duty cycle or power cycle is the fraction of one period in which a signal or system is active. In
this type of circuit, the duty cycle can never be 50% or lower.

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4.Calculations:
By selecting values for R1, R2 and C we can determine the period/frequency and the duty cycle.
The period is the length of time it takes for the on/off cyle to repeat itself.
In this type of circuit, the duty cycle can never be 50% or lower
R1=1k (fixed resistor)
R2= (variable resistor) or potentiometer
C=0.01 µF (Capacitor)
The frequency is the number of pulses per second. The formula to calculate the frequency of the
output voltage is:
f =
1.44
(R1+2R2)C
for typical generation of 10 KHz of frequency,
10x103
=
1.44
(1x103 +2R2)𝑋0.01𝑋10−6
R2=6700 Ω or 6.7 KΩ
The period is the time covered for one pulse. This is just the reciprocal of the frequency:
T=
1
𝑓
=0.694(R1+2R2)C
T=
1
10𝑋103=0.694(1x103
+2(6.7x103
))0.01x10-6=0.1 ms
Similarly,
50x103
=
1.44
(1x103 +2R2)𝑋0.01𝑋10−6
For to generate frequency of 50 KHz the value of R2 should be 940 Ω,
R2=940 Ω

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The period is the time covered for one pulse. This is just the reciprocal of the frequency:
T=
1
𝑓
=0.694(R1+2R2)C
T=
1
50𝑋103=0.694(1x103
+2(940))0.01x10-6=0.02 ms
The high time T1 and low time T0 can be calculated using the formulas below. Note that the period
is the sum of the high time and the low time.
For 10 KHz,
T1=0.694(R1+R2)C
T0=0.694R2C
T1=53.438 µs
T0=46.498 µs
The mark space ratio is the ratio between the high time and the low time or:
Mark Space Ratio=
𝑇1
𝑇0
=1.149253
The duty cycle is more commonly used than the mark space ratio. The formula for the duty cycle
is:
Duty Cycle=
𝑇1
𝑇
𝑋100 =
53.438 𝑋 10−6
0.1𝑋10−3 𝑋100 = 53.438
For 50 KHz,
T1=13.4636 µs
T0=6.5236 µs
Mark Space Ratio=
𝑇1
𝑇0
= 2.06471
Duty Cycle=
𝑇1
𝑇
𝑋100 =
13.4636 𝑋 10−6
0.02𝑋10−3 𝑋100 = 67.318

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5. Results
5.1 Simulation Results
Fig 4.1 Software Simulation result
Fig 4.2 Software Simulation result approximately 6.7 KΩ for 10 KHz frequency generation.

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Fig 4.3 Software Simulation result approximately 940Ω for 50 KHz frequency generation.

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5.2 Hardware Implementation and Results
Fig 4.2 Breadboard Proto-type testing
Fig 4.3 Result On DSO for 894 Hz

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Fig 4.2.1 Hardware result 10KHz
Fig 4.2.2 Hardware result 50 KHz

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6.Conclusion
In this project, we designed a clock generator using 555 IC and we come to know about the pin
configuration and other things related to 555 IC. We varied clock frequency using potentiometer
and observed the results by varying frequency range from 10 KHz to 50 KHz. We observed results
on simulation software Multisim. We designed a circuit and mounted it on PCB and observed
results on DSO and cross verified the output of DSO with simulation output. Depending on
requirement of frequency range required we can vary the capacitor’s and resistor’s value.

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7.References
[1] Variable Frequency Oscillator[website]
Available: http://www.circuitstoday.com/variable-frequency-oscillator
[2] NE555 Texas Instrument Datasheet of IC 555[Online]
[4] 555 Timer Pinout [website]
Available: http://www.learningaboutelectronics.com/Articles/555-timer-pinout.php
[5] IC555 block diagram[website]
Available:chttp://www.circuitstoday.com/wp-content/uploads/2009/09/555-Timer-IC.jpg