This document discusses the I/O ports on the 8051 microcontroller and how to interface it with an external 8255 parallel I/O chip. It describes the internal structure and functionality of the 8051's four 8-bit I/O ports P0-P3. It also covers how to configure the ports for input or output, read from and write to the ports, and how the port pins are multiplexed with other signals. The document then discusses using the 8255 chip to expand the number of available I/O ports and provides an example of simple interfacing between the 8051 and 8255 with code.
MICROPROCESSOR AND INTERFACING
8255A : ppi
8259A : pic
Basics of 8255A PPI
Different I/O mode of 8255A
Basics of 8259A PIC
Different interrupt mode of 8259A
Programming Mode of 8259A
MICROPROCESSOR AND INTERFACING
8255A : ppi
8259A : pic
Basics of 8255A PPI
Different I/O mode of 8255A
Basics of 8259A PIC
Different interrupt mode of 8259A
Programming Mode of 8259A
7.1 Data types and time delay in 8051 C
7.2 I/O programming in 8051 C
7.3 Logic operations in 8051 C
7.4 Data conversion programs in 8051 C
7.5 Accessing code ROM space in 8051 C
7.6 Data serialization using 8051 C
Complete description of AT89xxx (8051 based) microcontrollers with timers, serial communication and assembly language programming. Interfacing of some real time devices like led, sensor, and seven segment display is also covered.
2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers ports of 8051 microcontroller, Description and How to configure those ports with examples
An embedded system is closely integrated with the main system
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Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
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Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
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The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
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Class7
1. Pari vallal Kannan
Center for Integrated Circuits and Systems
University of Texas at Dallas
8051 I/O and 8255
Class 7
EE4380 Fall 2002
2. 17-Sep-02 2
Why I/O Ports
l Controllers need to get external inputs and
produce external outputs
– I/O ports serve the purpose
l 8051 has 4 built-in I/O ports
l Too many ports increase pin-count and device
cost. Too few makes it inadequate for complex
control needs
l Generally, Ports are scarce and Port
usage/allotment is an engineering decision
3. 17-Sep-02 3
8051 I/O Ports – Internal Structure
l 32 pins are allotted for 4
eight bit I/O ports
– P0, P1, P2, P3
l At power-on all are
output ports by default
l To configure any port for
input, write all 1’s (0xFF)
to the port
– Q=1, QB=0, M1=OFF,
Read_Pin asserted by
read instruction
Q
QB
D
Write
CLK
READ LATCH
READ PIN
INTERNAL
BUS
PORT
LATCH
P1.X
Vcc
Internal
Load
Pin
P1.X
M1
4. 17-Sep-02 4
8051 I/O Ports (contd.)
l Ports can be read and written to like normal registers
mov A, #55H ; can use A
mov P0, A ; write A to P0
mov P1, A
mov P2, #0AAH ; can use immediate mode
xlr P1, #0FFH ; read-modify-write (ex-or)
mov P0, #0FFH ; configure P0 for input
mov A, P0 ; read from P0
l Ports can be bit manipulated (single bit addressable)
using cpl and setb instructions
cpl P1.2 ; complement bit 2 of Port1
setb P1.3 ; set bit 3 for Port1 to 1
clr P0.0 ; clear bit 0 of Port0
5. 17-Sep-02 5
8051 I/O Ports – Pin Muxing
l Port pins are muxed with other signals
– P0 : Also carry A0:A7 and D0:D7
– P1 : dedicated
– P2 : Also carry A8:A15
– P3 : Also carry serial I/O (TxD, RxD), Timer inputs (T0, T1),
external interrupts (INT0, INT1) and read write signals (RD,
WR)
l For 8051 or DS5000, with no external memory, P0, P1
and P2 are available. For 8031, only P2 is available
l To increase the number of ports, use a Parallel port
interface chip like 8255
6. 17-Sep-02 6
8051 I/O Ports : Hardware Specs
l P0 is open drain.
– Has to be pulled high by external 10K resistors.
– Not needed if P0 is used for address lines
l P1, P2, P3 have internal pull-ups
l Port fan-out (number of devices it can drive) is limited.
– Use buffers (74LS244, 74LS245, etc) to increase drive.
– P1, P2, P3 can drive up to 4 LS-TTL inputs
– P0 fan-out is dependant on the pull-up resistor value, limited
by the max current it can sink on the output stage.
7. 17-Sep-02 7
8051 I/O Ports : Input Quirks
l Port read instructions either
– Read from the 8051 pins (“voltage”
levels on the pins)
– Read from an internal latch on the
ports
l Writing 1 to the latch
– Q=1, QB=0
– M1 off
– P1.x is available at tristate buffer
l Writing 0 to the latch
– Q=0, QB=1
– M1 ON
– Input always gets 0
– Can damage the port (M1) if P1.x is Vcc
– Use 10K resistance between switch on P1.x
and Vcc
– Or use a SPST switch connected to GND
Q
QB
D
Write
CLK
READ LATCH
READ PIN
INTERNAL
BUS
PORT
LATCH
P1.X
Vcc
Internal
Load
Pin
P1.X
M1
8. 17-Sep-02 8
Input Quirks (contd.)
l Instructions that read the pins (READ_PIN is asserted)
– mov A, Px
– jnb Px.y …
– jb Px.y …
– mov C, Px.y
l Instructions that read the latch (READ_LATCH is
asserted)
– They read the last output value and not the value on the pins
– [anl, orl, xrl] Px
– [jbc, djnz] Px.y, target
– [cpl, clr, setb] Px.y
– [inc, dec] Px
9. 17-Sep-02 9
8051 - Switch On IO Ports
l Case-1:
– Gives a logic 0 on switch
close
– Current is 0.5ma on
switch close
l Case-2:
– Gives a logic 1 on switch
close
– High current on switch
close
l Case-3:
– Can damage port if 0 is
output
Port Pin
1.Good
10K
Port Pin
2.Poor
GND
470
Port Pin
InternalPullup
GND GND
Vcc+5V
Vcc+5V
Port Pin
3.Poor
Vcc+5V
10. 17-Sep-02 10
DIP Switches on IO port
l DIP switches usually
have 8 switches
l Use the case-1 from
previous page
l Can use a Resistor
Pack, instead of
discrete resistors
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Vcc
+5V
10KResPack
SW-DIP8
GND
8051
11. 17-Sep-02 11
LED on IO Port
l Try to use current sinking
l Case-1
– LED is ON for an output of
zero
– Most LEDs drop 1.7 to 2.5
volts and need about 10ma
– Current is (5-2)/470
l Case-2
– Too much current
– Failure of Port or LED
l Case-3
– Not enough drive (1ma)
– LED too dim
l Seven Segment LEDs
– Common Anode/ Cathode
– CA preferred
– Case-1 may have LEDs of
different brightness
Vcc +5V Vcc +5V
GND
Port Pin Port Pin Port Pin
1. Good 2. Poor 3. Poor
470
Vcc
+5V
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
8051
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
8051
7segLED-CommonAnode
a
b
c
d
e
f
g
dp
CA
Vcc
+5V
330
7segLED-CommonAnode
CA
330
12. 17-Sep-02 12
8051 Interfacing with the 8255
l 8255 - Widely used I/O chip
– 40 pins
– Provides 3 eight bit ports PA, PB and PC
– Port PC can be used as two 4 bit ports PCL and PCU
– Ports have handshaking ability
– Two address lines A0,A1 and a Chip select CS
l Address space of 4 bytes
l 00b selects Port A
l 01b selects Port B
l 10b selects Port C
l 11b selects a control register
13. 17-Sep-02 13
8255 Functional Diagram
l CS is used to interface with 8051
l If CS is generated from lets say
Address lines A15:A12 as
follows,
A15:A12 = 1000
l Base address of 8255 is
– 1000 xxxx xxxx xx00b
– 8000H
l Address of the registers
– PA = 8000H
– PB = 8001H
– PC = 8002H
– CR = 8003H
8
2
5
5
PA
PB
PC
CS RESET
D7-D0
RD
WR
A0
A1
14. 17-Sep-02 14
8255 Operating Modes
l Mode 0 : Simple I/O
– Any of A, B, CL and CU can be programmed as input or output
l Mode 1: I/O with Handshake
– A and B can be used for I/O
– C provides the handshake signals
l Mode 2: Bi-directional with handshake
– A is bi-directional with C providing handshake signals
– B is simple I/O (mode-0) or handshake I/O (mode-1)
l BSR (Bit Set Reset) Mode
– C alone is available for bit mode access
15. 17-Sep-02 15
8255 Configuration
l Configured by writing a control-word in CR register
l CR definition
– D7 : 1àI/O mode, 0àBSR
– D6,D5 : Mode selection for A and CU
l 00àMode0, 01àMode1, 1xàMode2
– D4 : Port A control
l 1àA input, 0àA output
– D3 : Port CU control
l 1àCU input, 0àCU output
– D2 : Port B Mode selection
l 0àB is in mode 0, 1àB is in mode 1
– D1 : Port B control
l 1àB input, 0àB output
– D0 : Port CL control
l 1àCL input, 0àCL output
l Refer to 8255 datasheet for additional options
16. 17-Sep-02 16
8255 Usage: Simple Example
l 8255 memory mapped to 8051 at address 8000H base
– PA = 8000H, PB = 8001H, PC = 8002H, CR = 8003H
l Control word for all ports as outputs in mode0
– CR : 1000 0000b = 80H
l Code snippet
test: mov A, #80H ; control word
mov DPTR, #8003H ; address of CR
movx @DPTR, A ; write control word
mov A, #55h ; will try to write 55 and AA alternatively
repeat: mov DPTR, #8000H ; address of PA
movx @DPTR, A ; write 55H to PA
inc DPTR ; now DPTR points to PB
movx @DPTR, A ; write 55H to PB
inc DPTR ; now DPTR points to PC
movx @DPTR, A ; write 55H to PC
cpl A ; toggle A (55àAA, AAà55)
acall MY_DELAY ; small delay subroutine
sjmp repeat ; for (1)