This document discusses address mapping techniques for interfacing external devices to an 8051 microcontroller. It explains that external devices can be mapped into the microcontroller's address space and accessed like memory, or interfaced through I/O ports. The document provides examples of generating chip enable signals to map devices at specific memory addresses and discusses using decoders like the 74138 for address decoding. It also covers interfacing external memory, non-memory devices, and a case study of a sample 8051 system with external memory and a serial interface.
The word comes from the combination micro and processor.
Processor means a device that processes whatever. In this context processor means a device that processes numbers, specifically binary numbers, 0’s and 1’s.
To process means to manipulate. It is a general term that describes all manipulation. Again in this content, it means to perform certain operations on the numbers that depend on the microprocessor’s design.
The word comes from the combination micro and processor.
Processor means a device that processes whatever. In this context processor means a device that processes numbers, specifically binary numbers, 0’s and 1’s.
To process means to manipulate. It is a general term that describes all manipulation. Again in this content, it means to perform certain operations on the numbers that depend on the microprocessor’s design.
7.1 Data types and time delay in 8051 C
7.2 I/O programming in 8051 C
7.3 Logic operations in 8051 C
7.4 Data conversion programs in 8051 C
7.5 Accessing code ROM space in 8051 C
7.6 Data serialization using 8051 C
8085 Microprocessor, Features/Characteristics of 8085, Communication between Microprocessor & Memory, 8085 Programming Model, 8085 Registers, Flag Register, General Purpose Register, Special Purpose Register, Stack Pointer, Program Counter, Interrupts, Control Unit, Architecture/Block Diagram of 8085 & its explanation, Pin diagram of 8085
An embedded system is closely integrated with the main system
It may not interact directly with the environment
For example – A microcomputer in a car ignition control
This presentation discusses the internal architecture of Intel 8051. It discusses basic families of 8051, the programmer view, register sets and memory organiszation of 8051
It is a central processing unit etched on a single chip.A single integrated circuit has all the functional components of a cpu namely ALU,CONTROL UNIT & REGISTERS
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
1. Pari vallal Kannan
Center for Integrated Circuits and Systems
University of Texas at Dallas
8051 Interfacing: Address Map
Generation
EE4380 Fall02
Class 6
2. 12-Sep-02 2
8051 Interfacing
l Address Mapping
– Use address bus and data bus
– Interfaced device show up as memory locations from the
processor
– They use up some of the address space
– Memories, displays etc
l I/O Mapping
– Connect the devices to the I/O Ports of the processor
– Don’t use up address space
– Sensors, pushbuttons, LCDs, motors, LEDs etc
3. 12-Sep-02 3
8051 – Address Generator
l Address Generator is a piece
of hardware that produces
unique addresses to each
interfaced device
l Each Interfaced Device can
use up 1 or more locations
from the address space of the
processor
– Memories typically use up in
Kilobytes (2K, 4K, 8K etc)
– Other devices typically use a
few (<16) addresses
l Addresses of devices should
not overlap
8051
A[15:0]
Addr. Gen
Device 1
Device 2
Device 3
CE
CE
CE
f1
f2
f3
D[7:0]
D[7:0]
D[7:0]
D[7:0]
A[15:0]
A[15:0]
A[15:0]
4. 12-Sep-02 4
What is needed ?
l Need to know the
following for all the
devices before address
generator can be
designed
– Base address of each
device
l Where it starts in the
address map
– Size of the device
l How much of the address
space it uses up
Code Memory Data Memory
0x0000
0x4000
0x1000
0x5000
RAM1 32K
0x0000
0x8000
0xF000
LCD 8b
LEd 2b
Code RAM 4K
Code ROM1 4K
5. 12-Sep-02 5
Example –1 : 2K Memory at 0x0000
l Pins : address - A10 to A0, Data – D7 to D0,
_RD, _WR, _CE
l Base address = 0x0000
l Size = 2k (2 *1024 = 2048 bytes = 0x0800)
l Address Map occupancy
– 0x0000 to 0x07FF that is,
– 0000 - 0000 - 0000 - 0000 binary to
– 0000 - 0111 - 1111 - 1111 binary
l 11 lowest address bits A10 to A0 have to be
connected to the address pins on the memory
6. 12-Sep-02 6
Example –1 : (contd.)
l Unused address bits are
– A15 to A11
l Base address is 0x0000
l CE has to be generated
if all the unused address
bits are logic-0
– CE is active low
l _CE = A15 + A14 + A13
+ A12 + A11
l Then connect _RD and
_WR
0
1
1
1
1
1
0
1
X
X
X
X
0
X
1
X
X
X
0
X
X
1
X
X
0
X
X
X
1
X
0
X
X
X
X
1
_CEA11A12A13A14A15
Truth-Table for CE
7. 12-Sep-02 7
Ex-2: Same Memory at 0x4000
l Base address is 0x4000
– 0100 0000 0000 0000
l Size is 2K
l Unused address bits
– A15 to A11
l CE has to be generated
as per the truth-table
l Expression is
1
0
1
1
1
1
1
1
1
X
0
0
1
0
1
X
0
X
X
1
1
X
0
X
X
X
X
on
0
1
1
1
1
1
so
X
0
X
X
X
X
and
_CEA11A12A13A14A15
1112131415_ AAAAACE ••••=
8. 12-Sep-02 8
(In)Complete Addressing
l Complete addressing:
– Use all unused address bits to generate CE
l Incomplete addressing
– Use a sub-set of the unused address bits
– Used to reduce the address generator complexity
– Produces address aliases (same device at multiple addresses)
l Example
– 2K memory at 0x0000, we used A15 to A11
– Instead just connect A11 to _CE
– Same 2K memory device will then be aliased for all values of
A15 to A12
l 0x0000, 0x1000, 0x2000, 0x3000, …. , 0xF000
– Address generator became very simple, but we lost a lot of
address space
9. 12-Sep-02 9
74138 Decoder for Address Gen.
l 3 to 8 decoder, available in a single
DIP package.
l Takes 3 address lines and
generates complete addressing
among those
l Example
– Connect A15, A14, A13 to the
decoder inputs
– Decoder outputs give base
addresses for
l 0x0000, 0x2000, 0x4000, 0x6000,
0x8000, 0xA000, 0xC000, 0xE000
l For more complicated address
decoding use programmable
devices like PALs, PLDs or FPGAs
C
B
A
G2
G1
Y0
Y1
Y2
Y7
74LS138
A15
A14
A13
GND
Vcc
10. 12-Sep-02 10
External (pure) Code Memory
l Could be RAM or ROM
l Address generation as per standard procedure
l Connect _PSEN to the _OE of the memory
device
l _RD and _WR are ignored
– Don’t connect these 8051 pins to the memory
device
l Connect Data bits D7-D0 of the memory and
the 8051
11. 12-Sep-02 11
External (pure) Data Memory
l Could be RAM or ROM
l Address generation as per standard procedure
l Connect _RD from the 8051 to OE of the
memory
l Connect _WR from the 8051 to WR of the
memory
l Ignore _PSEN
l Connect Data bits D7-D0 of the memory and
the 8051
12. 12-Sep-02 12
External Code + Data Memory
l Could be RAM or ROM
l Address generation as per standard procedure
l Logically AND _PSEN and _RD and then
connect to the OE of the memory
l Connect _WR from the 8051 to WR of the
memory
l Connect Data bits D7-D0 of the memory and
the 8051
13. 12-Sep-02 13
External Non-Memory Devices
l Same procedure as for interfacing memory
l Only difference is that these devices have
smaller sizes and use lesser portions of the
address space
l Example:
– 8 LEDS connected to a 8bit latch. The latch is
address mapped to 0xF000. Size is 1byte
– 8255 I/O device memory mapped at 0xD000. Size is
4 bytes
15. 12-Sep-02 15
Case study – Sample 8051 System
l 8031 based
– No on-chip ROM, 128 bytes on-chip RAM, 18.432MHz oscillator,
74HC373 based ADBUS demuxer
– 8Kx8 external code memory in 28C64 EEPROM
– Code memory at 0x0000
– 32Kx8 external code+data overlapped in 62256 SRAM.
– SRAM mapped at 0x8000
l SRAM and EEPROM share code memory space. So
decoding needed.
– A15 line is used for the purpose
– A15 = 0 è EEPROM is selected (hence 0x0000)
– A15 = 1 è SRAM is selected (hence 0x8000)
l RS232 serial interface available for PC communication
l Monitor programs available
16. 12-Sep-02 16
Reverse Engineering
l Given a system with little or no docs, determine
the function, schematic, etc
l Vendors provide poor support.
l Reverse Engineering is fun !
l Usually No schematics are available
l Software is also undocumented !
l On-chip code could be copy protected !!
17. 12-Sep-02 17
Next Class
l 8051 I/O Mapped interfacing
l 8051 and the 8255 I/O device
l Example – Interfacing a character LCD