8051 Microcontrollers Course Content

8051 Microcontrollers
Gaurav Verma
Assistant Professor
Department of Electronics and Communication Engineering
Jaypee Institute of Information and Technology
Sector-62, Noida, Uttar Pradesh, India
1 copyright@gauravverma

Course Content cont…
2. INTRODUCTION TO MICROPROCESSORS AND MICROCONTROLLERS
1. Introduction
1.1 Microprocessor Versus Microcontrollers
1.2 Microcontrollers for Embedded Systems
1.3 Embedded Versus External Memory Devices
1.4 CISC Versus RISC Processors
1.5 Harvard Versus Von-Neumann architecture
1.6 Superscalar Versus VLIW architecture
2. 8051/8031/8052 Microcontroller
2.1 Basic architecture
2.2 Pin configuration
2.3 Memory organization (registers and i/o ports)
2.4 Assembly language programming ( addressing modes and instruction set)
2.5 Timers and Interrupts
2.6 Serial Communication

8051 Basic Component
y 4K bytes internal ROM
yy 128 bytes internal RAM
y Four 8-bit I/O ports (P0 - P3).
yy Two 16-bit timers/counters
y One serial interface
CPU RAM ROM
I/O
Port Timer
Serial
COM
Port
A single chip
Microcontroller

Block Diagram
External Interrupts
Interrupt
Control
ROM
I t t 4k
128 b t Ti 1
Timer Timer 2
bytes
RAM
CPU
OSC Bus 4 P t S i l
Control I/O Ports Serial
P0 P2 P1 P3 TXD RXD
Addr/Data 4 copyright@gauravverma

Other 8051 featurs
y only 1 On chip oscillator (external crystal)
y 6 interrupt sources (2 external , 3 internal, Reset)
y 64K external code (program) memory(only read)PSEN
y 64K external data memory(can be read and write) by RD,WR
yy Code memory is selectable by EA (internal or external)
y We may have External memory as data and code

Three criteria in Choosing a Microcontroller
y meeting g the computing needs of the task efficiently and cost
effectively
y speed, the amount of ROM and RAM, the number of I/O ports and timers,
size, packaging, power consumption
y easy to upgrade
y cost per unit
y availability of software development tools
y assemblers, debuggers, C compilers, emulator, simulator, technical support
y wide availability and reliable sources of the microcontrollers

Comparison of the 8051 Family Members
y ROM type
y 8031 no ROM
y 80xx mask ROM
yy 87xx EPROM
y 89xx Flash EEPROM
y 89xx
yy 8951
y 8952
y 8953
y 8955
y 898252
y 891051
y 892051
y Example (AT89C5112PC,AT89LV51,AT89S51, AT89S2051)
y AT= ATMEL(Manufacture)
y C = CMOS technology
y LV= Low Power(3.0v)
y 12= operating frequency
y P=Package type (DIP or QFP) & C= Commercial version 7
copyright@gauravverma

Comparison of the 8051 Family Members
89XX ROM RAM Timer Int
Source
IO pin Other
8951 4k 128 2 6 32 -
8952 8k 256 3 8 32 -
8953 12k 256 3 9 32 WD
8955 20k 256 3 8 32 WD
898252 8k 256 3 9 32 ISP
891051 1k 64 1 3 16 AC
892051 2k 128 2 6 16 AC
WD: Watch Dog Timer
AC: Analog Comparator
ISP: In System Programable

8051 Internal Block Diagram

8051 P1.0 1 40 Vcc
Pin Out 23
45
39
38
37
36
P1.1
P1.2
P1.3
P1 4
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
5 P0 3(AD3)
6
35
7
34
8
33
P1.4
P1.5
P1.6
P1.7
P0.3(P0.4(AD4)
P0.5(AD5)
8051
P0.6(AD6) 9
32
10
31
11
30
12
29
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
(8031)
(8751) 13
14
15
16
28
27
26
25
(INT1)P3.3
(T0)P3.4
(T1)P3.5
P3.6 P2.4((WR)P3 6
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2 4(A12)
(8951)
17
18
19
24
23
22
(RD)P3.7
XTAL2
XTAL1
P2.3(A11)
P2.2(A10)
P2.1(A9)
GND 20 21 P2.0(A8)

IMPORTANT PINS (IO Ports)
y One of the most useful features of the 8051 is that it contains
four I/O ports (P0 - P3)
y Port 0 （pins 32-39）：P0（P0.0～P0.7）
y 8-bit R/W - General Purpose I/O
y Or acts as a multiplexed low byte address and data bus for external memory design
y Port 1 （pins 1-8）：P1（P1.0～P1.7）
y Only 8-bit R/W - General Purpose I/O
y Port 2 （pins 21-28）：P2（P2.0～P2.7）
y 8-bit R/W - General Purpose I/O
y Or high byte of the address bus for external memory design
y Port 3 （pins 10-17）：P3（P3.0～P3.7）
y General Purpose I/O
y if not using any of the internal g y peripherals (timers) or external interrupts.
y Each port can be used as input or output (bi-directional)

Port 3 Alternate Functions

CONTROL PINS
y PSEN (out): Program Store Enable, the read signal for external
program memory (active low).
y ALE (out): Address Latch Enable, to latch address outputs at
Port0 and Port2
y EA (in): External Access Enable, active low to access external
program memory locations 0 to 64K
y XTAL1 & XTAL2: Crystal inputs for internal oscillator.
y RESET (in): Require 2 machine cycle for proper reset.

XTAL Connection to 8051
y Using a quartz crystal oscillator
y We can observe the frequency on the XTAL2 pin.
C2
30pF
C1
XTAL2
30pF
XTAL1
p
GND

Pins of 8051
y /EA（pin 31）：external access
y There is no on-chip ROM in 8031 and 8032 .
y The /EA pin is connected to GND to indicate the code is
stored externally.
y /PSEN ＆ ALE are used for external ROM.
y For 8051, /EA pin is connected to Vcc.
yy “/” means active low.
y /PSEN（pin 29）：program store enable
y This is an output pin and is connected to the OE pin of the
ROM.

Pins of 8051
y ALE（pin 30）：address latch enable
y It is an output pin and is active high.
y 8051 port 0 provides both address and data.
y The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of the
74LS373 latch.

External code memory
WR
PSEN OE
ALE 74LS373
G CS
RD
D P0.0
P0.7
A0
A7
D0
D7
P2.0
P2.7
A8
A15
EA
8051 ROM 17 copyright@gauravverma

External data memory
WR WR
PSEN
ALE 74LS373
RD
G CS
RD
D P0.0
P0.7
A0
A7
D0
D7
P2.0
P2.7
A8
A15
EA
8051 RAM 18 copyright@gauravverma

On-Chip Memory Internal RAM

RESET Value of Some 8051 Registers:
Register Reset Value
PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero

Hardware Structure of I/O Pin
Vcc
Load(L1)
Read latch
TB2
Internal CPU D Q
bus
P1.X
P1.X pin
Write to latch Clk Q M1
Read pin
TB1

Hardware Structure of I/O Pin
y Each pin of I/O ports
y Internally connected to CPU bus
y A D latch store the value of this pin
y Write to latch＝1：write data into the D latch
yy 2 Tri-state buffer：：
y TB1: controlled by “Read pin”
y Read pin＝1：really read the data present at the pin
y TB2: controlled by “Read latch”
y Read latch＝1：read value from internal latch
y A transistor M1 gate
y Gate=0: open
y Gate=1: close

Writing “1” to Output Pin P1.X
Vcc
Load(L1)
Read latch
2. pin is
TB2
1. write a 1 to the pin Vcc
D Q
Internal CPU
bus
output P1.X
1
P1 P1.X p
pin
Write to latch Clk Q
0 output 1
M1
Read pin
TB1

Writing “0” to Output Pin P1.X
Vcc
Load(L1)
Read latch
2. output pin is
TB2
1. write a 0 to the pin ground
D Q
Internal CPU
bus
P1.X
0
P1 P1.X p
pin
Write to latch Clk Q
1 output 0
M1
Read pin
TB1

Reading “High” at Input Pin
Read latch 2. MOV A,P1
Vcc
Load(L1)
external pin=High
1. write a 1 to the pin MOV
P1,#0FFH
TB2
Internal CPU bus D Q P1.X pin
P1.X
1 1
Write to latch Clk Q M1 0
Read pin
3 Read 1 Read 0
TB1
3. pin=latch=Write to latch=1

Reading “Low” at Input Pin
Vcc
Load(L1)
Read latch
2. MOV A,P1
1. write a 1 to the pin external pin=Low
MOV P1,#0FFH
TB2
Internal CPU bus D Q P1.X pin
P1.X
,
1
0
0
Write to latch Clk Q M1 Read pin
3. Read pin=1 Read latch=0
TB1
8051 IC
Write to latch=1

8051 Port 3 Bit Latches and I/O Buffers

Port 0 with Pull-Up Resistors
Vcc
10 K
P0.0
P0.1
P0.2
P0 3
DS5000
8751
Port
P0.3
P0.4
P0.5
P0.6
P0 7
8951 0
P0.7

8051 Software Overview
1.Internal RAM Organization
2.Addressing Modes
3.Instruction Set
4.Programming

Registers
1F
Bank 3
Four Register Banks
bank R0-R7
18
17
Each an has 7
Selectable by psw.2,3
10
0F
Bank 2
08
07
R7
Bank 1
06
05
04
03
02
01
R6
R5
R4
R3
R2
R1
Bank 0
00
R0

Bit Addressable Memory
20h – 2Fh (16 locations X
8-bits = 128 bits)
Bit addressing:
mov C, 67h
or
mov C, 2Ch.7
32

Special Function Registers
33

8051 Addressing Modes
y The CPU can access data in various
ways, which are called addressing
modes.
1.Immediate
2.Register
3.Direct
4.Register indirect
5.External Direct
[label : ] mnemonic [operands] [;comment]
34

Addressing Modes
Immediate Mode – specify data by its value
mov A, #0 ;put 0 in the accumulator
;A = 00000000
mov R4, #11h ;put 11hex in the R4 register
;R4 = 00010001
mov B, #11 ;put 11 decimal in b register
;B = 00001011
mov DPTR,#7521h ;put 7521 hex in DPTR
;DPTR = 0111010100100001
MOV DPL,#21H
MOV DPH, #75

Addressing Modes
Register Addressing – Used only registers as operands.
MOV R0,A
MOV A,R7
ADD A,R4
ADD A,R7
MOV DPTR,#25F5H
MOV R5,DPL
MOV R6,DPH
Note: MOV R4,R7 is incorrect

Addressing Modes
Direct Mode – specify data by its 8-bit address
Usually for 30h-7Fh of RAM
Mov a, 70h ; copy contents of RAM at 70h to a
Mov R0,40h ; copy contents of RAM at 70h to a
Mov 56h,a ; put contents of a at 56h to a
Mov 0D0h,a ; put contents of a into PSW

Addressing Modes
Direct Mode – play with R0-R7 by direct address
MOV A,4 ≡≡ MOV A,R4
MOV A,7 ≡ MOV A,R7
MOV 7,6 ≡ MOV R7,R6 (but this syntax is incorrect)
MOV R2,#5 ;Put 5 in R2
MOV R2,5 ;Put content of RAM at 5 in R2

Addressing Modes
Register Indirect – the address of the source or destination is specified
in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0 ; use register bank 0
mov r0, #3Ch
mov @r0, #3 ; memory at 3C gets #3
; M[3C] Å 3
Uses DPTR register for 16-bit addresses:
mov dptr ; Å 9000h
3C
r0
3
dptr, #9000h dptr 3C
movx a, @dptr ; a Å M[9000]
N t th t 9000 i dd i t l
9000
acc
xx
Note that is an address in external memory
dptr 9000

Addressing Modes
Register Indexed Mode – source or destination address is
the sum of the base address and the accumulator(Index)
y Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5
movc a, @a + dptr ;a Å M[4005]

Addressing Modes
Register Indexed Mode continue
y Base address can be DPTR or PC
ORG 1000h
1000 mov a, #5
1002 movc a, @a + PC ;a Å M[1008]
PC
1003 Nop
y MOVC only can read internal or external (if connected) code
memory.

Overview of ISA
y Data transfer instructions
y Program flow instructions (Jump,Call,Ret)
y Data processing (arithmetic and logic)
y Machine Control & Stack (Push, Pop)

Data Transfer Instructions
yy MOV dest, source dest ÅÅsource
y Dest & sourceÆÆregister(Rn)*, direct address(RAM Locations),
Indirect add. (@Ri)*, SFRs (A, Ports),
Immediate data (#20h)^.
y *either source or destination.
y ^only destination.
y Exchange instructions
XCH a, byte ;exchange accumulator and byte
XCHD a, byte ;exchange low nibbles of
;accumulator and byte

Exchange Instructions
two way data transfer
XCH a, 30h ; a ÅÆ M[30]
XCH a, R0 ; a ÅÆ R0
XCH a, @R0 ; a ÅÅÆÆ M[R0]
XCHD a, R0 ; exchange “digit”
a[7..4] a[3..0] R0[7..4] R0[3..0]
Only 4 bits exchanged

Bit-Oriented Data Transfer
y transfers between individual bits.
yy Carry flag (C) (bit 7 in the PSW) is used as a single-bit accumulator
y RAM bits in addresses 20-2F are bit addressable
mov C, P0.0
mov C, 67h
mov C, 2Ch.7

SFRs that are Bit Addressable
SFRs with addresses ending
in 0 or 8 are bit-addressable.
(80, 88, 90, 98, etc)
Notice that all 4 parallel I/O
ports are bit addressable.

Example
y Note: Keep in mind code optimization while
writing the program.

Bit Logic Operations
y Some logic operations can be used with single bit operands
ANL C, bit
ORL C, bit
CLR C
CLR bit
CPL C
CPL bit
SETB C
SETB bit
y “bit” can be any of the bit-addressable RAM locations or SFRs.

Program Status Word
C AC F0 RS1 RS0 OV F1 P
Carry
A ili C
Parity
Register Bank Select
Auxiliary Carry
User Flag 0
User Flag 1
Overflow

Program Flow Control
‰ Unconditional jumps (“go to”)
‰ Conditional jumps
‰ Call and return

Unconditional Jumps
y SJMP <rel addr>
Short jump, relative address is 8-bit 2’s
complement number, so jump can be up to 127
locations forward, or 128 locations back.
y LJMP <address 16>
Long jump range is 64kb
y AJMP <address 11>
Absolute jump to anywhere within 2K block of
program memory

Infinite Loops
Start: mov C, p3.7
mov p1.6, C
sjmp Start
Microcontroller application programs are always in infinite loops!

Re-locatable Code
Memory specific NOT Re-locatable (machine code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
ljmp Start
end
Re-locatable (machine code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
sjmp Start
end

Conditional Jump
y These instructions cause a jump to occur only if a condition is true.
Otherwise, program execution continues with the next instruction.
loop: mov a, P1
jz loop ; if a=0, goto loop,
; else goto next instruction
mov b, a
y There is no zero flag (z)
y Content of A checked for zero on time

Conditional jumps
Mnemonic Description
JZ <rel addr> Jump if a = 0
JNZ <rel addr> Jump if a != 0
JC <rel addr> Jump if C = 1
JNC <rel addr> Jump if C != 1
JB <bit>, <rel addr> Jump if bit = 1
JNB <bit>,<rel addr> Jump if bit != 1
JBC <bir>, <rel addr> Jump if bit =1, &clear
bit
CJNE A, direct, <rel addr> Compare A and memory,
jump if not equal

More Conditional Jumps
CJNE A, #data <rel addr> Compare A and data, jump
if not equal
CJNE Rn, #data <rel addr> Compare Rn and data,
jump if not equal
CJNE @Rn, #data <rel addr> Compare Rn and memory,
jump if not equal
DJNZ Rn, <rel addr> Decrement Rn and then
jump if not zero
DJNZ direct, <rel addr> Decrement memory and
then jump if not zero

Example: Conditional Jumps
if (a = 0) is true
send a 0 to LED
else
send a 1 to LED
jz _
led_off
Setb P1.6
sjmp skipover
led_off: clr P1.6
mov A, P0
skipover: end

Program on Conditional Jumps

Iterative Loops
For A = 0 to 4 do
{
For A = 4 to 0 do
{
…
…
…
}
…
}
clr a
l
mov R0, #4
loop: ... l
...
inc loop: ...
...
a
djnz R0 loop
cjne a, #4, loop
R0, 59

Iterative Loops(examples)
mov a,#50h
mov b #mov a,#25h
b,#00h
mov r0 #10h
cjne a,#50h,next
mov b,#01h
next: r0,#mov r2,#5
Again: mov @ro,a
nop
inc r0
end
djnz r2,again
end
mov a #mov a,#0h
mov r4,#12h
Back: add a,#05
a,#0aah
mov b,#10h
Back1:mov r6,#50
Back2:cpl a
,#
djnz r4,back
mov r5,a
end
ac :cp djnz r6,back2
djnz b,back1
end

Call and Return
y Call is similar to a jump, but
y Call pushes PC on stack before branching
acall <address ll> ; stack Å PC
; PC Å address 11 bit
lcall <address 16> ; stack Å PC
; PC ÅÅ address 16 bit

Return
y Return is also similar to a jump, but
y Return instruction pops PC from stack to get address to jump
to
ret ; PC Å stack

Subroutines
M i
call to the subroutine
Main: ...
acall sublabel
...
...
sublabel: ...
...
ret
the subroutine

Example of LED Blinking
org 0000h
Loop: clr P1.0
acall Delay
setb P1.0
acall Delay
sjmp Loop
Delay:
....
....
RET
end

Concept of Machine Cycle
y Time Period of 1 clock cycle = 1/f = 1/12 microsec.
o 1 T State = 2 clock cycles
y Time Period of 1 T State = 2 x 1/12 = 1/6 microsec.
o 1 Machine Cycle = 6 T States
y Time Period of 1 Machine Cycle = 6 x 1/6 = 1 microsec.

Machine cycle
Find the machine cycle for
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 μμs
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 μs

Example of delay
mov a,#0aah D l 2
back1:mov p0,a
lcall delay1
cpl Delay2:
mov r6,#0ffh ;1cycle
back1: mov r7,#0ffh ;1cycle
a
Here: r7 ;2cycle
sjmp back1
Delay1:mov r0,#0ffh;1cycle
Here: ;2cycle
djnz r7,here djnz r6,back1;2cycle
ret ;2cycle
djnz r0,here end
ret ;2cycle
end
Delay=1+255*2+2
=513 machine cycle
Delay=1+(1+255*2+2)*255+2
=130818 machine cycle
1 machine cycle = 1 microseconds (if crystal frequency is
67 taken as 12 Mhz)

Long delay Example
GREEN_LED equ P1.0
org 0000h
ljmp reset service
Main
org 0100h
Main: clr GREEN_LED main program
Again: acall Delay
setb GREEN_LED
sjmp Again
Delay: mov R7, #02
Loop1: mov R6, #00h
Loop0: mov R5, #00h
djnz R5, $
djnz R6, Loop0
subroutine
j , p
djnz R7, Loop1
ret
END

Example (duty cycle 50%)
org 0000h
back: cpl p1.2
acall delay
sjmp back
end
org 0000h
back: setb p1.2
acall delay
Clr p1.2
acall delay
sjmp back
end 69 copyright@gauravverma

p
Example (duty cycle 60%)
org 0000h
b k back: setb b 1 p1.2
2
acall delay
acall delay
Clr p1.2
acall delay
sjmp back
end

MOD-9 Counter using 7 seg. display

MOD-9 Counter – Data Values
Binary Pattern for different Segments Data in (Hex)
dp g f e d c b a Data Number
1 1 0 0 0 0 0 0 #0C0h 0
1 1 1 1 1 0 0 1 #0F9h 1
1 0 1 0 0 1 0 0 #0A4h 2
1 0 1 1 0 0 0 0 #0B0h 3
1 0 0 1 1 0 0 1 #99h 4
1 0 0 1 0 0 1 0 #92h 5
1 0 0 0 0 0 1 0 #82h 6
1 1 1 1 1 0 0 0 #0F8h 7
1 0 0 0 0 0 0 0 #80h 8
1 0 0 1 0 0 0 0 #90h 9

MOD-9 Counter
Org 0000h
Loop: Mov P1, #0C0h
Acall Delay
Mov P1, #0F9h
Acall Delay
Mov P1, #0A4h
Acall Delay
Mov P1, #0B0h
Acall Delay
.
.
.
.
Mov P1, #90h
Acall Delay
Sjmp Loop
Delay: .
73
.
RET
END

Sensor Interface
Org 0000h
Main: Setb P3.0
Mov C, P3.0
JC OFF
Clr P1.0 ; LED GLOW
Sjmp Main
OFF: Setb P1.0 ; LED OFF
Sjmp Main
End
74

Data Processing Instructions
Arithmetic Instructions
Logic Instructions

y Add
y Subtract
y Increment
y Decrement
y Multiply
y Divide
y Decimal adjust

ADD A, byte add A to byte, put result in A
ADDC A, byte add with carry
SUBB A, byte subtract with borrow
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
MUL AB multiply accumulator by b register
DIV AB divide accumulator by b register
DA A decimal adjust the accumulator

ADD Instructions
add a, byte ; a Å a + byte
addc a, byte ; a ÅÅ a + byte + C
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not
from bit 6, or visa versa.

ADD Examples
mov a, #3Fh y What is the value of the C,
AC fl f h d
,
add a, #D3h
AC, OV flags after the second
instruction is executed?
0011 1111
1101 0011
0001 0010
C = 1
AC = 1
OV = 0

Addition Example
; Computes Z = X + Y
; Adds values at locations 78h and 79h and puts them in 7Ah
X equ 78h
Y equ 79h
Z equ 7Ah
org 0000h
mov a, X
add a, Y
mov Z, a
end

The 16-bit ADD example
; Computes DPTR = X + Y (X,Y,DPTR are 16 bit)
;---------------------------------------------------------
X = 1278h
Y = 137Ah
org 0000h
mov R0, #78h
mov a, #7Ah
add a, R0
mov DPL, a
mov R0, #12h
mov a, # 13h
addc a, R0
mov DPH, a
end

Signed Addition and Overflow
0111 1111 (positive 127)
2’s complement: 0111 0011 (positive 115)
1111 0010 (overflow
cannot represent 242 in 8
bits 2’s complement)
p
0000 0000 00 0
… p
0111 1111 7F 127
1000 0000 80 -128 1000 1111 (negative 113)
1101 0011 (negative 45)
…
1111 1111 FF -1
g
0110 0010 (overflow)
0011 1111 (positive)
1101 0011 (negative)
0001 0010 (never overflows)

Subtract
SUBB A, byte subtract with borrow
Example:
SUBB A, #0x4F ;A Å A – 4F – C
Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.
Example:
Clr c
SUBB A, #0x4F ;A Å A – 4F

Increment and Decrement
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
y The increment and decrement instructions do NOT
affect the C flag.
y Notice we can only INCREMENT the data pointer,
not decrement.

Example: Increment 16-bit Word
y Assume 16-bit word in R3:R2
mov a, r2
add a, #1 ; use add rather than increment to affect C
mov r2, a
mov a, r3
addc a, #0 ; add C to most significant byte
mov r3, a

Multiply
When multiplying two 8-bit numbers, the size of the maximum
product is 16-bits
FF x FF = FE01
(255 x 255 = 65025)
MUL AB ; BA Å A * B
Note : B gets the High byte
A gets the Low byte

Division
yy Integer Division
DIV AB ; divide A by B
A Å Quotient(A/B)
B Å Remainder(A/B)
OV - used to indicate a divide by zero condition.
C – set to zero

Decimal Adjust
DA a ; decimal adjust a
y Used to facilitate BCD addition.
y Adds “6” to either high or low nibble after an
addition to create a valid BCD number.
Example:
mov a, #23h
mov b, #29h
add a, b ; a Å 23h + 29h = 4Ch (wanted 52)
DA a ; a ÅÅ a + 6 = 52

copyright@gauravverma Program
y Write a program to copy the value 55H into RAM memory locations
40H to 41H using (a) direct addressing mode, (b) register indirect
addressing mode without a loop, and (c) with a loop.
89

Logic Instructions
‰ Bitwise logic operations
™ (AND, OR, XOR, NOT)
‰ Clear
‰ Rotate
‰ Swap
yy Logic instructions do NOT affect the
flags in PSW

Bitwise Logic
ANL Î AND Examples:
00001111
ORL Î OR
XRL Î XOR
ANL 10101100
00001100
CPL Î Complement 00001111
ORL 10101100
10101111
00001111
XRL 10101100
10100011
CPL
10101100
01010011

Address Modes with Logic
ANL – AND
a, byte
[direct, reg. indirect, reg,
immediate]
ORL – OR
XRL – eXclusive oR
byte, a
[direct]
byte, #constant
a ex: cpl a CPL – Complement

Uses of Logic Instructions
y Force individual bits low, without affecting other bits.
anl PSW, #0E7h ;PSW AND 11100111
y Force individual bits high.
orl PSW, #18h ;PSW OR 00011000
y Complement individual bits
xrl P1, #40h ;P1 XRL 01000000

Other Logic Instructions
CLR - clear
RL – rotate left
RLC – rotate left through Carry
RR – rotate right
RRC – rotate right through Carry
SWAP – swap accumulator nibbles

CLR ( Set all bits to 0)
CLR A
CLR byte (direct mode)
CLR Ri (register mode)
CLR @Ri (register indirect mode)

Rotate
y Rotate instructions operate only on a
RL a
Mov a,#0xF0 ; aÅÅ 11110000
RR a ; aÅ 11100001
RR a
Mov a,#0xF0 ; aÅ 11110000
RR a ; aÅÅ 01111000

Rotate through Carry
RRC a
C
mov a, #0A9h ; a Å A9
add a, #14h ; a ÅÅ BD (10111101), CÅÅ0
rrc a ; a Å 01011110, CÅ1
RLC a C
mov a, #3ch ; a Å 3ch(00111100)
setb c ; c Å 1
rlc a ; a Å 01111001, CÅ1

Rotate and Multiplication/Division
y Note that a shift left is the same as multiplying by 2, shift
right is divide by 2
mov a, #3 ; AÅÅ 00000011 (3)
clr C ; CÅ 0
rlc a ; AÅÅ 00000110 (6)
rlc a ; AÅ 00001100 (12)
rrc a ; AÅ 00000110 (6)

Swap
SWAP a
mov a, #72h ; a Å 27h
swap a ; a Å 27h

Instructions that Affect PSW
bits

Stacks
push
pop
stack pointer
stack
By default SPÆÆ 07h Concept of LIFO

Stack
y Stack-oriented data transfer
yy Only one operand (direct addressing)
y SP is other operand – register indirect - immediate
y Direct addressing mode must be used in Push
and Pop
mov sp,#40h ; Initialize SP
push 55h ; SP Å SP+1, M[SP] Å M[55]
; M[41] Å M[55]
pop b ; b Å M[55], SP Å SP-1
Note: can only specify RAM or SFRs (direct mode) to
push or pop. Therefore, to push/pop the accumulator,
must use acc, not a

Stack (push, pop)
y Therefore
Push a ;is invalid
Push r0 ;is invalid
Push r1 ;is invalid
push acc ;is correct
Push psw ;is correct
Push b ;is correct
Push 13h
Push 0
Push 1
Pop 7
Pop 8
Push 0e0h ;acc
Pop 0f0h ;b

Timers/Counter
Timer 0
Timer 1

8051 TIMERS
Timer 0 Timer 1
y Two timers registers of 16 bit i.e. T0 or
T1. They can also be accessed as two 8 bit
registers as THx & TLx.
y Can be used as timer reg/ counter reg.
y As a timer: if input source is oscillator.
y As a counter: if input source is one of
the pin i.e. either TO/T1.

8051 Timer/Counter
T PIN
Gate
INT PIN

TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is
high and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit
set.
C/T*:
When set, counter operation (input from Tx input
pin).
107
p )
When cleared, timer operation (input from internal
clock). copyright@gauravverma

TMOD Register
The TMOD byte is not bit addressable.

TCON Register

8051 TIMERS
Timer 0 Timer 1
Mode 0 Mode 0
Mode 1
Mode 1
Mode 2 Mode M d 2
Mode 110
3

TIMER 0
T0PIN
TR0
Gate
INT0 PIN

TIMER 0 – Mode 0
13 Bit Timer / Counter
T 0PIN
Gate
INT 0 PIN
Maximum Count = copyright@gauravverma
1FFFh
112 (0001111111111111)

TIMER 0 – Mode 1
T 0PIN
TR0
Gate
INT 0 PIN
Maximum Count = FFFFh
(1111111111111111) 113

TIMER 0 – Mode 2
8 Bit Timer / Counter with AUTORELOAD.
Gate
INT 0 PIN
Maximum Count = FFh (11111111)

TIMER 0 – Mode 3
Two - 8 Bit Timer / Counter

TIMER 1

TIMER 1 – Mode 0
Maximum Count = 1FFFh
117 (0001111111111111)

TIMER 1 – Mode 1
Maximum Count = FFFFh
118 copyri(ght1@g1au1rav1ver1ma11111111111)

TIMER 1 – Mode 2
8 Bit Timer / Counter with AUTORELOAD
TL1
OSC ÷12
C / T = 0 TH1
TF1 INTERRUPT
C / T = 1 (8 Bit)
(8 Bit)
T1PIN
TR1
Gate Reload
INT1 PIN
TH1
(8 Bit)
Maximum Count = FFh (11111111) 119 copyright@gauravverma

Programming Timers
y Example: Indicate which mode and which timer are selected for
each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV
TMOD, #12H
y Solution:We convert the value from hex to binary.
(a)TMOD = 00000001, mode 1 of timer 0 is selected.
(b)TMOD = 00100000, mode 2 of timer 1 is selected.
(c)TMOD = 00010010,mode 2 of timer 0, and mode 1 of timer 1
are selected.

Programming Timers
y Find the timer’s clock frequency and its period for various 8051-
based system, with the crystal frequency 11.0592 MHz when C/T bit
ofTMOD is 0.
y Solution:
1/12 × 11.0529 MHz = 921.6 MHz;
T = 1/921.6 kHz = 1.085 us

Programming Timers
y Maximum delay: 65535 microseconds (0000-FFFF)
y Calculation for 50 millisecond or 50000 microsecond delay
y 65535-50000 = 15535 (in decimal) or 3CAF (in hex)
y Put this value in T0 or T1 register as:
THx = #3Ch & TLx = #0AFh
y Use this 50 millisecond delay for making higher value delays like 1
second, 1minute, 1 hour & so on

Programming Timers
y Example: Make a delay of 50 msec using Timer T1 in mode 1 in
software triggered mode.
y Solution:
Assembly Code Embedded C Code
DELAY:
MOV TMOD, # 01H
MOV TCON # 00H
Void delay()
{
TCON, TMOD = 0 01
MOVTH1, # 3CH
MOVTL1, # 0AFH
SETBTR1
0x01;
TCON = 0x00;
TH1 = 0x3C;
TL1 = 0xAF;
WAIT:JNBTF1,WAIT
CLRTR1
RET
TR1=1;
While (TF1==0);
TR1=0;
}
123

Interrupts

INTERRUPTS
y An interrupt is an external or internal event that interrupts
the microcontroller to inform it that a device needs its
service
y A single microcontroller can serve several devices by two
ways:
1. Interrupt
2. Polling

Interrupt Vs Polling
1. Interrupts
y Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
y Upon receiving an interrupt signal, the microcontroller interrupts
whatever it is doing and serves the device.
y The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
y The microcontroller continuously monitors the status of a given
device.
y When the conditions met, it performs the service.
y After that, it moves on to monitor the next device until every one is
serviced.

Interrupt Vs Polling
y The polling method is not efficient, since it wastes much of the
microcontroller’s time by polling devices that do not need service.
y The advantage of interrupts is that the microcontroller can serve
many devices (not all at the same time).
y Each devices can get the attention of the microcontroller based on the
assigned priority.
y For the polling method, it is not possible to assign priority since it
checks all devices in a round-robin fashion.
y The microcontroller can also ignore (mask) a device request for
service in Interrupt.

Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e: not
on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector table,
that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the interrupt
vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it reaches
the last instruction of the subroutine which is RETI (return from
interrupt).
6. Upon executing the RETI instruction, the microcontroller returns to
128 tchopeyrpiglhat@cegawurahveverremait was interrupted.

Six Interrupts in 8051
Six interrupts are allocated as follows:
1. Reset – power-up reset.
2. Two interrupts are set aside for the timers.
y one for timer 0 and one for timer 1
3. Two interrupts are set aside for hardware external
interrupts.
y P3.2 and P3.3 are for the external hardware interrupts INT0 (or
EX1), and INT1 (or EX2)
4. Serial communication has a single interrupt that belongs to
both receive and transfer.

What events can trigger Interrupts?
y We can configure the 8051 so that any of the following events will
cause an interrupt:
y Timer 0 Overflow.
y Timer 1 Overflow.
y Reception/Transmission of Serial Character.
y External Event 0.
y External Event 1.
y We can configure the 8051 so that when Timer 0 Overflows or when
a character is sent/received, the appropriate interrupt handler
routines are called.

8051 Interrupt Vectors

8051 Interrupt related Registers
y The various registers associated with the use of interrupts
are:
y TCON - Edge and Type bits for External Interrupts
0/1
y SCON - RI andTI interrupt flags for RS232
y IE - Enable interrupt sources
y IP - Specify priority of interrupts

Enabling and Disabling an Interrupt
y Upon reset, all interrupts are disabled (masked), meaning that
none will be responded to by the microcontroller if they are
activated.
y The interrupts must be enabled by software in order for the
microcontroller to respond to them.
y There is a register called IE (interrupt enable) that is responsible
for enabling (unmasking) and disabling (masking) the interrupts.

Interrupt Enable (IE) Register
--
• EA : Global enable/disable
disable.
• ‐‐ : Reserved for additional interrupt hardware.
• ES : Enable Serial port interrupt.
• ET1 : Enable Timer 1 control bit.
MOV IE,#08h
or
SETB ET1
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
134
• EX0 : Enable External 0 interrupt.

Enabling and Disabling an Interrupt
y Example: Show the instructions to (a) enable the serial interrupt, timer 0
interrupt, and external hardware interrupt 1 and (b) disable (mask) the
timer 0 interrupt, then (c) show how to disable all the interrupts with a
single instruction.
y Solution:
y (a) MOV IE,#10010110B ;enable serial, timer 0, EX1
y Another way to perform the same manipulation is:
y SETB IE.7 ;EA=1, global enable
y SETB IE.4 ;enable serial interrupt
yy SETB IE.1 ;enable Timer 0 interrupt
y SETB IE.2 ;enable EX1
y (b) CLR IE.1 ;mask (disable) timer 0 interrupt only
y (c) CLR IE.7 ;disable all interrupts 135 copyright@gauravverma

Interrupt Priority
y When the 8051 is powered up, the priorities are assigned according to the
following.
y In reality, the priority scheme is nothing but an internal polling sequence in
which the 8051 polls the interrupts in the sequence listed and responds
accordingly.

Interrupt Priority
y We can alter the sequence of interrupt priority by assigning a higher
priority to any one of the interrupts by programming a register called IP
(interrupt priority).
y To give a higher priority to any of the interrupts, we make the
corresponding bit in the IP register high.

Interrupt Priority (IP) Register
Reserved PS PT1 PX1 PT0 PX0
Serial Port
Timer 1 Pin INT 0 Pin
INT 1 Pin Timer 0 Pin
138
Priority bit=1 assigns high priority
copyright@gauravverma Priority bit=0 assigns low priority

Interrupt Programming
Org 0000h
sjmp Main
Org 0003h
sjmp INTR
Main: Setb EA
Setb EX0
Setb P1.0 ; LED OFF
sjmp $
INTR: cpl P1.0 ; LED GLOW
clr EA
INT0’
reti
End

Serial Communication

Basics of Serial Communication
y Computers transfer data in two ways:
y Parallel: Often 8 or more lines (wire conductors) are used to transfer
data to a device that is only a few feet away.
y Serial: To transfer to a device located many meters away, the serial
method is used.The data is sent one bit at a time.

Basics of Serial Communication
y Serial data communication uses two methods
y Synchronous method transfers a block of data at a time
y Asynchronous method transfers a single byte at a time
yy There are special IC’’s made by many manufacturers for serial
communications.
y UART (universal asynchronous Receiver transmitter)
y USART (universal synchronous-asynchronous Receiver-transmitter)

Asynchronous – Start & Stop Bit
y Asynchronous serial data communication is widely used for
character-oriented transmissions
y Each character is placed in between start and stop bits, this is called
framing.
y Block-oriented data transfers use the synchronous method.
yy The start bit is always one bit, but the stop bit can be one or
two bits
y The start bit is always a 0 (low) and the stop bit(s) is 1
(high)

Asynchronous – Start & Stop Bit

Data Transfer Rate
y The rate of data transfer in serial data communication is stated in bps
(bits per second).
y Another widely used terminology for bps is baud rate.
y It is modem terminology and is defined as the number of signal
changes per second
y In modems, there are occasions when a single change of signal transfers
several bits of data
y As far as the conductor wire is concerned, the baud rate and
bps are the same.

Interfacing IC

Connection Diagram

Interfacing to PC through RS232

8051 Serial Port
y Synchronous and Asynchronous
yy SCON Register is used to Control
y Data Transfer through TXd & RXd pins
y Some time - Clock through TXd Pin
y Four Modes of Operation:
Mode 0 :Synchronous Serial Communication
Mode 1 :8‐Bit UART with Timer Data Rate
Mode 2 :9‐Bit UART with Set Data Rate
Mode 3 :9‐Bit UART with Timer Data Rate

Registers related to Serial
Communication
1. SBUF Register
2. SCON Register
3. PCON Register

SBUF Register
y SBUF is an 8-bit register used solely for serial communication.
y For a byte data to be transferred via the TxD line, it must be placed in
the SBUF register.
y The moment a byte is written into SBUF, it is framed with the start and
stop bits and transferred serially via theTxD line.
y SBUF holds the byte of data when it is received by 8051 RxD line.
y When the bits are received serially via RxD, the 8051 deframes it by
eliminating the stop and start bits, making a byte out of the data
received, and then placing it in SBUF.

SBUF Register
y Sample Program:

SCON Register
SM0 SM1 SM2 REN TB8 RB8 TI RI
Set to Enable
Set when a Cha-ractor
received
Serial Data
reception Set when Stop bit Txed
Enable Multiprocessor
Communication Mode
9th Data Bit
Sent in Mode 2,3
9th Data Bit
Received in Mode 2,3

8051 Serial Port – Mode 0
The Serial Port in Mode-0 has the following features:
1. Serial data enters and exits through RXD
2. TXD outputs the clock
3. 8 bits are transmitted / received
4. The baud rate is fixed at (1/12) of the oscillator frequency

1. Serial data enters through RXD
2. Serial data exits through TXD
3. On receive, the stop bit goes into RB8 in SCON
1. Start bit (0)
2. Data bits (8)
3. Stop Bit (1)
5. Baud rate is determined by the Timer 1 over flow rate.

3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is programmable

3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is determined by Timer 1 overflow rate.

Programming Serial Data Transmission
1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in
mode 2 (8-bit auto-reload) to set baud rate.
2.The TH1 is loaded with one of the values to set baud rate for serial data transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLRTI instruction
6.The character byte to be transferred serially is written into SBUF register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx to see if the
character has been transferred completely.
8.To transfer the next byte, go to step 5

Programming Serial Data Reception
1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in
mode 2 (8-bit auto-reload) to set baud rate.
2. TH1 is loaded to set baud rate
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB RI, xx to see if an
entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are moved into a safe place.
8.To receive the next character, go to step 5.

Doubling Baud Rate
y There are two ways to increase the baud rate of data transfer
1. By using a higher frequency crystal
2. By changing a bit in the PCON register
y PCON register is an 8-bit register.
•When 8051 is powered up, SMOD is zero
•We can set it to high by software and thereby double the baud rate.

Doubling Baud Rate (cont…)
161

C Program
void main()
{
SCON=0X50;
TMOD=0X20; //8bit timer auto‐reload
TH1=0XFD; //baudrate9600
TR1=1; //run the timer
while(1)
{
while(RI==0); //waiting to receive data
P2=SBUF; //after receiving data stored in serial buffer
RI=0; //clear receive interrupt flag to get more
data
SBUF=‘Y’; //fetching data to transmit
while(TI==0); //transmitting it
TI=0; //after transmit complete transmit interrupt
flag is set, so clear it
}
}
162

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