3. interface memory (RAM, ROM, EPROM'...) or I/O
devices to 8086 microprocessor. Several memory
chips or I/O devices can connected to a
microprocessor. An address decoding circuit is used
to select the required I/O device or a memory chip.
3
4. Memory Mapped IO
• Memory Instructions are
used.
• Memory control signals
are used.
• Arithmetic and logic
operations can be
performed on data.
• Data transfer b/w
register and IO.
IO Mapped IO
• Special Instructions
are used like IN, OUT.
• Special control signals
are used.
• Arithmetic and logic
operations can not be
performed on data.
• Data transfer b/w
accumulator and IO.
4
6. 8255 PPI
• The 8255 chip is also called as Programmable Peripheral
Interface.
• The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and
higher capability microprocessors
• The 8255 is a 40 pin integrated circuit (IC), designed to perform
a variety of interface functions in a computer environment.
• It is flexible and economical.
6
9. 8255 PIO/PPI
It has 24 input/output lines which may be
individually programmed.
2 groups of I/O pins are named as
Group A (Port-A & Port C Upper)
Group B (Port-B & Port C Lower)
3 ports(each port has 8 bit)
Port A lines are identified by symbols PA0-PA7
Port B lines are identified by symbols PB0-PB7
Port C lines are identified by PC0-PC7 , PC3-PC0
ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)
9
10. D0 - D7: data input/output lines for the device. All
information read from and written to the 8255 occurs via
these 8 data lines.
CS (Chip Select). If this line is a logical 0, the microprocessor
can read and write to the 8255.
RESET : The 8255 is placed into its reset state if this input
line is a logical 1
10
11. • RD : This is the input line driven by the microprocessor
and should be low to indicate read operation to 8255.
• WR : This is an input line driven by the microprocessor.
A low on this line indicates write operation.
• A1-A0 : These are the address input lines and are driven
by the microprocessor.
11
12. CONTROL LOGIC
CS signal is the master Chip Select
A0 and A1 specify one of the two I/O Ports
CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is not
selected12
14. BLOCK DIAGRAM OF 8255 (ARCHITECTURE)
It has a 40 pins of 4 parts.
1. Data bus buffer
2. Read/Write control logic
3. Group A and Group B controls
4. Port A, B and C
14
15. 1. DATA BUS BUFFER
This is a tristate bidirectional buffer used to
interface the 8255 to system data bus. Data is
transmitted or received by the buffer on execution
of input or output instruction by the CPU.
15
16. 2. READ/WRITE CONTROL LOGIC
This unit accepts control signals ( RD, WR ) and
also inputs from address bus and issues
commands to individual group of control blocks
( Group A, Group B).
It has the following pins.
CS , RD , WR , RESET , A1 , A0
16
17. 3. GROUP A AND GROUP B CONTROLS
• These block receive control from the CPU and issues
commands to their respective ports.
Group A - PA and PCU ( PC7 –PC4)
Group B – PB and PCL ( PC3 –PC0)
a) Port A: This has an 8 bit latched/buffered O/P and 8 bit
input latch. It can be programmed in 3 modes – mode 0,
mode 1, mode 2.
17
18. b) Port B: It can be programmed in mode 0, mode1
c) Port C : It can be programmed in mode 0
18
22. B3 B2 B1
Bit/pin of port C
selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
Concerned only with the 8-bits of Port C.
Set or Reset by control word
Ports A and B are not affected
22
23. A) MODE 0 (SIMPLE INPUT OR OUTPUT):
• Ports A and B are used as Simple I/O
Ports
• Port C as two 4-bit ports
• Features
– Outputs are latched
– Inputs are not latched
– Ports do not have handshake or
interrupt capability
2. I/O MODE
23
25. B) MODE 1: (INPUT OR OUTPUT WITH
HANDSHAKE)
• Handshake signals are exchanged
between MPU & Peripherals
• Features
– Ports A and B are used as Simple I/O Ports
– Each port uses 3 lines from Port C as
handshake signals
– Input & Output data are latched
– interrupt logic supported
25
26. c) Mode 2: Bidirectional Data
Transfer
• Used primarily in applications such as
data transfer between two computers
• Features
– Ports A can be configured as the
bidirectional Port
– Port B in Mode 0 or Mode 1.
– Port A uses 5 Signals from Port C as
handshake signals for data transfer
– Remaining 3 Signals from Port C Used as
– Simple I/O or handshake for Port B
26
27. FIND CONTROL WORD
(1) PORT A: OUTPUT WITH HANDSHAKE
(2) PORT B: INPUT WITH HANDSHAKE
(3) PORT CL: OUTPUT (4)PORT CU: INPUT
Solution:
1 0 1 0 1 1 1 0 = AEH
27
28. FIND THE CONTROL WORD FOR THE REGISTER
ARRANGEMENT
OF THE PORTS OF INTEL 8255 FOR MODE 0 OPERATION.
Port A: Output, Port B: Output,
Port CU: Output, Port CL: Output
Solution:
1 0 0 0 0 0 0 0 = 80H
The control word register for the above ports of
Intel 8255 is 80H.
28
29. FIND THE CONTROL WORD FOR THE REGISTER
ARRANGEMENT
OF THE PORTS OF INTEL 8255 FOR MODE 0
OPERATION.
Port A: Input, Port B: Input,
Port CU: Input, Port CL: Input
Solution:
1 0 0 1 1 0 1 1 = 9BH
The control word register for the above ports of
intel 8255 is 9BH.
29
30. BASICS OF SERIAL COMMUNICATION
1. Transmitter:
- A parallel-in, serial-out
shift register
Receiver:
- A serial-in, parallel-out
shift register.
-
30
Parallel Transfer
33. UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
Programmable chip designed for synchronous and
asynchronous serial data transmission
28 pin DIP
Coverts the parallel data into a serial stream of bits
suitable for serial transmission.
Receives a serial stream of bits and convert it into
parallel data bytes to be read by a microprocessor.
33
36. FIVE SECTIONS
– Read/Write Control Logic
• Interfaces the chip with MPU
• Determine the functions according to the control word
• Monitors data flow
– Transmitter
• Converts parallel word received from MPU into serial bits
• Transmits serial bits over TXD line to a peripheral.
– Receiver
• Receives serial bits from peripheral
• Converts serial bits into parallel word
• Transfers the parallel word to the MPU
– Data Bus Buffer- 8 bit Bidirectional bus.
– Modem Controller
• Used to establish data communication modems over
telephone line
36
37. INPUT SIGNALS
CS – Chip Select
When this signal goes low, 8251 is selected by MPU for
communication
C/D – Control/Data
When this signal is high, the control register or status register
is addressed
When it is low, the data buffer is addressed
Control and Status register is differentiated by WR and RD
signals, respectively
37
38. • WR – Write
– writes in the control register or sends outputs to the data
buffer.
– This connected to IOW or MEMW
• RD – Read
– Either reads a status from status register or accepts data from
the data buffer
– This is connected to either IOR or MEMR
• RESET - Reset
• CLK - Clock
– Connected to system clock
– Necessary for communication with microprocessor.
38
39. CS C/D RD WR Function
0 1 1 0 MPU writes instruction in the
control register
0 1 0 1 MPU reads status from the status
register
0 0 1 0 MPU outputs the data to the Data
Buffer
0 0 0 1 MPU accepts data from the Data
Buffer
1 X X X USART is not Selected
39
40. • Control Register
– 16-bit register
– This register can be accessed an output port
when the C/D pin is high
• Status Register
– Checks ready status of a peripheral
• Data Buffer
40
41. TRANSMITTER SECTION
Accepts parallel data and converts it into serial data
Two registers
Buffer Register
To hold eight bits
Output Register
Converts eight bits into a stream of serial bits
Transmits data on TxD pin with appropriate framing
bits(Start and Stop)
41
42. SIGNALS ASSOCIATED WITH TRANSMITTER
SECTION
• TxD – Transmit Data
– Serial bits are transmitted on this line
• TxC – Transmitter Clock
– Controls the rate at which bits are transmitted
• TxRDY – Transmitter Ready
– Can be used either to interrupt the MPU or indicate the status
• TxE – Transmitter Empty
– Logic 1 on this line indicate that the output register is empty
42
43. RECEIVER SECTION
Accepts serial data from peripheral and converts it
into parallel data
The section has two registers
Input Register
Buffer Register
43
44. SIGNALS ASSOCIATED WITH RECEIVER SECTION
RxD – Receive Data
Bits are received serially on this line and converted into
parallel byte in the receiver input
RxC – Receiver Clock
RxRDY – Receiver Ready
It goes high when the USART has a character in the buffer
register and is ready to transfer it to the MPU
44
45. SIGNALS ASSOCIATED WITH MODEM CONTROL
• DSR- Data Set Ready
– Normally used to check if the Data Set is ready when
communicating with a modem
• DTR – Data Terminal Ready
– device is ready to accept data when the 8251 is communicating with
a modem.
• RTS – Request to send Data
– the receiver is ready to receive a data byte from modem
• CTS – Clear to Send
45
54. 11-
54
8251 command register
EH IR RTS ER SBRK RxE DTR TxE command register
TxE: transmit enable
DTR: data terminal ready, DTR pin will be low
RxE: receiver enable
SBPRK: send break character, TxD pin will be low
ER: error reset
RTS: request to send, CTS pin will be low
IR: internal reset
EH: enter hunt mode (1=enable search for SYN character)
55. 11-
55
8251 status register
DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status
register
TxRDY: transmit ready
RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
57. ADC 0808/0809
The analog to digital converter chips 0808 and 0809 are
8-bit CMOS,successive approximation converters.
Successive approximation technique is one of the fast
techniques for analog to digital conversion. The
conversion delay is 100 µs at a clock frequency of 640
kHz.
57
63. INTERFACING DIGITAL TO ANALOG
ONVERTERS
The digital to analog converters convert binary
numbers into their analog equivalent voltages or
currents.
Techniques are employed for digital to analog
conversion.
i. Weighted resistor network
ii. R-2R ladder network
iii. Current output D/A converter
63
64. The DAC find applications in areas like digitally controlled
gains, motor speed control, programmable gain
amplifiers, digital voltmeters, panel meters, etc.
In a compact disk audio player for example a 14 or16-bit
D/A converter is used to convert the binary data read off
the disk by a laser to an analog audio signal.
Characteristics :
1. Resolution: It is a change in analog output for one
LSB change in digital input.
It is given by(1/2^n )*Vref. If n=8 (i.e.8-bit DAC)
1/256*5V=39.06mV
2. Settling time: It is the time required for the DAC to
settle for a full scale code change.
64
65. DAC 0800 8-bit Digital to Analog converter
Features:
i. DAC0800 is a monolithic 8-bit DAC manufactured by
National semiconductor.
ii. It has settling time around 100ms
iii. It can operate on a range of power supply voltage i.e.
from 4.5V to +18V. Usually the supply V+ is 5V or
+12V.
The V- pin can be kept at a minimum of -12V.
iv. Resolution of the DAC is 39.06mV
65
70. RD: read signal
WR: write signal
CS: chip select signal
A0, A1: address lines
Clock :This is the clock input for the counter. The counter
is 16 bits.
Out :This single output line is the signal that is the final
programmed output of the device.
Gate :This input can act as a gate for the clock input line,
or it can act as a start pulse,
70
74. 8254 MODES
Gate is low the
count will be
paused
Gate is high
Will continue
counting
Mode 0: An events counter enabled with G.
Mode 1: One-shot mode. s
Gate is
High output
will be high
Counter will be reloaded
After gate high.
74
75. Mode 2: Counter generates a series of pulses 1 clock
pulse wide
Mode 3: Generates a continuous square-wave with G set to 1
cycle is repeated until
reprogrammed or G pin
set to 0
If count is even, 50% duty cycle
otherwise OUT is high 1 cycle
longer
75
76. Mode 4: Software triggered one-shot.
Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.
In the last counting
Will be stop
(not repeated)
In the last count
Out will be low
76
84. KEYBOARD SECTION
The keyboard section consists of 8 return lines
RL0 - RL7 that can be used to form the columns
of a keyboard matrix.
It has two additional input : shift and
control/strobe. The keys are automatically
debounced.
The two operating modes of keyboard section
are 2-key lockout and N-key rollover.
84
85. In the 2-key lockout mode, if two keys are pressed
simultaneously, only the first key is recognized.
In the N-key rollover mode simultaneous keys are
recognized and their codes are stored in FIFO.
The keyboard section also have an 8 x 8 FIFO (First
In First Out) RAM.
The FIFO can store eight key codes in the
scan keyboard mode. The status of the shift
key and control key are also stored along
with key code. The 8279 generate an interrupt
signal (IRQ)when there is an entry in FIFO.
85
86. DISPLAY SECTION
The display section has eight output lines
divided into two groups A0-A3 and B0-B3.
The output lines can be used either as a single
group of eight lines or as two groups of four
lines, in conjunction with the scan lines for a
multiplexed display.
The output lines are connected to the anodes
through driver transistor in case of common
cathode 7-segment LEDs.
86
87. The cathodes are connected to scan lines
through driver transistors.
The display can be blanked by BD (low) line.
The display section consists of 16 x 8 display
RAM. The CPU can read from or write into any
location of the display RAM.
87
88. SCAN SECTION
The scan section has a scan counter and
four scan lines, SL0 to SL3.
In decoded scan mode, the output of scan
lines will be similar to a 2-to-4 decoder.
In encoded scan mode, the output of scan
lines will be binary count, and so an
external decoder should be used to convert
the binary count to decoded output.
The scan lines are common for keyboard
and display.
88
89. CPU INTERFACE SECTION
The CPU interface section takes care of data
transfer between 8279 and the processor.
This section has eight bidirectional data lines
DB0 to DB7 for data transfer between 8279 and
CPU.
It requires two internal address A =0 for
selecting data buffer and A = 1 for selecting
control register of8279.
89
90. The control signals WR (low), RD (low), CS (low) and
A0 are used for read/write to 8279.
It has an interrupt request line IRQ, for interrupt
driven data transfer with processor.
The 8279 require an internal clock frequency of 100
kHz. This can be obtained by dividing the input clock
by an internal prescaler.
90
91. All the command words or status words are written or
read with A0 = 1 and CS = 0 to or from 8279.
a) Keyboard Display Mode Set : The format of the command word to select
different modes of operation of 8279 is given below with its bit definitions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
91
93. B) Programmable clock :
The clock for operation of 8279 is obtained by
dividing the external clock input signal by a
programmable constant called prescaler.
PPPPP is a 5-bit binary constant.
The input frequency is divided by a decimal
constant ranging from 2 to 31, decided by the bits of
an internal prescaler, PPPPP.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 P P P P P
93
94. c) Read FIFO / Sensor RAM : The format of this command is
given below.
AI – Auto Increment Flag
AAA – Address pointer to 8 bit FIFO RAM
X- Don’t care
This word is written to set up 8279 for reading FIFO/ sensor
RAM.
In scanned keyboard mode, AI and AAA bits are of no use.
The 8279 will automatically drive data bus for each
subsequent read, in the same sequence, in which the data
was entered.
In sensor matrix mode, the bits AAA select one of the 8
rows of RAM.
If AI flag is set, each successive read will be from the
subsequent RAM location.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A
94
95. d) Read Display RAM :
This command enables a programmer to read the display RAM
data.
The CPU writes this command word to 8279 to prepare
it for display RAM read operation.
AI is auto increment flag and AAAA, the 4-bit address
points to the 16-byte display RAM that is to be read.
If AI=1, the address will be automatically, incremented
after each read or write to the Display RAM.
The same address counter is used for reading and
writing.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A
95
96. d) Write Display RAM :
This command enables a programmer to write the display RAM
data.
AI – Auto increment Flag.
AAAA – 4 bit address for 16-bit display RAM to be
written.
e) Display Write Inhibit/Blanking :
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 X IW IW BL BL
IW - inhibit write flag
BL - blank display bit flags
96
97. g) Clear Display RAM :
ENABLES CLEAR DISPLAY
WHEN CD2=1
• CD2 must be 1 for enabling the clear display command.
• If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly
same as above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is
cleared and IRQ line is pulled down and the sensor RAM
pointer is set to row 0.
•If CA=1, this combines the effect of CD and CF bits.
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 CD2 CD1 CD0 CF CA
CD2 CD1 CD0
0X - All zeros ( x don’t care ) AB=00
10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
11 - All ones (AB =FF), i.e. clear RAM
97
98. h) End Interrupt / Error mode Set :
E- Error mode
X- don’t care
For the sensor matrix mode, this command lowers
the IRQ line and enables further writing into the RAM.
Otherwise, if a change in sensor value is detected,
IRQ goes high that inhibits writing in the sensor RAM.
For N-Key roll over mode, if the E bit is
programmed to be ‘1’, the 8279 operates in special
Error mode
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 E X X X 1
98
101. 1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. The operation of the PIC is programmable under software control (Programmable)and it
can be configured for a wide variety of applications.
5. 8259A is treated as peripheral in a microcomputer system.
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
7. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.
8. Some of its programmable features are:
· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.
8259 Programmable Interrupt Controller (PIC)
104. ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a
slave in a system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the
master, and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the
system. In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
105. When the 8259A is in buffered mode, this pin is an
output that controls the data bus transceivers in a
large microprocessor-based system.
When the 8259A is not in buffered mode, this pin
programs the device as a master (1) or a slave (0).
CAS2-CAS0, the cascade lines are used as outputs from
the master to the slaves for cascading multiple
8259As in a system.
124. The 82C59A accepts two types of command words generated by the
CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 82C59A in the
system must be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
• Operational Command Words (OCWs):
These are the command words which command the 82C59A
to operate in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
Programming the 8259A: -
125. To program this ICW for 8086 we place a logic 1 in bit IC4.
Bits D7, D6 , D5and D2 are don’t care for microprocessor operation and only
apply to the 8259A when used with an 8-bit 8085 microprocessor.
This ICW selects single or cascade operation by programming the SNGL bit. If
cascade operation is selected, we must also program ICW3.
The LTIM bit determines whether the interrupt request inputs are positive edge
triggered or level-triggered.
ICW1:
126. Selects the vector number used with the interrupt request inputs.
For example, if we decide to program the 8259A so that it functions at vector
locations 08H-0FH, we place a 08H into this command word.
Likewise, if we decide to program the 8259A for vectors 70H-77H, we place a
70H in this ICW.
ICW2:
127. Is used only when ICW1 indicates that the system is operated in cascade mode.
This ICW indicates where the slave is connected to the master.
For example, if we connected a slave to IR2, then to program ICW3 for this
connection, in both master and slave, we place a 04H in ICW3.
Suppose we have two slaves connected to a master using IR0 and IR1. The
master is programmed with an ICW3 of 03H; one slave is programmed with an
ICW3 of 01H and the other with an ICW3 of 02H.
ICW3:
128. Is programmed for use with the 8088/8086. This ICW
is not programmed in a system that functions with the
8085 microprocessors.
The rightmost bit must be logic 1 to select operation
with the 8086 microprocessor, and the remaining bits
are programmed as follows:
ICW4:
129. Is used to set and read the interrupt mask register.
When a mask bit is set, it will turn off (mask) the corresponding
interrupt input. The mask register is read when OCW1 is read.
Because the state of the mask bits is known when the 8259A is
first initialized, OCW1 must be programmed after programming
the ICW upon initialization.
Operation Command Words
OCW1:
130. Is programmed only when the AEOI mod is not selected for the 8259A.
In this case, this OCW selects how the 8259A responds to an interrupt.
The modes are listed as follows in next slide:
OCW2:
131. Selects the register to be read, the operation of the special mask register, and
the poll command.
If polling is selected, the P-bit must be set and then output to the 8259A. The
next read operation would read the poll word. The rightmost three bits of the
poll word indicate the active interrupt request with the highest priority.
The leftmost bit indicates whether there is an interrupt, and must be checked
to determine whether the rightmost three bits contain valid information.
OCW3:
132. INTRODUCTION:
Direct Memory Access (DMA) is a method of allowing
data to be moved from one location to another in a
computer without intervention from the central processor
(CPU).
It is also a fast way of transferring data within (and
sometimes between) computer.
The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily
disabled.
The DMA controller temporarily borrows the address
bus, data bus and control bus from the microprocessor
and transfers the data directly from the external devices
to a series of memory locations (and vice versa).
132
133. Supplies memory and I/O with control signals and addresses
during DMA transfer
4-channels (expandable)
0: DRAM refresh
1: Free
2: Floppy disk controller
3: Free
1.6MByte/sec transfer rate
64 KByte section of memory address capability with single
programming
“fly-by” controller (data does not pass through the DMA-only
memory to I/O transfer capability)
Initialization involves writing into each channel:
i) The address of the first byte of the block of data that must be transferred
(called the base address).
ii) The number of bytes to be transferred (called the word count).
133
THE 8237 DMA CONTROLLER
134. 8237 PINS
CLK: System clock
CS΄: Chip select (decoder output)
RESET: Clears registers, sets mask register
READY: 0 for inserting wait states
HLDA: Signals that the μp has relinquished buses
DREQ3 – DREQ0: DMA request input for each channel
DB7-DB0: Data bus pins
IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
EOP΄: End of process is a bidirectional signal used as input to terminate a DMA
process or as output to signal the end of the DMA transfer
A3-A0: Address pins for selecting internal registers
A7-A4: Outputs that provide part of the DMA transfer address
HRQ: DMA request output
DACK3-DACK0: DMA acknowledge for each channel.
AEN: Address enable signal
ADSTB: Address strobe
MEMR΄: Memory read output used in DMA read cycle
MEMW΄: Memory write output used in DMA write cycle
134
136. BLOCK DIAGRAM DESCRIPTION
It containing Five main Blocks.
1. Data bus buffer
2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.
136
137. DATA BUS BUFFER:
It contain tristate ,8 bit bi-directional buffer.
Slave mode ,it transfer data between
microprocessor and internal data bus.
Master mode ,the outputs A8-A15 bits of
memory address on data lines
(Unidirectional).
READ/CONTROL LOGIC:
It control all internal Read/Write operation.
Slave mode ,it accepts address bits and control signal from
microprocessor.
Master mode ,it generate address bits and control signal.
137
138. Control logic block
It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:
Master mode ,It control the sequence of DMA
operation during all DMA cycles.
It generates address and control signals.
It increments 16 bit address and decrement 14
bit counter registers.
It activate a HRQ signal on DMA channel
Request.
Slave ,mode it is disabled. 138
142. Traffic lights, which may also be known as stoplights,
traffic lamps, traffic signals, signal lights, robots or
semaphore, are signaling devices positioned at road
intersections, pedestrian crossings and other
locations to control competing flows of traffic.
INTERFACING TRAFFIC LIGHT WITH 8086
The Traffic light controller section consists of 12
Nos. point led’s arranged by 4Lanes in Traffic light
interface card. Each lane has Go(Green),
Listen(Yellow) and Stop(Red) LED is being placed.
142
143. LAN Direction 8086 LINES MODULES
SOUTH
PA.0 GO
PA.1 LISTEN
PA.2 STOP
EAST
PA.3 GO
PA.4 LISTEN
PA.5 STOP
NORTH
PA.6 GO
PA.7 LISTEN
PB.0 STOP
WEST
PB.1 GO
PB.2 LISTEN
PB.3 STOP
13-16 No Connection
PWR
17,189 Supply from
microcontroller
18,20
143
148. Light Emitting Diodes (LED) is the most
commonly used components, usually for displaying pins
digital states. Typical uses of LEDs include alarm
devices, timers and confirmation of user input such as a
mouse click or keystroke.
INTERFACING LED
Anode is connected through a resistor to GND & the
Cathode is connected to the Microprocessor pin. So
when the Port Pin is HIGH the LED is OFF & when the
Port Pin is LOW the LED is turned ON.
148
151. 8086 ALP LED INTERFACE
1100: START: MOV AL, 80
MOV DX, FF36
OUT DX, AL
BEGIN: MOV AL, 00
MOV DX, FF30
OUT DX, AL
CALL DELAY
MOV AL, FF
OUT DX, AL
CALL DELAY
JMP BEGIN
DELAY: MOV CX, FFFF
PO: DEC CX
JNE PO
RET
151
155. LCD INTERFACING WITH 8086
TRAINER KIT
GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24
GPIO- I (8255) J4 Connector
PORTS ADDRESS
Control port FF36
PORT A FF30
PORT B FF32
PORT C FF34 155
157. LCD INTERFACING WITH 8051 TRAINER KIT
GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port 4003
PORT A 4000
PORT B 4001
PORT C 4002
Used in UNIT 5 also
157
160. HARDWARE DESCRIPTION OF 8279 INTERFACE CARD
Keyboard and display is configured in the encoded
mode. In the encoded mode, a binary count sequence is
put on the scan lines SL0-SL3. These lines must be
externally decoded to provide the scan lines for keyboard
and display. A 3 to 8 decoder 74LS138 is provided for this
purpose. The S0-S1 output lines of this decoder are
connected to the two rows of the keyboard. And QA0 to
QA7 is connected to 7 Segment Display
160
161. PIN DIAGRAM OF 8279 PIN DIAGRAMOF 74LS138
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
161
164. MVI A, 00H Initialize keyboard/display in encoded
OUT 81H scan keyboard 2 key lockout mode
MVI A, 34H
OUT 81H Initialize prescaler count
MVI A, 0BH Load mask pattern to enable RST 7.5
SIM mask other interrupts
EI Enable Interrupt
HERE: JMP HERE Wait for the interrupt
Interrupt service routine
MVI A, 40H Initialize 8279 in read FIFO RAM mode
OUT 81H
IN 80H Get keycode
MVI H, 62H Initialize memory pointer to point
MOV L, A 7-Segment code
MVI A, 80H : Initialize 8279 in write display RAM mode
OUT 81H
MOV A, M : Get the 7 segment code
OUT 80H : Write 7-segment code in display RAM
EI : Enable interrupt
RET : Return to main program
164
167. TO INTERFACE RELAY AND BUZZER WITH 8086 TRAINER KIT
AND TO ON/OFF RELAY AND BUZZER CARD
GPIO- I J1 Connecter
PORTS
ADDRESS
Control port FF26
PORT A
FF20
PORT B
FF22
PORT C
FF24
GPIO- II J1 Connecter
PORTS
ADDRESS
Control port FF36
PORT A
FF30
PORT B
FF32
167
173. MICROPROCESSOR VS. MICROCONTROLLER
Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are
separate
Designer can decide on the
amount of ROM, RAM and
I/O ports.
Expansive
General-purpose
Microcontroller
CPU, RAM, ROM, I/O and timer
are all on a single chip
Fix amount of on-chip ROM,
RAM, I/O ports
For applications in which cost,
power and space are critical
Not Expansive
Single-purpose 173
174. MICROCONTROLLERS APPLICATIONS
Home
Appliances, intercom, telephones, security systems, garage door openers,
answering machines, fax machines, home computers, TVs, cable TV
tuner, VCR, camcorder, remote controls, video games, cellular phones,
musical instruments, sewing machines, lighting control, paging, camera,
pinball machines, toys, exercise equipment etc.
Office
Telephones, computers, security systems, fax machines, microwave,
copier, laser printer, color printer, paging etc.
Auto
Trip computer, engine control, air bag, ABS, instrumentation, security
system, transmission control, entertainment, climate control, cellular
phone, keyless entry
174
