The document describes a novel 5-stage delay line circuit using multi-threshold carbon nanotube field-effect transistors (MTCNTFETs) designed at a 32nm technology node. Simulation results show that the MTCNT delay line has a 97.45% reduction in propagation delay and a 99.2% reduction in average power consumption compared to an equivalent MTCMOS delay line. The MTCNT technique offers better performance than MTCMOS for delay lines by using carbon nanotubes instead of silicon, which enables further reductions in leakage current and power. A 5-stage MTCNT delay line circuit is presented and its operation explained, showing how it introduces delay between stages using NOT gates constructed from the MTC
IRJET- Novel Design of Low Power Nonvolatile 10T1R SRAM CellIRJET Journal
This document proposes a novel design for a low power nonvolatile 10T1R SRAM cell. The proposed cell aims to reduce power dissipation in SRAMs, which account for 70% of chip area in microprocessors. It combines a conventional 6T SRAM cell with a memristor and additional transistors. The cell operates in three modes - write, power off, and restore. Simulation results show the proposed cell reduces power, delay, power-delay product, and leakage current compared to previous nonvolatile SRAM designs. The cell was simulated in Cadence using a 45nm technology at a 1V supply voltage. Key advantages are its nonvolatility, which allows restoring data after power off, and lower power consumption
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
This document describes the VLSI implementation of a fractional-N phase locked loop (PLL) frequency synthesizer using 45nm technology. It discusses the design and simulation of the key PLL components including the phase detector, loop filter, voltage controlled oscillator, and sigma-delta modulator. The layout of the overall fractional-N PLL integrated circuit is presented, which consists of 23 NMOS and 23 PMOS transistors. Simulation results show the PLL locks onto an output frequency of 2.5GHz while consuming only 53.239μwatts of power.
Design and Implementation of 6t SRAM using FINFET with Low Power ApplicationIRJET Journal
This document discusses the design and implementation of a 6T SRAM cell using FINFET technology with low power applications. It begins with an introduction to some of the limitations of conventional CMOS-based SRAM cells, such as high power dissipation and increased leakage current. FINFET-based SRAM cells are proposed as an alternative to address these issues due to their multi-gate structure which provides better electrostatic control. The document then describes the implementation of a basic 6T FINFET SRAM cell. It further discusses the use of the multithreshold CMOS (MTCMOS) technique applied to the FINFET SRAM cell to reduce dynamic power dissipation during write operations by disconnecting the low threshold
IRJET - Low Power M-Sequence Code Generator using LFSR for Body Sensor No...IRJET Journal
The document describes a proposed low power m-sequence code generator using a linear feedback shift register (LFSR) for body sensor node applications. An LFSR generates pseudo-random binary sequences through a linear feedback function combining bits in the shift register. The document evaluates different designs for the XOR gates used in the feedback function, finding a transmission gate based design consumes significantly less power than other designs. It then proposes a 7-bit m-sequence code generator using a 3-stage LFSR with XOR gates in the feedback loop for low power consumption, suitable for use in wireless body sensor nodes.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
IRJET- Novel Design of Low Power Nonvolatile 10T1R SRAM CellIRJET Journal
This document proposes a novel design for a low power nonvolatile 10T1R SRAM cell. The proposed cell aims to reduce power dissipation in SRAMs, which account for 70% of chip area in microprocessors. It combines a conventional 6T SRAM cell with a memristor and additional transistors. The cell operates in three modes - write, power off, and restore. Simulation results show the proposed cell reduces power, delay, power-delay product, and leakage current compared to previous nonvolatile SRAM designs. The cell was simulated in Cadence using a 45nm technology at a 1V supply voltage. Key advantages are its nonvolatility, which allows restoring data after power off, and lower power consumption
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
This document describes the VLSI implementation of a fractional-N phase locked loop (PLL) frequency synthesizer using 45nm technology. It discusses the design and simulation of the key PLL components including the phase detector, loop filter, voltage controlled oscillator, and sigma-delta modulator. The layout of the overall fractional-N PLL integrated circuit is presented, which consists of 23 NMOS and 23 PMOS transistors. Simulation results show the PLL locks onto an output frequency of 2.5GHz while consuming only 53.239μwatts of power.
Design and Implementation of 6t SRAM using FINFET with Low Power ApplicationIRJET Journal
This document discusses the design and implementation of a 6T SRAM cell using FINFET technology with low power applications. It begins with an introduction to some of the limitations of conventional CMOS-based SRAM cells, such as high power dissipation and increased leakage current. FINFET-based SRAM cells are proposed as an alternative to address these issues due to their multi-gate structure which provides better electrostatic control. The document then describes the implementation of a basic 6T FINFET SRAM cell. It further discusses the use of the multithreshold CMOS (MTCMOS) technique applied to the FINFET SRAM cell to reduce dynamic power dissipation during write operations by disconnecting the low threshold
IRJET - Low Power M-Sequence Code Generator using LFSR for Body Sensor No...IRJET Journal
The document describes a proposed low power m-sequence code generator using a linear feedback shift register (LFSR) for body sensor node applications. An LFSR generates pseudo-random binary sequences through a linear feedback function combining bits in the shift register. The document evaluates different designs for the XOR gates used in the feedback function, finding a transmission gate based design consumes significantly less power than other designs. It then proposes a 7-bit m-sequence code generator using a 3-stage LFSR with XOR gates in the feedback loop for low power consumption, suitable for use in wireless body sensor nodes.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
Delay Optimized Full Adder Design for High Speed VLSI ApplicationsIRJET Journal
This document describes the design and simulation of a hybrid full adder circuit for high-speed VLSI applications. Full adders are important components used in arithmetic logic units, floating point units, and address generation. The author first reviews existing full adder designs based on static CMOS, transmission gate, and dynamic logic styles. Then, a previously proposed hybrid CMOS full adder using both transmission gates and CMOS is described. To improve speed, the author proposes a modified full adder design using only 14 transistors instead of 16. Both the existing and proposed designs are simulated in Cadence Virtuoso at 180nm and 90nm technology nodes. Simulation results show the proposed design has lower power consumption and propagation delay compared to the
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
This document analyzes and compares the pocket double gate tunnel FET (DGTFET) and MOSFET for use in low standby power logic circuits. Simulation results show that the pocket DGTFET has lower leakage current than the MOSFET. A pocket DGTFET inverter is designed in 32nm technology with a supply voltage of 0.6V. The pocket DGTFET inverter has significantly lower leakage power of 0.116pW compared to 1.83pW for a multi-threshold CMOS inverter. Therefore, the pocket DGTFET is well-suited to replace the MOSFET for low standby power applications.
The document describes a 4-phase power supply design using the LTC3875 controller that can deliver 120A of current in a small footprint. It utilizes two LTC3875 controllers operating with 90 degree phase shifts to reduce ripple. Each phase supports 30A using a single top and bottom MOSFET. The LTC3875 can accurately sense currents even with inductors having very low DCR values as low as 0.2mOhms. The design achieves 87.1% efficiency at 120A output. An alternative design is presented using one LTC3875 controller and one LTC3874 slave controller to reduce component count and solution size.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
This document discusses techniques to reduce leakage current and power consumption in static random-access memory (SRAM) cells implemented using independent gate fin field-effect transistors (FinFETs). It first describes the independent gate FinFET SRAM cell design and its advantages over other designs. It then examines two circuit-level leakage reduction techniques: 1) using multi-threshold voltages by connecting high-threshold transistors to reduce leakage when in standby mode, and 2) adding a gated power supply transistor to reduce leakage through stacking effects. Simulation results show that both techniques can reduce leakage current and power in the independent gate FinFET SRAM cell, with multi-threshold voltages providing better leakage control.
This document discusses the design of high frequency 32/33 prescalers using a 2/3 prescaler technique. It analyzes different types of flip-flops that can be used in prescaler circuits including master-slave, pulse-triggered, differential, and dual-edge triggered. Dual-edge triggered and pulse-triggered flip-flops are determined to be unsuitable for prescaler circuits. Various implementations of divide-by-2/3 prescalers using true single phase clock (TSPC) and extended TSPC (ETSPC) flip-flops are presented and compared in terms of operating frequency, power, delay, and power-delay product. Simulation results show that ETSPC designs
2011 Protection of a 3.3V Domain and Switchable 1.8V/3.3V I/O in 40nm and 28n...Sofics
This document summarizes a conference paper describing protection circuits for a 3.3V power domain and switchable 1.8V/3.3V I/O in 40nm and 28nm processes using only 1.8V transistors. It describes the issues, solutions, and results of building protection against HBM, MM, CDM, and latch-up. Key aspects included a DTSCR power clamp, ESD-ON-SCR local I/O clamps, and test results showing protection levels exceeding specifications of 2kV HBM and 200V MM in 40nm. The same approach was then ported to a 28nm process with I/O circuits tested on a 28nm MPW test chip.
This document discusses switch-on-to-fault (SOTF) protection schemes. It describes the purpose of SOTF schemes, which is to trip a transmission line breaker when closed onto a faulted line. It outlines three common SOTF scheme applications and details the internal logic and settings of SOTF schemes in numerical relays. The document compares internal dead line detection logic to external trigger methods and discusses merits and limitations of different SOTF implementation methods. It also provides examples of SOTF logic for different breaker arrangements like one and a half breaker, double bus, and double bus transfer schemes.
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
1) The document proposes a novel design of flip flops and a 4-bit up counter using Quantum-Dot Cellular Automata (QCA) technology. QCA is an emerging nanotechnology that could overcome scaling limitations of CMOS.
2) In QCA, logic states are represented by the position of electrons in quantum dots rather than voltage as in CMOS. Basic logic gates like inverters and majority gates are constructed using QCA cells.
3) The document designs various flip flops like SR, JK, D, and T flip flops in QCA and uses them to build a 4-bit up counter. Power consumption is shown to be lower for the QCA designs compared to
An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. The use of a Phase Locked Loop enables the receiver to adaptively track and remove frequency/phase offsets. The pll consists of loop filter, VCO and amplifier. The paper describes the designing of this loop filter using CMOS. The use of this element reduces cost drastically and has a good response. An experiment was conducted through this component which provided better result. The main advantage of designing low pass filter by CMOS is that it offers improvements in design simplicity and programmability when compared to op-amp based structures as well as reduced component count. It has high noise immunity and low static power consumption. Hence the overall efficiency increases as well producing the desired effect.
Analysis and design of a low voltage and low power double tail comparatorUshaswini Chowdary
The document describes the design and analysis of a low-voltage, low-power double-tail comparator. It begins by introducing comparators and their use in analog-to-digital converters. It then discusses challenges in designing high-speed comparators for modern low-voltage CMOS processes. The document analyzes delay in dynamic comparators and presents a new double-tail comparator design that aims to reduce latch delay time without requiring a boosted voltage. It describes the operation of conventional dynamic and double-tail comparators before detailing the proposed comparator's design which uses added control transistors to increase the initial differential output voltage and speed up latch regeneration.
This document discusses the advantages of a 5T SRAM cell compared to a traditional 6T SRAM cell. It summarizes the design and operation of a 5T SRAM cell, which removes one transistor compared to a 6T cell. This reduces power consumption by eliminating the need to charge and discharge one of the bit lines during read and write operations. The document then describes the layout design of a 64-bit 5T SRAM using a 90nm technology node. It compares the performance of this 64-bit 5T SRAM to a 64-bit 6T SRAM in terms of power consumption, layout area, number of transistors, and leakage current.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
7SS52 Distributed Bus Bar Diffrential Protection Relayashwini reliserv
The SIPROTEC 7SS52 numerical protection is a selective, reliable and fast protection for busbar faults and breaker failure in medium, high and extra-high voltage substations with various possible busbar configurations.
The protection is suitable for all switchgear types with iron-core or linearized current transformers. The short tripping time is especially advantageous for applications with high fault levels or where fast fault clearance is required for power system stability.
This document summarizes an improved SRAM design implemented using Cadence. The focus was on developing a simplified design by reducing transistor count and replacing some conventional circuit designs. Key aspects of the SRAM design discussed include the 6T SRAM cell, transistor sizing considerations, precharge circuits, sense amplifiers, write amplifiers, decoders, control circuits including flip-flops and write select generators, and specifying input stimuli using digital vector files. The design aims to increase speed and reduce layout area of the SRAM.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Review on Tunnel Field Effect Transistors (TFET)IRJET Journal
The document discusses Tunnel Field Effect Transistors (TFETs) as a promising alternative to MOSFETs for low power applications. TFETs use band-to-band tunneling as the switching mechanism instead of thermionic emission like in MOSFETs, allowing TFETs to achieve subthreshold slopes lower than 60 mV/decade. The document reviews different TFET structures that have been proposed over time, including heterojunction TFETs that use different materials for the source and channel to facilitate band-to-band tunneling. TFETs are seen as important for continued device scaling as they can help reduce static and dynamic power consumption compared to conventional MOSFETs.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Delay Optimized Full Adder Design for High Speed VLSI ApplicationsIRJET Journal
This document describes the design and simulation of a hybrid full adder circuit for high-speed VLSI applications. Full adders are important components used in arithmetic logic units, floating point units, and address generation. The author first reviews existing full adder designs based on static CMOS, transmission gate, and dynamic logic styles. Then, a previously proposed hybrid CMOS full adder using both transmission gates and CMOS is described. To improve speed, the author proposes a modified full adder design using only 14 transistors instead of 16. Both the existing and proposed designs are simulated in Cadence Virtuoso at 180nm and 90nm technology nodes. Simulation results show the proposed design has lower power consumption and propagation delay compared to the
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
This document analyzes and compares the pocket double gate tunnel FET (DGTFET) and MOSFET for use in low standby power logic circuits. Simulation results show that the pocket DGTFET has lower leakage current than the MOSFET. A pocket DGTFET inverter is designed in 32nm technology with a supply voltage of 0.6V. The pocket DGTFET inverter has significantly lower leakage power of 0.116pW compared to 1.83pW for a multi-threshold CMOS inverter. Therefore, the pocket DGTFET is well-suited to replace the MOSFET for low standby power applications.
The document describes a 4-phase power supply design using the LTC3875 controller that can deliver 120A of current in a small footprint. It utilizes two LTC3875 controllers operating with 90 degree phase shifts to reduce ripple. Each phase supports 30A using a single top and bottom MOSFET. The LTC3875 can accurately sense currents even with inductors having very low DCR values as low as 0.2mOhms. The design achieves 87.1% efficiency at 120A output. An alternative design is presented using one LTC3875 controller and one LTC3874 slave controller to reduce component count and solution size.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
This document discusses techniques to reduce leakage current and power consumption in static random-access memory (SRAM) cells implemented using independent gate fin field-effect transistors (FinFETs). It first describes the independent gate FinFET SRAM cell design and its advantages over other designs. It then examines two circuit-level leakage reduction techniques: 1) using multi-threshold voltages by connecting high-threshold transistors to reduce leakage when in standby mode, and 2) adding a gated power supply transistor to reduce leakage through stacking effects. Simulation results show that both techniques can reduce leakage current and power in the independent gate FinFET SRAM cell, with multi-threshold voltages providing better leakage control.
This document discusses the design of high frequency 32/33 prescalers using a 2/3 prescaler technique. It analyzes different types of flip-flops that can be used in prescaler circuits including master-slave, pulse-triggered, differential, and dual-edge triggered. Dual-edge triggered and pulse-triggered flip-flops are determined to be unsuitable for prescaler circuits. Various implementations of divide-by-2/3 prescalers using true single phase clock (TSPC) and extended TSPC (ETSPC) flip-flops are presented and compared in terms of operating frequency, power, delay, and power-delay product. Simulation results show that ETSPC designs
2011 Protection of a 3.3V Domain and Switchable 1.8V/3.3V I/O in 40nm and 28n...Sofics
This document summarizes a conference paper describing protection circuits for a 3.3V power domain and switchable 1.8V/3.3V I/O in 40nm and 28nm processes using only 1.8V transistors. It describes the issues, solutions, and results of building protection against HBM, MM, CDM, and latch-up. Key aspects included a DTSCR power clamp, ESD-ON-SCR local I/O clamps, and test results showing protection levels exceeding specifications of 2kV HBM and 200V MM in 40nm. The same approach was then ported to a 28nm process with I/O circuits tested on a 28nm MPW test chip.
This document discusses switch-on-to-fault (SOTF) protection schemes. It describes the purpose of SOTF schemes, which is to trip a transmission line breaker when closed onto a faulted line. It outlines three common SOTF scheme applications and details the internal logic and settings of SOTF schemes in numerical relays. The document compares internal dead line detection logic to external trigger methods and discusses merits and limitations of different SOTF implementation methods. It also provides examples of SOTF logic for different breaker arrangements like one and a half breaker, double bus, and double bus transfer schemes.
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
1) The document proposes a novel design of flip flops and a 4-bit up counter using Quantum-Dot Cellular Automata (QCA) technology. QCA is an emerging nanotechnology that could overcome scaling limitations of CMOS.
2) In QCA, logic states are represented by the position of electrons in quantum dots rather than voltage as in CMOS. Basic logic gates like inverters and majority gates are constructed using QCA cells.
3) The document designs various flip flops like SR, JK, D, and T flip flops in QCA and uses them to build a 4-bit up counter. Power consumption is shown to be lower for the QCA designs compared to
An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. The use of a Phase Locked Loop enables the receiver to adaptively track and remove frequency/phase offsets. The pll consists of loop filter, VCO and amplifier. The paper describes the designing of this loop filter using CMOS. The use of this element reduces cost drastically and has a good response. An experiment was conducted through this component which provided better result. The main advantage of designing low pass filter by CMOS is that it offers improvements in design simplicity and programmability when compared to op-amp based structures as well as reduced component count. It has high noise immunity and low static power consumption. Hence the overall efficiency increases as well producing the desired effect.
Analysis and design of a low voltage and low power double tail comparatorUshaswini Chowdary
The document describes the design and analysis of a low-voltage, low-power double-tail comparator. It begins by introducing comparators and their use in analog-to-digital converters. It then discusses challenges in designing high-speed comparators for modern low-voltage CMOS processes. The document analyzes delay in dynamic comparators and presents a new double-tail comparator design that aims to reduce latch delay time without requiring a boosted voltage. It describes the operation of conventional dynamic and double-tail comparators before detailing the proposed comparator's design which uses added control transistors to increase the initial differential output voltage and speed up latch regeneration.
This document discusses the advantages of a 5T SRAM cell compared to a traditional 6T SRAM cell. It summarizes the design and operation of a 5T SRAM cell, which removes one transistor compared to a 6T cell. This reduces power consumption by eliminating the need to charge and discharge one of the bit lines during read and write operations. The document then describes the layout design of a 64-bit 5T SRAM using a 90nm technology node. It compares the performance of this 64-bit 5T SRAM to a 64-bit 6T SRAM in terms of power consumption, layout area, number of transistors, and leakage current.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
7SS52 Distributed Bus Bar Diffrential Protection Relayashwini reliserv
The SIPROTEC 7SS52 numerical protection is a selective, reliable and fast protection for busbar faults and breaker failure in medium, high and extra-high voltage substations with various possible busbar configurations.
The protection is suitable for all switchgear types with iron-core or linearized current transformers. The short tripping time is especially advantageous for applications with high fault levels or where fast fault clearance is required for power system stability.
This document summarizes an improved SRAM design implemented using Cadence. The focus was on developing a simplified design by reducing transistor count and replacing some conventional circuit designs. Key aspects of the SRAM design discussed include the 6T SRAM cell, transistor sizing considerations, precharge circuits, sense amplifiers, write amplifiers, decoders, control circuits including flip-flops and write select generators, and specifying input stimuli using digital vector files. The design aims to increase speed and reduce layout area of the SRAM.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Review on Tunnel Field Effect Transistors (TFET)IRJET Journal
The document discusses Tunnel Field Effect Transistors (TFETs) as a promising alternative to MOSFETs for low power applications. TFETs use band-to-band tunneling as the switching mechanism instead of thermionic emission like in MOSFETs, allowing TFETs to achieve subthreshold slopes lower than 60 mV/decade. The document reviews different TFET structures that have been proposed over time, including heterojunction TFETs that use different materials for the source and channel to facilitate band-to-band tunneling. TFETs are seen as important for continued device scaling as they can help reduce static and dynamic power consumption compared to conventional MOSFETs.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Ground Bounce Noise Reduction in Vlsi CircuitsIJERA Editor
Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce
noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute
to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE
mode transition. FinFET based designs are compared with MOSFET based designs on basis of different
parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software
tool used for simulation and circuit design.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Comparative Analysis and Designing of High Performance and Low Power XNOR Gat...IRJET Journal
This document presents the design and analysis of a low power XNOR gate circuit using a hybrid sleep-stack (MTCMOS) technique. It begins with an introduction to the increasing importance of power reduction in integrated circuits due to device scaling. It then describes the MTCMOS technique, which uses high-Vt sleep transistors to cut off power in standby mode. The document goes on to present the design of a 2-transistor XNOR gate using MTCMOS. Simulation results on a 32nm technology platform show that this design achieves lower power consumption than conventional approaches.
This document proposes a novel dual stack sleep technique for reducing reactivation noise in MTCMOS circuits.
The technique divides existing transistors into two half-sized transistors and adds sleep transistors in parallel to reduce leakage current during sleep mode. During active mode, the sleep transistors and parallel transistors work as a transmission gate to efficiently reconnect power.
Simulation results show the dual stack SCCER flip-flop has an area of 38um^2 and power dissipation of 3.297uW, compared to 22um^2 and 0.327mW for the conventional SCCER flip-flop. The dual stack approach significantly reduces leakage power while maintaining performance during active mode.
Optimization of Threshold Voltage for 65nm PMOS Transistor using Silvaco TCAD...IOSR Journals
This document summarizes research optimizing the threshold voltage (VTH) for a 65nm PMOS transistor using Silvaco TCAD simulation tools. The researchers varied three fabrication factors - gate oxide thickness, channel doping concentration, and channel implantation concentration - in the simulation. The simulation results showed a VTH value of -2.55427V for a 65nm PMOS transistor with a gate oxide thickness of 0.0025um, boron channel doping of 2x1015, and phosphorus implantation of 3.5x1013 atom/cm-1. Thicker gate oxides, higher channel doping, and increased implantation concentrations each caused higher VTH values in the simulation, consistent with theoretical expectations.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The document presents a novel approach called "stacking with sleepy keeper" for reducing leakage power in 65nm CMOS technologies. It combines transistor stacking, sleep transistors, and sleepy keeper techniques. Simulation results show the proposed approach significantly reduces average and static power compared to basic NAND gates and other techniques. For a 2-input NAND gate, the proposed approach with high Vth transistors reduces average power by 97.32% and static power by 99.24% compared to a basic NAND gate. When implemented in an SRAM cell, the proposed approach also improves power, delay, and power-delay product metrics.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Different Leakage Power Reduction Techniques in SRAM Circuits : A State-of-th...IRJET Journal
This document reviews various techniques to reduce leakage power in SRAM circuits, which is a major component of total power consumption as technology scales down. It first describes the different sources of leakage current in CMOS devices like subthreshold leakage, gate induced drain leakage, junction leakage, etc. It then surveys conventional techniques like sleep transistor, forced stack, and sleepy stack that reduce leakage by stacking off transistors in leakage paths. A newer LECTOR technique is described in detail, which introduces leakage control transistors to keep one transistor near cutoff without depending on input voltage. This allows obtaining a path with less leakage between supply and ground. The document concludes leakage reduction will be important for low power memory circuit design in emerging technologies.
The document describes a proposed 9T SRAM cell design with the following key features:
1. It uses a combination of a standard inverter and a single-ended Schmitt trigger inverter to provide high read stability.
2. Transmission gates are used instead of single-pass gates to reduce unnecessary switching during hold mode.
3. A negative assist technique alters the trip voltage of the Schmitt trigger inverter to improve write-1 ability.
4. Multi-threshold CMOS techniques are adopted to reduce leakage power in the proposed 9T SRAM cell.
Simulation results show the proposed cell has better performance than previous 7T, 10T, 11T, ST 9T
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
Design of low power 4 bit full adder using sleepy keeper approacheSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A high speed dynamic ripple carry addereSAT Journals
Abstract Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path; apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools. Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock
switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
Similar to IRJET- A Novel 5 Stage MTCNT Delay Line at 32nm Technology Node (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
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Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
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Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...University of Maribor
Slides from talk presenting:
Aleš Zamuda: Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapter and Networking.
Presentation at IcETRAN 2024 session:
"Inter-Society Networking Panel GRSS/MTT-S/CIS
Panel Session: Promoting Connection and Cooperation"
IEEE Slovenia GRSS
IEEE Serbia and Montenegro MTT-S
IEEE Slovenia CIS
11TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTING ENGINEERING
3-6 June 2024, Niš, Serbia
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024