This document presents a new mesh analytical method for symbolic simulation of linear RLC circuits in the frequency domain. The method formulates the circuit equations as a set of mesh equations that account for both the steady-state impedances of the circuit elements as well as the initialization effects of non-zero initial conditions in the capacitors and inductors. It derives the mesh equations for a simple three-node, three-mesh example circuit and shows that the circuit equations can be expressed in matrix form with impedance matrices representing the steady-state and initialization impedances. The method aims to provide a simple yet robust way to simulate transient responses of linear circuits symbolically in the frequency domain.
Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for ...IDES Editor
Fast delay estimation methods, as compared to
simulation techniques, are needed for incremental
performance-driven layout synthesis. On-chip inductive and
conductive effects are becoming predominant in deep
submicron (DSM) interconnects due to increasing clock
speeds; circuit complexity and interconnect lengths.
Inductance causes noise in the signal waveforms, which can
adversely affect the performance of the circuit and signal
integrity. Elmore delay-based estimation methods, although
efficient, fails to accurately estimate the delay for RLCG
interconnect lines. This paper presents an analytical delay
model, based on first and second moments of RLCG
interconnection lines, that considers the effect of inductance
and conductance for the estimation of delay in interconnection
lines. Simulation results justify the efficacy of the proposed
delay modelling approach.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Report-Implementation of Quantum Gates using VerilogShashank Kumar
It was a project-based work in which I was guided to implement the quantum-based gates which would be equivalent to classical gates So, the project name was "FPGA Implementation of Digital Logic Design using Quantum Computing". Actually, it is to mitigate the problem, since in quantum any NAND based circuit is not shown universal as in the classical it was so tried by using the "IBM Quantum Composer" to make such circuit which would behave as the NAND gate and also reversible in nature as per the quantum physics says and simulated the circuitry using the "Verilog".
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for ...IDES Editor
Fast delay estimation methods, as compared to
simulation techniques, are needed for incremental
performance-driven layout synthesis. On-chip inductive and
conductive effects are becoming predominant in deep
submicron (DSM) interconnects due to increasing clock
speeds; circuit complexity and interconnect lengths.
Inductance causes noise in the signal waveforms, which can
adversely affect the performance of the circuit and signal
integrity. Elmore delay-based estimation methods, although
efficient, fails to accurately estimate the delay for RLCG
interconnect lines. This paper presents an analytical delay
model, based on first and second moments of RLCG
interconnection lines, that considers the effect of inductance
and conductance for the estimation of delay in interconnection
lines. Simulation results justify the efficacy of the proposed
delay modelling approach.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Report-Implementation of Quantum Gates using VerilogShashank Kumar
It was a project-based work in which I was guided to implement the quantum-based gates which would be equivalent to classical gates So, the project name was "FPGA Implementation of Digital Logic Design using Quantum Computing". Actually, it is to mitigate the problem, since in quantum any NAND based circuit is not shown universal as in the classical it was so tried by using the "IBM Quantum Composer" to make such circuit which would behave as the NAND gate and also reversible in nature as per the quantum physics says and simulated the circuitry using the "Verilog".
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Log...IDES Editor
The high-speed dynamic True Single Phase
Clock (TSPC) logic design style offer fully pipelined logic
circuits using only one clock signal, which makes clock
distribution simple and compact. The conversion of simple
logic gates to pipelined TSPC logic gates increases transistor
count since standard cell implementation for a logic function
uses both N-block as well as P-block to remove transparency
between pipelined stages, despite the fact that logic
functions are only implemented with N-block. In this paper
we present a technique in which a TSPC logic cell are
implemented both as cell_N and cell_P cells, where each cell
block is performing a logic function along with only one
type latching operation. Such an implementation allows a
systematic approach for converting un-pipelined circuits to
fully pipelined circuits. The alternate cell_N and cell_P
behaves as dynamic register and removes transparency
between pipelined stages. The appropriate numbers of
dynamic registers are used to equalize stage delays for all
paths and to remove transparency between pipelined stages.
The modified TSPC implementation shows almost 40% to
50% reduction in transistor counts and almost 50%
reduction in clock cycles as compared to worst-case
standard TSPC implementation. The worst-case standard
TSPC implementation assumes that no logic merging is
possible with P-block, since input to any cell appears after
different cycle delays. The modified TSPC logic circuit
implementation preserves all the advantages of standard
TSPC logic implementation and in addition offers the
reduced circuit complexity due to reduced transistor count
per logic cell. The proposed logic design style reduces layout
area and average power consumption as compared to the
standard TSPC pipelined circuit implementation.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
Design of a Low Power and Area Efficient Flip Flop With Embedded Logic Moduleiosrjce
As number of modules per chip is increasing, number of transistors in a chip increases resulting in
increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed
if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. FlipFlop,
which is basic building block, plays a major role in design of complex systems. From the open literature,
Semi Dynamic Flip-Flop (SDFF) and Dual Dynamic Flip-Flops (DDFF) are classic structures which are
efficient for incorporating complex logic functions. In this paper, a new low power and area efficient flip-flop
with Embedded Logic Module (ELM) is proposed. The proposed Flip-Flop reduces 50% to 60% of power
dissipation as compared to conventional flip-flops and delay up to 86% is also reduced. Serial in Parallel out
(SIPO) shift register is designed with the proposed flip-flop which exhibit low power dissipation. The
simulations are done in MENTOR GRAPHICS, Schematic editor, Generic GDK, 130nm technology.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
20 Ideas for your Website Homepage ContentBarry Feldman
Perplexed about what to put on your website home? Every company deals with this tough challenge. The 20 ideas in this presentation should give you a strong starting point.
10 Insightful Quotes On Designing A Better Customer ExperienceYuan Wang
In an ever-changing landscape of one digital disruption after another, companies and organisations are looking for new ways to understand their target markets and engage them better. Increasingly they invest in user experience (UX) and customer experience design (CX) capabilities by working with a specialist UX agency or developing their own UX lab. Some UX practitioners are touting leaner and faster ways of developing customer-centric products and services, via methodologies such as guerilla research, rapid prototyping and Agile UX. Others seek innovation and fulfilment by spending more time in research, being more inclusive, and designing for social goods.
Experience is more than just an interface. It is a relationship, as well as a series of touch points between your brand and your customer. Here are our top 10 highlights and takeaways from the recent UX Australia conference to help you transform your customer experience design.
For full article, continue reading at https://yump.com.au/10-ways-supercharge-customer-experience-design/
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Log...IDES Editor
The high-speed dynamic True Single Phase
Clock (TSPC) logic design style offer fully pipelined logic
circuits using only one clock signal, which makes clock
distribution simple and compact. The conversion of simple
logic gates to pipelined TSPC logic gates increases transistor
count since standard cell implementation for a logic function
uses both N-block as well as P-block to remove transparency
between pipelined stages, despite the fact that logic
functions are only implemented with N-block. In this paper
we present a technique in which a TSPC logic cell are
implemented both as cell_N and cell_P cells, where each cell
block is performing a logic function along with only one
type latching operation. Such an implementation allows a
systematic approach for converting un-pipelined circuits to
fully pipelined circuits. The alternate cell_N and cell_P
behaves as dynamic register and removes transparency
between pipelined stages. The appropriate numbers of
dynamic registers are used to equalize stage delays for all
paths and to remove transparency between pipelined stages.
The modified TSPC implementation shows almost 40% to
50% reduction in transistor counts and almost 50%
reduction in clock cycles as compared to worst-case
standard TSPC implementation. The worst-case standard
TSPC implementation assumes that no logic merging is
possible with P-block, since input to any cell appears after
different cycle delays. The modified TSPC logic circuit
implementation preserves all the advantages of standard
TSPC logic implementation and in addition offers the
reduced circuit complexity due to reduced transistor count
per logic cell. The proposed logic design style reduces layout
area and average power consumption as compared to the
standard TSPC pipelined circuit implementation.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
Design of a Low Power and Area Efficient Flip Flop With Embedded Logic Moduleiosrjce
As number of modules per chip is increasing, number of transistors in a chip increases resulting in
increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed
if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. FlipFlop,
which is basic building block, plays a major role in design of complex systems. From the open literature,
Semi Dynamic Flip-Flop (SDFF) and Dual Dynamic Flip-Flops (DDFF) are classic structures which are
efficient for incorporating complex logic functions. In this paper, a new low power and area efficient flip-flop
with Embedded Logic Module (ELM) is proposed. The proposed Flip-Flop reduces 50% to 60% of power
dissipation as compared to conventional flip-flops and delay up to 86% is also reduced. Serial in Parallel out
(SIPO) shift register is designed with the proposed flip-flop which exhibit low power dissipation. The
simulations are done in MENTOR GRAPHICS, Schematic editor, Generic GDK, 130nm technology.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
20 Ideas for your Website Homepage ContentBarry Feldman
Perplexed about what to put on your website home? Every company deals with this tough challenge. The 20 ideas in this presentation should give you a strong starting point.
10 Insightful Quotes On Designing A Better Customer ExperienceYuan Wang
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VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running
different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
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yahoo journals, bing journals, International Journal of Computational Engineering Research, Google journals, hard copy of Certificate,
journal of engineering, online Submission
Modeling of solar array and analyze the current transientEditor Jacotech
Spacecraft bus voltage is regulated by power
conditioning unit using switching shunt voltage regulator having
solar array cells as the primary source of power. This source
switches between the bus loads and the shunt switch for fine
control of spacecraft bus voltage. The effect of solar array cell
capacitance [5][6] along with inductance and resistance of the
interface wires between solar cells and power conditioning
unit[1], generates damped sinusoidal currents superimposed on
the short circuit current of solar cell when shunted through
switch. The peak current stress on the shunt switch is to be
considered in the selection of shunt switch in power conditioning
unit. The analysis of current transients of shunt switch in PCU
considering actual spacecraft interface wire length by
illumination of solar panel (combination of series and parallel
solar cells) is difficult with hardware simulation. Software
simulation by modeling solar cell is carried out for a single string
(one parallel) in Pspice [6]. Since in spacecrafts number of
parallels and interface cable length are variable parameters the
analysis of current transients of shunt switch is carried out by
modeling solar array with the help of solar cell model[6] for the
actual spacecraft condition.
Modeling of solar array and analyze the current transient response of shunt s...Editor Jacotech
Spacecraft bus voltage is regulated by power
conditioning unit using switching shunt voltage regulator having
solar array cells as the primary source of power. This source
switches between the bus loads and the shunt switch for fine
control of spacecraft bus voltage. The effect of solar array cell
capacitance [5][6] along with inductance and resistance of the
interface wires between solar cells and power conditioning
unit[1], generates damped sinusoidal currents superimposed on
the short circuit current of solar cell when shunted through
switch. The peak current stress on the shunt switch is to be
considered in the selection of shunt switch in power conditioning
unit. The analysis of current transients of shunt switch in PCU
considering actual spacecraft interface wire length by
illumination of solar panel (combination of series and parallel
solar cells) is difficult with hardware simulation. Software
simulation by modeling solar cell is carried out for a single string
(one parallel) in Pspice [6]. Since in spacecrafts number of
parallels and interface cable length are variable parameters the
analysis of current transients of shunt switch is carried out by
modeling solar array with the help of solar cell model[6] for the
actual spacecraft condition.
An Explicit Approach for Dynamic Power Evaluation for Deep submicron Global I...IDES Editor
As the VLSI process technology is shrinking to the
nanometer regime, power consumption of on-chip VLSI
interconnects has become a crucial and an important issue.
There are several methodologies proposed to estimate the onchip
power consumption using Voltage Mode Signaling
technique (VMS). But the major drawback of VMS is that it
increases the power consumption of on-chip interconnects
compared to current mode signaling (CMS). A closed form
formula is, thus, necessary for current mode signaling to
accurately estimate the power dissipation in the distributed
line. In this paper, we derived an explicit dynamic power
formula in S-domain based on Modified Nodal Analysis
(MNA) formulation. The usefulness of our approach is that
dynamic power consumption of an interconnect line can be
estimated accurately and efficiently at any operating
frequency. By substituting s=0 in the vector of node voltages
in our model results similar solution as that of Bashirullah
et. al. Comparison of simulation results with other
established models justifies the accuracy of our approach.
Modeling and test validation of a 15 kV - 24 MVA superconducting fault curren...Franco Moriconi
High-power short-circuit test results and numerical simulations of a 15kV–24MVA distribution-class High Temperature Superconductor (HTS) Fault Current Limiters (FCL) are presented and compared in this paper. The FCL design was based on the nonlinear inductance model here described, and the device was tested at 13.1kV line-to-line voltage for prospective fault currents up to 23kArms, prior to its installation in the electric grid. Comparison between numerical simulations and fault test measurements show good agreement. Some simulations and field testing results are depicted. The FCL was energized in the Southern California Edison grid on March 9, 2009.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
1. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
Symbolic Simulation By Mesh Method Of Complementary Circuitry
I. I. OKONKWO*, P. I. OBI *, G. C CHIDOLUE**, AND S. S. N. OKEKE**
P. G. Scholars In Dept. Of Electrical Engineering, Anambra State University, Uli. Nigeria*
Professors In Dept. Of Electrical Engineering, Anambra State University, Uli. Nigeria**
Abstract
Transient simulation of electric network circuits elements [2 – 4]. Symbolic formulation grows
with non – zero initial values could be quite exponentially with circuit size and it limits the
challenging even in frequency domain, especially maximum analyzable circuit size and also makes
when transient equation formulation involves more difficult, formula interpretation and its use in
vectorial sense establishment of the initialization design automation application [5 – 10]. This is
effect of the storage elements. In this paper, we usually improved by using semisymbolic formulation
derived a robust laplace frequency transient mesh which is symbolic formulation with numerical
equation which takes care of the vectorial sense of equivalent of symbolic coefficient. Other methods of
these initialization effects by mere algebraic simplification include simplification before
formulation. The result of the new derived generation (SBG), simplification during generation
transient mesh equation showed promising SDG, and simplification after generation (SAG) [11 –
conformity with the existing simpowersystem 16].
simulation tool with just knowledge of the steady Symbolic response formulation of electrical
state current and not the state variables. circuit can classified broadly as modified nodal
analysis (MNA) [17], sparse tableau formulation and
Keyword: transient simulation, mesh equation, state variable formulations. The state variable method
state variables, and non – zero initialization. were developed before the modified nodal analysis, it
involves intensive mathematical process and has
1 INTRODUCTION major limitation in the formulation of circuit
A single run of a conventional simulation equations. Some of the limitations arise because the
provide limited information about the behaviour of state variables are capacitor voltages and inductor
electrical circuit. It determines only how the circuit currents [18]. The tableau formulation has a problem
would behave for a single initial, input sequence and that the resulting matrices are always quite large and
set of circuit parameter characterizing condition. the sparse matrix solver is needed. Unfortunately, the
Many cad tasks require more extensive information structure of the matrix is such that coding these
than can be obtained by a single simulation run. For routine are complicated. MNA despite the fact that its
example the formal verification of a design requires formulated network equation is smaller than tableau
showing that the circuit will behave properly for all method, it still has a problem of formulating matrices
possible initial start sequences that will detect a given that are larger than that which would have been
set of faults, clearly conventional simulation is of obtained by pure nodal formulation [19].
little use for such task [1]. In this paper a new mesh analytical method
Some of these tasks that cannot be solved is introduced which may be used on linear or
effectively by conventional simulation have become linearized RLC circuit and can be computer
tractable by extending the simulation to operate a applicable and user friendly. The simplicity of the
symbolic domain. Symbolic simulation involves new transient mesh formulation lies in the fact that
introducing an expanded set of signal values and minimal mesh index is enough to formulate transient
redefining the basic simulation functions to operate equation and also standard method of building steady
over this expanded set. This enables the simulator state mesh impedance bus is just needed to build the
evaluate a range of operating conditions in a single two formulated impedance buses that are required to
run. By linearizing the circuits with lumped formulate the new transient mesh equation.
parameters at particular operating points and Simplicity, compactness and economy are the
attempting only frequency domain analysis, the advantages of the newly formulated transient mesh
program can represent signal values as rational equation.
functions in the s ( continuous time ) or z (discrete
time) domain and are generated as sums of the 2 New Transient Mesh Equation.
products of symbols which specify the parameters of Mesh analysis may not be as powerful as the
356 | P a g e
2. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
nodal analysis in power system because of a little bit
of application complication in circuits with multiple E1 (s) E 3 (s) E5 (s) [I1 (s) I 2 (s)][R1
branches in between two nodes, when power system 1 1
is characterized with short line model, mesh analysis sL1 ] I1 (s)[R1 sL1 ] [I1 (s)
C1 C1
become a faster option especially when using laplace
1
transient analysis. The new mesh method sees a linear I 3 (s)][R5 sL5 ] [I1 (0) I 2 (0)]L1
RLC transient network in frequency domain as one C5
that sets up complementary circuit by the initial dc Vc1(0)
[I1 (0) I 3 (0)]L5 I1 (0)L3
quantities at transient inception. With this mesh s
method, the complimentary circuit sets its resultant Vc3 (0) Vc5 (0)
residual quantities (voltage drop) which complement 0 3
s s
the mesh transient voltage source. but
The constitutional effect of the initial
quantities at the transient inception combine with the
1
Vck ( 0 ) i k ( 0 ) 4
voltage sources on the RLC linear circuits (1) is s1Ck
setting up of two identifiable impedance diagrams. Where ik (0) is the initial branch current and s1 is the
One impedance diagram is the normal laplace steady state frequency.
transformed impedance diagram of the original circuit
elements, in this paper it is called the auxiliary
transient Impedance diagram. The other impedance
diagram is due to non zero transient initialization
effect of the storage elements and it is called the
complementary transient impedance diagram in this
paper.
Z(s)I(s) E(s) ZC(s)IC(s) 1
Where Z(s) is the Auxiliary impedance bus, s –
domain equivalent of steady state mesh impedance
matrix, Zc(s) is the s – domain complementary
impedance bus, it is the storage element driving point
impedance bus due to transient inception effect, I(s) is
the laplace mesh current vector and Ic(s) is the initial Figure 1: Three node, three mesh linear transient
dc mesh current vector, equivalent to the steady state electric circuit.
mesh current vector at the transient inception.
substituting branch current in (4) with appropriate
2.1 Derivation mesh currents to get branch capacitor voltage drops in
The newly transient mesh equation may be terms of mesh currents,
derived by considering a simple three node, three 1
Vc1(0) [I1 (0) I 2 (0)]
mesh linearized RLC circuit, fig. 1, if Kirchhoff’s s1C1
voltage law is applied on the various meshes then,
Vc5 (0) [I1 (0) I 3 (0)]
1
5
s1C5
From mesh 1
1
d Vc3 (0) I1 (0)
E1 (t) {R1 [I1 (t) I 2 (t)] L1 [I1 (t) I 2 (t)] s1C3
dt
1
C1
[I1 (t) I 2 (t)]dt E5 (t) {R5 [I1 (t) I 3 (t)] Substituting equation (5) in (3) and simplifying to get,
I1 (s)[Z1 (s) Z3 (s) Z5 (s)] I 2 (s)Z1 (s)
d 1
L5
dt
[I1 (t) I 3 (t)]
C5 [I (t) I
1 3 (t)]dt E 3 (t) I 3 (s)Z 5 (s) [E1 (s) E 3 (s) E5 (s)]
1 1 1
I1 (0){[L1 ] [L3 ] [L5 ]}
d
{R 3 I1 (t) L3 I1 (t)
1
I (t)dt 0
1 2 ss1C1 ss1C3 ss1C5
dt C3
I 2 (0)[L1
1
] I 3 (0)[L5
1
] 6
ss1C1 ss1C5
then,
taking the laplace transform of equation (2) to get,
357 | P a g e
3. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
I1 (s)[Z1 (s) Z3 (s) Z5 (s)] I 2 (s)Z1 (s) Z( c )11 ( s ) Z( c )1 (s) Z( c )3 (s) Z( c )5 (s)
I 3 (s)Z 5 (s) [E1 (s) E 3 (s) E5 (s)] Z( c )22 ( s ) Z( c )1 (s) Z( c )2 (s) Z( c )4 (s)
I1 (0)[Z(C)1 (s) Z(C)3 (s) Z(C)5 (s)] Z( c )33 ( s ) Z( c )4 (s) Z( c )5 (s) Z( c )6 (s) 13
I 2 (0)Z(C)1 (s) I 3 (0)Z(C)5 (s) 7 Z( c )12 ( s ) Z( c )21 ( s ) Z( c )1 ( s )
where Z( c )13 ( s ) Z( c )31 ( s ) Z( c )5 ( s )
Z( c )k [Lk
1
] 8 Z( c )23 ( s ) Z( c )32 ( s ) Z( c )4 ( s )
ss1Ck
Z(c)k(s) is the dc transient driving point impedance, Lk E(M)1 (s) E1 (s) E3 (s) E5 (s)
and Ck are the k – th branch inductance and
capacitance respectively. E(M)2 (s) E1 (s) E2 (s) E4 (s) 14
For mesh 2 E(M)3 (s) E4 (s) E5 (s) E6 (s)
Similarly, Kirchhoff’s voltage law may be applied in
mesh 2 and simplified as in mesh 1 to get ,
I 2 (s)[Z1 (s) Z2 (s) Z4 (s)] I1 (s)Z1 (s)
K
I 3 (s)Z 4 (s) [ E1 (s) E 2 (s) E 4 (s)] E(M)m (s) E (s)k 15
I1 (0)[Z(C)1 (s) Z(C)2 (s) Z(C)4 (s)] k 1
where m = 1,2 – – – M–th mesh and also k = 1,2 – –
I1 (0)Z(C)1 (s) I 3 (0)Z(C)4 (s) 9 – K–th branch incident on the m–th mesh.
For mesh 3
Similarly, Kirchhoff’s voltage law may be applied in
mesh 3 and simplified as in mesh 1 to get
I 3 (s)[Z 4 (s) Z5 (s) Z6 (s)] I 2 (s)Z 4 (s)
I1 (s)Z 5 (s) [ E 4 (s) E5 (s) E6 (s)]
I 3 (0)[Z(C)4 (s) Z(C)5 (s) Z(C)6 (s)]
I 2 (0)Z(C)4 (s) I1 (0)Z(C)5 (s) 10
Equations (6), (8) and (8) may be combined to form s
– domain mesh matrix equation as follows,
Z11 ( s ) Z12 ( s ) Z13 ( s ) I1 ( s ) E( m )1 ( s )
Z21 ( s ) Z22 ( s ) Z23 ( s ) I 2 ( s ) E( m )2 ( s )
Z ( s ) Z ( s ) Z ( s ) I ( s ) E
31 32 33 3 ( m )3 ( s )
=
Z( c )11 ( s ) Z( c )12 ( s ) Z( c )13 ( s ) I1 ( 0 ) Figure 2: s – domain auxiliary circuit diagram for
Z( c )21 ( s ) Z( c )22 ( s ) Z( c )23 ( s ) I 2 ( 0 ) 11 transient nodal analysis.
Z( c )31 ( s ) Z( c )32 ( s ) Z( c )33 ( s ) I 3 ( 0 ) 2.2 Generalized Matrix Form for Transient Nodal
Equation
where Equation (11) may be used to generalize an
Z11 ( s ) Z1 (s) Z3 (s) Z5 (s) equation in the matrix form for transient mesh analysis
of M th mesh electrical circuit, thus
Z22 ( s ) Z1 (s) Z 2 (s) Z4 (s)
Z11 (s) Z12 (s) Z1m (s) I1 (s) E1 (s)
Z33 ( s ) Z4 (s) Z5 (s) Z6 (s) 12
Z21 (s) Z22 (s) Z2m (s) I 2 (s) E 2 (s)
Z12 ( s ) Z21 ( s ) Z1 ( s )
Z13 ( s ) Z31 ( s ) Z5 ( s )
Z (s) Z (s) Z (s) I (s) E (s)
Z23 ( s ) Z32 ( s ) Z 4 ( s ) m1 m2 mm m m
=
358 | P a g e
4. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
Z(C)11 (s) Z(C)12 (s) Z(C)1m (s) I1 (0) Z(C)(s) is laplace frequency domain dc driving point
impedance bus, the impedance bus could be built
Z(C)21 (s) Z(C)22 (s) Z(C)2m (s) I 2 (0)
16 from fig 3 using any standard method of building an
impedance bus when the branch dc driving point
Z(C)m1 (s) Z(C)m2 (s) Z(C)mm (s) I (0) impedance Z(C)k(s) of the circuit is evaluated from
m
equation (8). In this paper it is called the s – domain
complementary admittance bus.
The variables of equation (16) are defined in the
compact equation of section 2.
I1 (s) E1 (s)
I 2 (s) E 2 (s)
I(s) , E(s)
I (s) E (s)
m m
I1 (0)
I 2 (0)
I c (s) I(0) 20
I (0)
m
I(s) and E(s) are the vector of mesh transient current
and mesh voltage source (vectorial sum) in laplace
frequency domain respectively, while Ic(s)is equal to
I(0) and is the steady state mesh current at the instant
of fault inception. Hence Ic(s) is and I(0) will be used
interchangeably in this paper.
Figure 3: s – domain complementary circuit diagram 3 ANALYSIS PROCEDURES
for mesh analysis. 1. Solve for the initial dc mesh current from
steady state for example
2.3 Generalized Compact Form For Transient ZI E 21
Nodal Equation where Z is the steady state mesh impedance bus, I is
The generalized compact form of the the steady mesh current vector, E is the mesh sum
equation 16 is thus as follows, voltage source vector.
2. Transform all the branch voltage sources to
Z(s)I(s) E(s) Z(C)(s)I(C)(s) 17 laplace equivalent and find the mesh sum (14) and
eventually convert to vector form (20).
Z11 (s) Z12 (s) Z1m (s)
3. Draw the auxiliary laplace impedance
Z21 (s) Z22 (s) Z2m (s)
Z(s) 18 diagram as in Fig 2. by converting all the branch
elements to laplace equivalent, then build the laplace
Z (s) Z (s) Z (s) impedance bus from the impedance diagram by using
m1 m2 mm any of the standard method of building steady state
Z(s) is laplace frequency domain impedance bus, the impedance bus.
impedance bus have the same formulation with the 4. From the branch storage elements formulate
common steady state mesh impedance bus only that the newly derived branch dc transient driving point
in this equation, the branch impedances are translated impedances (8), and then draw the complementary
to laplace frequency domain. In this paper it is called impedance diagram as in fig. 3. from the diagram
the s – domain auxiliary impedance bus. build the complementary impedance bus (19) with
any of the standard method of building steady state
also impedance bus.
Z(C)11 (s) Z(C)12 (s) Z(C)1m (s) 5. Form equation (16) and solve for I(s) using
Cramer’s rule.
Z(C)21 (s) Z(C)22 (s) Z(C)2m (s)
Zc (s)
19 6. Transform I(s) to time domain equivalent
using laplace inverse transform. Eg. in Matlab,
Z(C)m1 (s) Z(C)m2 (s) Z(C)mm (s)
359 | P a g e
5. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
In this paper the transient mesh currents
I( t ) ilap I( s ))
( 22 were simulated by using the described formulation (s
– domain mesh equation by method of
complementary circuitry). Analysis procedures of
From this branch currents could easily be obtained at
section 3 were used to calculate the s – domain
any instant of the transient.
rational functions of the mesh currents I(s). The
obtained s – domain rational functions were
4 TEST CIRCUIT transformed to close form continuous time functions
An earth faulted 100kV - double end fed using laplace inverse transformation. Discretization of
70% series compensated 100km single transmission the close form continuous time functions were done
line was used for verification of the formulated s – to plot the mesh current response graphs.
domain transient mesh equation. In this analysis
compensation beyond fault was adopted and fault 5.2 Simpower Simulation of Test Circuit
position was assumed to be 40%. To validate the formulated transient mesh
equation, a simulation of the earth faulted line end
series compensated single line transmission was
performed using matlab simpowersystem software to
obtain the circuit transient mesh current responses.
Figure 4: earth faulted single line with compensation Results were compared with the responses obtained
beyond fault from the simulations using the formulated transient
mesh equation.
Test Circuit Parameter
Generator 1 6 Results
E1 (t)=10x104sin(t), ZG1=(6+j40), S=1MVA Mesh current response were simulated using
Generator 2 the formulated mesh equation and also using
E2 (t)=0.8|E1|sin (t+450), ZG2=(4+j36), S=1MVA simpowersystem package, all simulation were done
Line Parameter using Matlab 7.40 mathematical tool. Simulated
Rs=0.075 /km, Ls=0.04875 H/km responses by these methods for the earth faulted
Gs=3.75*10-8 mho/km, Cs=8.0x10-9F/km double end fed single line transmission were obtained
Line length=100 km and shown in fig 6 through fig 13. Mesh currents
Fault position 40% C1=70%compensation. were taken for various simulating conditions.
Simulating conditions included; zero initial condition,
4.1 Modeling non – zero initial condition, high resistive (1000)
A lumped parameter was adopted as a model fault but at zero initial condition, and 1 sec.
for the test circuit. It was assumed that compensation simulation. All simulations were done, except
protection had not acted as such the compensation otherwise stated on 100km line at 40% fault position
was of constant capacitance. More so, the model is and 5 earth resistive fault. Sampling interval for the
characterized with constant parameter, shunt formulated equation simulation is 0.0005 sec, while
capacitance and shunt conductance of transmission that of the simpowersystem simulation is at 0.00005
line are neglected. The equivalent circuit of the test sec. The overall result showed almost 100%
circuit is below fig 5. conformity between new mesh symbolic formulation
and the simpowersystem simulation.
7 Conclusions
Simulation software has been formulated for
transient simulation of RLC circuits initiating from
steady state. The simulation software is especially
useful for power circuits that are modeled with short
Figure 5: single line with compensation beyond earth line parameter. The result of the simulation of this
fault equivalent circuit (short line model). new symbolic mesh software showed promising
conformity with the existing simpowersystem
5 Transient Simulation package and has the advantage of being able to
5.1 Symbolic Simulation with Formulated simulate complex value initial conditions and also
Equation sets the directions and the senses of the state variables
automatically.
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6. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
Test Circuit Simulated Mesh Voltage Response
Graphs:
All graph are plotted except otherwise
stated, 100 km Line, Compensation 70% Fault
Position=40%, And 5 Resistive Earth Fault.
Figure 9: Simulation of Mesh Current versus Time;
Initial Conditions, 0.013 Sec of Steady State Run.
Figure 6: Simulation Of Mesh Current Versus time ;
0% Initial Condition.
Figure 10: Simulation Of Mesh Current Versus
Time; 0% Initial Condition, and 1000 Resistive
Earth Fault.
Figure 7: Simulation Of Mesh Current Versus Time ;
0% Initial Condition.
Figure 11: Simulation Of Mesh Current Versus Time;
0% Initial Condition, and 1000 Resistive Earth Fault.
Figure 8: Simulation of Mesh Current versus Time;
Initial Conditions, 0.013 Sec of Steady State Run.
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7. I. I. Okonkwo, P. I. Obi, G. C Chidolue, S. S. N. Okeke / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.356-363
Rodríguez-Vázquez ―Comparison Of Matroid
Intersection Algorithms For Large Circuit
Analysis‖ Proc. Xi Design Of Integrated
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Sitges (Barcelona), November 1996.
[6] A. Rodríguez-Vázquez, F.V. Fernández, J.L.
Huertas And G. Gielen, ―Symbolic Analysis
Techniques And Applicaitons To Analog
Design Automation‖, IEEE Press, 1996.
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Figure 12: Simulation Of Mesh Current Versus Time ;
Cairo, Egypt, 2007.
0% Initial Condition.
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