This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
This document discusses using a unified power flow controller (UPFC) with an adaptive neuro-fuzzy controller to damp low frequency oscillations (LFO) in a power system. It presents a linearized model of a single machine connected to an infinite bus power system with a UPFC. The UPFC consists of two voltage source converters that can independently control reactive power and the voltage amplitude and phase to influence power flow. Simulation results show the neuro-fuzzy controller provides better damping of LFO disturbances compared to a conventional lead-lag controller for the UPFC.
The document describes a technique called Local Common Mode Feedback (LCMFB) that can be applied to operational transconductance amplifiers (OTAs) to improve their performance. Applying LCMFB to the conventional OTA structure provides significant increases in gain-bandwidth and slew rate without increasing static power consumption or requiring much additional silicon area. LCMFB works by connecting the gates of the OTA's active load transistors to a common node with matched resistors, forming a feedback loop that enhances the amplifier's characteristics and versatility. The proposed OTA architecture with LCMFB can achieve high slew rates and gain bandwidth needed for wireless applications while keeping low static power, addressing demands for improved performance in battery-powered systems.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
The document summarizes the evolution of voltage regulators from early voltage divider circuits to modern system on chip applications. Key developments include:
1) Early voltage divider circuits were found to not provide constant voltage and had limitations, prompting the development of feedback-based voltage regulators.
2) Modern voltage regulators consist of three main components - a feedback circuit, error amplifier, and pass element - to maintain a constant output voltage despite varying inputs or loads.
3) MOSFETs came to be used as the pass element over BJTs due to advantages like lower dropout voltage, power loss, noise, and fabrication area, making regulators more efficient for portable applications.
This document describes the design of an enhancement mode GaAs PHEMT LNA with a linearity-controllable and phase-matched mitigated bypass switch, as well as a differential active mixer. The LNA operates in three modes - high linearity, low linearity, and bypass - to optimize performance based on signal strength. A novel phase shift element in the bypass switch maintains phase matching between LNA modes. The low-power differential mixer incorporates an active balun and buffer amplifier. Measurements show the LNA and mixer meet specifications for wireless applications.
A Modified Bridgeless Converter for SRM Drive with Reduced Ripple CurrentIJPEDS-IAES
A Single Phase Switched Reluctance Motor is more popular in many
industrial purposes for high speed applications because of its robust and
rugged construction. For low cost and variable speed drive applications SRM
are widely used.Due to doubly salient structure of motor, the torque
pulsations are high when compared to other sinusoidal machines. The major
drawback in using SRM drive is torque pulsations and increased number of
switching components. In order to overcome these drawbacks, a bridgeless
Single Ended Primary Inductor Converter (SEPIC) is proposed. The major
advantages of this converter are continuous output current, smaller voltage
ripple and reduced semiconductor current stress when compared to the
conventional SEPIC converter. The ripple free input current is obtained by
using additional winding of input inductor and auxiliary capacitors. To
achieve high efficiency, active power factor correction circuits (PFC) are
employed to precise the power factor. Further, the unity power factor can be
obtained by making the input current during switching period proportional to
the input voltage is proposed. The proposed system consists of reduced
components and it is also capable of reducing the conduction losses. The
working principles and the waveforms of proposed converter are analyzed.
To analyze the circuit operation, theoretical analysis and simulation results
are provided. Finally, the comparison between the waveforms of
conventional SEPIC and proposed system is presented by using
MATLAB/Simulink tools.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
This document discusses using a unified power flow controller (UPFC) with an adaptive neuro-fuzzy controller to damp low frequency oscillations (LFO) in a power system. It presents a linearized model of a single machine connected to an infinite bus power system with a UPFC. The UPFC consists of two voltage source converters that can independently control reactive power and the voltage amplitude and phase to influence power flow. Simulation results show the neuro-fuzzy controller provides better damping of LFO disturbances compared to a conventional lead-lag controller for the UPFC.
The document describes a technique called Local Common Mode Feedback (LCMFB) that can be applied to operational transconductance amplifiers (OTAs) to improve their performance. Applying LCMFB to the conventional OTA structure provides significant increases in gain-bandwidth and slew rate without increasing static power consumption or requiring much additional silicon area. LCMFB works by connecting the gates of the OTA's active load transistors to a common node with matched resistors, forming a feedback loop that enhances the amplifier's characteristics and versatility. The proposed OTA architecture with LCMFB can achieve high slew rates and gain bandwidth needed for wireless applications while keeping low static power, addressing demands for improved performance in battery-powered systems.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
The document summarizes the evolution of voltage regulators from early voltage divider circuits to modern system on chip applications. Key developments include:
1) Early voltage divider circuits were found to not provide constant voltage and had limitations, prompting the development of feedback-based voltage regulators.
2) Modern voltage regulators consist of three main components - a feedback circuit, error amplifier, and pass element - to maintain a constant output voltage despite varying inputs or loads.
3) MOSFETs came to be used as the pass element over BJTs due to advantages like lower dropout voltage, power loss, noise, and fabrication area, making regulators more efficient for portable applications.
This document describes the design of an enhancement mode GaAs PHEMT LNA with a linearity-controllable and phase-matched mitigated bypass switch, as well as a differential active mixer. The LNA operates in three modes - high linearity, low linearity, and bypass - to optimize performance based on signal strength. A novel phase shift element in the bypass switch maintains phase matching between LNA modes. The low-power differential mixer incorporates an active balun and buffer amplifier. Measurements show the LNA and mixer meet specifications for wireless applications.
A Modified Bridgeless Converter for SRM Drive with Reduced Ripple CurrentIJPEDS-IAES
A Single Phase Switched Reluctance Motor is more popular in many
industrial purposes for high speed applications because of its robust and
rugged construction. For low cost and variable speed drive applications SRM
are widely used.Due to doubly salient structure of motor, the torque
pulsations are high when compared to other sinusoidal machines. The major
drawback in using SRM drive is torque pulsations and increased number of
switching components. In order to overcome these drawbacks, a bridgeless
Single Ended Primary Inductor Converter (SEPIC) is proposed. The major
advantages of this converter are continuous output current, smaller voltage
ripple and reduced semiconductor current stress when compared to the
conventional SEPIC converter. The ripple free input current is obtained by
using additional winding of input inductor and auxiliary capacitors. To
achieve high efficiency, active power factor correction circuits (PFC) are
employed to precise the power factor. Further, the unity power factor can be
obtained by making the input current during switching period proportional to
the input voltage is proposed. The proposed system consists of reduced
components and it is also capable of reducing the conduction losses. The
working principles and the waveforms of proposed converter are analyzed.
To analyze the circuit operation, theoretical analysis and simulation results
are provided. Finally, the comparison between the waveforms of
conventional SEPIC and proposed system is presented by using
MATLAB/Simulink tools.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Interleaved digital power factor correction based on the sliding mode approachLeMeniz Infotech
Interleaved Digital Power Factor Correction Based on the Sliding-Mode Approach
This study describes a digitally controlled power factor correction (PFC) system based on two interleaved boost converters operating with pulsewidth modulation (PWM). Both converters are independently controlled by an inner control loop based on a discrete-time sliding-mode (SM) approach that imposes loss-free resistor (LFR) behavior on each cell. The switching surface implements an average current-mode controller so that the power factor (PF) is high. The SM-based digital controller is designed to operate at a constant switching frequency so that the interleaving technique, which is recommended for ac-dc power conversion systems higher than 1 kW, can be readily applied. An outer loop regulates the output voltage by means of a discrete-time proportional-integral (PI) compensator directly obtained from a discrete-time small-signal model of the ideal sliding dynamics. The control law proposed has been validated using numerical simulations and experimental results in a 2-kW prototype.
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Web : http://ieeemaster.com
Web : http://ieeemaster.com/power-electronics-ieee-projects-2016-2017/
Web : http://ieeemaster.com/power-system-ieee-projects-2016-2017/
Address: 36, 100 Feet Road(Near Indira Gandhi Statue), Natesan Nagar, Pondicherry-605 005
Contact numbers: +91 95663 55386, 99625 88976 (0413) 420 5444
Mail : projects@lemenizinfotech.com
Mobile : 9566355386 / 9962588976
Hardware Implementation of Single Phase Power Factor Correction System using ...IAES-IJPEDS
Rapid increase of consumers in electronics devices and the use of mains rectification circuits inside these electronic devices is the root cause of mains harmonic distortion. Automatic power factor correction techniques can be applied to the industries, power systems and households to make them stable inturns increases the efficiency of system as well as the apparatus. This paper deals with the hardware design of active power factor correction circuit employing boost converter which is used to boost the DC voltages with a controller based on PID control strategy. The pulses given to power switches by pulse width modulation techniques generated by utilizing micro-controller board, Arduino thus obviating the need of complex hardware circuitry. MATLAB/SIMULINK was used to design and tune the PID controller parameters. The simulation results are matching with the predictions and the same was implemented as hardware. The waveforms various test points and across capacitors were obtained, studied and compared with the theoretical waveforms and are found to be in precise proximity of theoretical waveforms.
Engineering Research Publication
Best International Journals, High Impact Journals,
International Journal of Engineering & Technical Research
ISSN : 2321-0869 (O) 2454-4698 (P)
www.erpublication.org
This paper presents a PFC (Power Factor Correction) Cuk converter fed BLDC (Brushless DC) motor drive and the speed of BLDC motor is controlled using fuzzy logic implementation. The PFC converters are employed to enhance the power quality. The Brushless DC motor speed is under the control of DC-bus voltage of VSI-Voltage Source Inverter in which switching of low frequency is used. This helps in the electronic commutation of BLDC motors thus decreasing the switching losses in VSI. A DBR (Diode Bridge Rectifier) next to the PFC Cuk converter controls the voltage at DC link maintaining unity power factor. The characteristics of Cuk converter in four dissimilar modes of operation are studied such as continuous and discontinuous conduction modes (CCM and DCM) respectively. The entire system is simulated using Matlab/Simulink software and the simulation results are reported to verify the performance investigation of the proposed system.
Novel pwm modulation technique for minimizing circulation current and zero cr...IAEME Publication
This document discusses novel PWM modulation techniques for minimizing circulation current and zero crossing distortion in dual buck inverters. It begins by introducing a dual buck inverter topology and discusses traditional and improved bipolar PWM methods. While the improved method eliminates circulating current, it results in significant current distortion near zero crossings due to operating in discontinuous conduction mode. The document then proposes a novel nonlinear bipolar PWM method that provides a 0% duty cycle at zero crossings to improve the current and reduce distortion. Simulation results show the proposed method reduces THD compared to the improved bipolar PWM.
Loss free resistor-based power factor correction using a semi-bridgeless boos...LeMeniz Infotech
Loss free resistor-based power factor correction using a semi-bridgeless boost rectifier in sliding-mode control
To Get this projects Call : 9566355386 / 99625 88976
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This paper presents parameters analysis of 4-level capacitor-clamped boost converter with hard-switching and soft-switching implementation. Principally, by considering the selected circuit structure of the 4-level capacitor-clamped boost converter and appropriate pulse width modulation (PWM) switching strategy, the overall converter volume able to be reduced. Specifically, phase-shifted of 120° of each switching signal is applied in the 4-level capacitor-clamped boost converter in order to increase the inductor current ripple frequency, thus the charging and discharging times of the inductor is reduced. Besides, volume of converters is greatly reduced if very high switching frequency is considered. However, it causes increasing of semiconductor losses and consequently the converter efficiency is affected. The results show that the efficiency of 2-level conventional boost converter and 4-level capacitor-clamped boost converter are 98.59% and 97.67%, respectively in hard-switching technique, and 99.31% and 98.15%, respectively in soft-switching technique. Therefore, by applying soft-switching technique, switching loss of the semiconductor devices is greatly minimized although high switching frequency is applied. In this study, passive lossless snubber circuit is selected for the soft-switching implementation in the 4-level capacitor-clamped boost converter. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation.
Development of a Single Stage C-Band Pulsed Power Amplifier for RADAR Transmi...somandal88
Abstract— This paper presents the design and development of
a single stage solid state pulse power amplifier(SS-PPA)
working at 7.23 GHz ± 100 MHz frequency by using hybrid technology. The amplifier is designed to achieve maximum
power gain with medium output power by adopting
simultaneous conjugate matching procedure. Commercial
available packaged pseudomorphic high electron mobility
transistor (pHEMT) FPD6836P70 (from RFMD) is used for
designing the amplifier. A pulse aggregate card has been developed to provide pulse bias. Plated through hole (PTH)
technique is used for good high frequency grounding. At room
ambient temperature, the measured peak output power from
the prototype amplifier is 18.31 dBm for 8 dBm input driving
power, measuring 10.31 dB gain. We present a description of
the design of the amplifier, its simulated and measured results
and their comparison with desired specifications.
This paper presents the new generation of advanced gate driver circuit based on IR2110 device for a Single-Phase Matrix Converter (SPMC) circuit topology that uses MOSFETs or IGBTs switches. The new generation of gate drive circuit uses less number of components, since a single IR2110 device can drive two power switches, thus reduce power losses and minimize the complexity of conventional circuit. An additional isolation of the upper and lower sides of IR2110 device features additional protection to the proposed gate drive system. As a result, the proposed gate drive circuit just uses four IR2110 gate drives in order to control eight switches of SPMC circuit, thus, solve the conventional bulky gate drive circuit problem in SPMCs operation. This is in line with the international power electronic technology road-maps to reduce losses, cost, volume, therefore to raise up the power density of power electronics converters. Validation have been done through the experimental test-rig. As a result, such new theoretical enhancements can be used as a novel foundation of future high power density of SPMC circuit topology and in-line with the Fourth Industrial Revolution (IR 4.0) which were characterized mainly by advances in technology.
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
Brushless DC Motor Drive using an Isolated-Luo Converter for Power Factor Cor...IRJET Journal
This document summarizes a research paper on a brushless DC motor drive using an isolated Luo converter for power factor correction. Key points:
1) A brushless DC motor drive is presented using an isolated Luo converter to improve power quality at the AC mains while allowing for speed control of the BLDC motor.
2) The isolated Luo converter operates in discontinuous inductor current mode using a single voltage sensor, achieving inherent power factor correction with reduced sensing requirements.
3) Simulation results are presented to evaluate the performance of the drive in improving power quality for varying motor speeds and supply voltages.
This paper presents a proposed modified pulse width modulation – low frequency triangular (MPWM-LFT) switching strategy for minimization of voltage THD with implementation of asymmetric multilevel inverter (AMLI) topology on the reduced number of switching devices (RNSD) circuit structure. Principally, MPWM-LFT able to produce optimum angle of the output voltage level in order to minimize total harmonic distortion (THD). In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for asymmetric (7-level structure) multilevel inverter. For switching strategy, MPWM used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. By optimizing angle at the output voltage using MPWM-LFT switching strategy, the voltage THD is lower as compared to MPWM and SPWM switching strategies. MPWM-LFT switching strategy obtains 11.6% of voltage THD for the 7-level asymmetric topology as compared to MPWM and SPWM switching strategies with the voltage THD are 21.5% and 17.5% respectively from the experimental works.
Low Power CMOS Electrocardiogram Amplifier Design for Wearable Cardiac Screen...IJECEIAES
The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip is increasing in exponential way, the front-end electrocardiogram (ECG) amplifiers are still suffering from flicker noise for low frequency cardiac signal acquisition, 50Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a CMOS based ECG amplifier that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13µm CMOS technology from Silterra, the simulation results show that this front-end circuit can achieve a very low input referred noise of 1pV/Hz 1/2 and high common mode rejection ratio of 174.05dB. It also gives voltage gain of 75.45dB with good power supply rejection ratio of 92.12dB. The total power consumption is only 3µW and thus suitable to be implemented with further signal processing and classification back end for low power wearable biomedical device.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
The document describes a proposed low-voltage low-dropout (LDO) regulator using 90-nm CMOS technology. It converts an input of 1V to an output of 0.85-0.5V. Key features include a simple operational transconductance amplifier as the error amplifier with current splitting to boost gain and bandwidth. A power noise cancellation mechanism minimizes the power transistor size. A fast transient accelerator provides extra current during load transients. The proposed LDO achieves high efficiency, small output variation, and high power supply rejection while occupying a small area of only 0.0041 mm2.
Vlsi implementation of a programmable low drop out voltage regulatoreSAT Journals
This document summarizes the VLSI implementation of a programmable low drop-out voltage regulator. It begins by introducing low drop-out voltage regulators and their importance in applications requiring low noise and high accuracy power rails. It then discusses key design considerations for low voltage, low power LDO regulators including fast transient response, high power supply rejection, and programmability. The document presents the schematic and CMOS layout of the proposed 32nm programmable LDO regulator design. The design uses an operational transconductance amplifier as the error amplifier, along with a common-source amplifier and current-sourcing PMOS transistor in the output stage to achieve fast transient response while operating below 1V with low power consumption and program
This 3 sentence summary provides the key details about the document:
The document describes the design of a low-voltage low-dropout (LDO) voltage regulator that can operate from an input of 1V down to an output of 0.85V-0.5V. It uses a simple symmetric operational transconductance amplifier as the error amplifier with a current splitting technique to boost gain and bandwidth. Simulation results showed the proposed LDO regulator achieved 99.94% current efficiency, a 28mV output variation for a 0-100mA load transient, and 50dB power supply rejection from 0-100kHz, while only requiring an area of 0.0041mm2.
IRJET- Implementation of Combined SVL Technique in Domino Inverter using Micr...IRJET Journal
This document discusses the implementation of a combined self-controllable voltage level (SVL) technique in a domino inverter to reduce power consumption. The combined SVL technique incorporates both upper and lower SVL circuits. The lower SVL circuit increases the back gate bias of transistors, raising their threshold voltage and reducing leakage current. The upper SVL circuit decreases the supply voltage, reducing drain induced barrier lowering and also raising threshold voltage. Simulations using Microwind at 90nm show the combined SVL domino inverter has 27.7% lower power consumption than a standard static CMOS inverter. The combined SVL technique is an effective way to reduce power dissipation in domino logic circuits.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Interleaved digital power factor correction based on the sliding mode approachLeMeniz Infotech
Interleaved Digital Power Factor Correction Based on the Sliding-Mode Approach
This study describes a digitally controlled power factor correction (PFC) system based on two interleaved boost converters operating with pulsewidth modulation (PWM). Both converters are independently controlled by an inner control loop based on a discrete-time sliding-mode (SM) approach that imposes loss-free resistor (LFR) behavior on each cell. The switching surface implements an average current-mode controller so that the power factor (PF) is high. The SM-based digital controller is designed to operate at a constant switching frequency so that the interleaving technique, which is recommended for ac-dc power conversion systems higher than 1 kW, can be readily applied. An outer loop regulates the output voltage by means of a discrete-time proportional-integral (PI) compensator directly obtained from a discrete-time small-signal model of the ideal sliding dynamics. The control law proposed has been validated using numerical simulations and experimental results in a 2-kW prototype.
Web : http://www.lemenizinfotech.com
web : http://www.lemenizinfotech.com/tag/ieee-projects-in-pondicherry/
Web : http://ieeemaster.com
Web : http://ieeemaster.com/power-electronics-ieee-projects-2016-2017/
Web : http://ieeemaster.com/power-system-ieee-projects-2016-2017/
Address: 36, 100 Feet Road(Near Indira Gandhi Statue), Natesan Nagar, Pondicherry-605 005
Contact numbers: +91 95663 55386, 99625 88976 (0413) 420 5444
Mail : projects@lemenizinfotech.com
Mobile : 9566355386 / 9962588976
Hardware Implementation of Single Phase Power Factor Correction System using ...IAES-IJPEDS
Rapid increase of consumers in electronics devices and the use of mains rectification circuits inside these electronic devices is the root cause of mains harmonic distortion. Automatic power factor correction techniques can be applied to the industries, power systems and households to make them stable inturns increases the efficiency of system as well as the apparatus. This paper deals with the hardware design of active power factor correction circuit employing boost converter which is used to boost the DC voltages with a controller based on PID control strategy. The pulses given to power switches by pulse width modulation techniques generated by utilizing micro-controller board, Arduino thus obviating the need of complex hardware circuitry. MATLAB/SIMULINK was used to design and tune the PID controller parameters. The simulation results are matching with the predictions and the same was implemented as hardware. The waveforms various test points and across capacitors were obtained, studied and compared with the theoretical waveforms and are found to be in precise proximity of theoretical waveforms.
Engineering Research Publication
Best International Journals, High Impact Journals,
International Journal of Engineering & Technical Research
ISSN : 2321-0869 (O) 2454-4698 (P)
www.erpublication.org
This paper presents a PFC (Power Factor Correction) Cuk converter fed BLDC (Brushless DC) motor drive and the speed of BLDC motor is controlled using fuzzy logic implementation. The PFC converters are employed to enhance the power quality. The Brushless DC motor speed is under the control of DC-bus voltage of VSI-Voltage Source Inverter in which switching of low frequency is used. This helps in the electronic commutation of BLDC motors thus decreasing the switching losses in VSI. A DBR (Diode Bridge Rectifier) next to the PFC Cuk converter controls the voltage at DC link maintaining unity power factor. The characteristics of Cuk converter in four dissimilar modes of operation are studied such as continuous and discontinuous conduction modes (CCM and DCM) respectively. The entire system is simulated using Matlab/Simulink software and the simulation results are reported to verify the performance investigation of the proposed system.
Novel pwm modulation technique for minimizing circulation current and zero cr...IAEME Publication
This document discusses novel PWM modulation techniques for minimizing circulation current and zero crossing distortion in dual buck inverters. It begins by introducing a dual buck inverter topology and discusses traditional and improved bipolar PWM methods. While the improved method eliminates circulating current, it results in significant current distortion near zero crossings due to operating in discontinuous conduction mode. The document then proposes a novel nonlinear bipolar PWM method that provides a 0% duty cycle at zero crossings to improve the current and reduce distortion. Simulation results show the proposed method reduces THD compared to the improved bipolar PWM.
Loss free resistor-based power factor correction using a semi-bridgeless boos...LeMeniz Infotech
Loss free resistor-based power factor correction using a semi-bridgeless boost rectifier in sliding-mode control
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This paper presents parameters analysis of 4-level capacitor-clamped boost converter with hard-switching and soft-switching implementation. Principally, by considering the selected circuit structure of the 4-level capacitor-clamped boost converter and appropriate pulse width modulation (PWM) switching strategy, the overall converter volume able to be reduced. Specifically, phase-shifted of 120° of each switching signal is applied in the 4-level capacitor-clamped boost converter in order to increase the inductor current ripple frequency, thus the charging and discharging times of the inductor is reduced. Besides, volume of converters is greatly reduced if very high switching frequency is considered. However, it causes increasing of semiconductor losses and consequently the converter efficiency is affected. The results show that the efficiency of 2-level conventional boost converter and 4-level capacitor-clamped boost converter are 98.59% and 97.67%, respectively in hard-switching technique, and 99.31% and 98.15%, respectively in soft-switching technique. Therefore, by applying soft-switching technique, switching loss of the semiconductor devices is greatly minimized although high switching frequency is applied. In this study, passive lossless snubber circuit is selected for the soft-switching implementation in the 4-level capacitor-clamped boost converter. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation.
Development of a Single Stage C-Band Pulsed Power Amplifier for RADAR Transmi...somandal88
Abstract— This paper presents the design and development of
a single stage solid state pulse power amplifier(SS-PPA)
working at 7.23 GHz ± 100 MHz frequency by using hybrid technology. The amplifier is designed to achieve maximum
power gain with medium output power by adopting
simultaneous conjugate matching procedure. Commercial
available packaged pseudomorphic high electron mobility
transistor (pHEMT) FPD6836P70 (from RFMD) is used for
designing the amplifier. A pulse aggregate card has been developed to provide pulse bias. Plated through hole (PTH)
technique is used for good high frequency grounding. At room
ambient temperature, the measured peak output power from
the prototype amplifier is 18.31 dBm for 8 dBm input driving
power, measuring 10.31 dB gain. We present a description of
the design of the amplifier, its simulated and measured results
and their comparison with desired specifications.
This paper presents the new generation of advanced gate driver circuit based on IR2110 device for a Single-Phase Matrix Converter (SPMC) circuit topology that uses MOSFETs or IGBTs switches. The new generation of gate drive circuit uses less number of components, since a single IR2110 device can drive two power switches, thus reduce power losses and minimize the complexity of conventional circuit. An additional isolation of the upper and lower sides of IR2110 device features additional protection to the proposed gate drive system. As a result, the proposed gate drive circuit just uses four IR2110 gate drives in order to control eight switches of SPMC circuit, thus, solve the conventional bulky gate drive circuit problem in SPMCs operation. This is in line with the international power electronic technology road-maps to reduce losses, cost, volume, therefore to raise up the power density of power electronics converters. Validation have been done through the experimental test-rig. As a result, such new theoretical enhancements can be used as a novel foundation of future high power density of SPMC circuit topology and in-line with the Fourth Industrial Revolution (IR 4.0) which were characterized mainly by advances in technology.
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
Brushless DC Motor Drive using an Isolated-Luo Converter for Power Factor Cor...IRJET Journal
This document summarizes a research paper on a brushless DC motor drive using an isolated Luo converter for power factor correction. Key points:
1) A brushless DC motor drive is presented using an isolated Luo converter to improve power quality at the AC mains while allowing for speed control of the BLDC motor.
2) The isolated Luo converter operates in discontinuous inductor current mode using a single voltage sensor, achieving inherent power factor correction with reduced sensing requirements.
3) Simulation results are presented to evaluate the performance of the drive in improving power quality for varying motor speeds and supply voltages.
This paper presents a proposed modified pulse width modulation – low frequency triangular (MPWM-LFT) switching strategy for minimization of voltage THD with implementation of asymmetric multilevel inverter (AMLI) topology on the reduced number of switching devices (RNSD) circuit structure. Principally, MPWM-LFT able to produce optimum angle of the output voltage level in order to minimize total harmonic distortion (THD). In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for asymmetric (7-level structure) multilevel inverter. For switching strategy, MPWM used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. By optimizing angle at the output voltage using MPWM-LFT switching strategy, the voltage THD is lower as compared to MPWM and SPWM switching strategies. MPWM-LFT switching strategy obtains 11.6% of voltage THD for the 7-level asymmetric topology as compared to MPWM and SPWM switching strategies with the voltage THD are 21.5% and 17.5% respectively from the experimental works.
Low Power CMOS Electrocardiogram Amplifier Design for Wearable Cardiac Screen...IJECEIAES
The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip is increasing in exponential way, the front-end electrocardiogram (ECG) amplifiers are still suffering from flicker noise for low frequency cardiac signal acquisition, 50Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a CMOS based ECG amplifier that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13µm CMOS technology from Silterra, the simulation results show that this front-end circuit can achieve a very low input referred noise of 1pV/Hz 1/2 and high common mode rejection ratio of 174.05dB. It also gives voltage gain of 75.45dB with good power supply rejection ratio of 92.12dB. The total power consumption is only 3µW and thus suitable to be implemented with further signal processing and classification back end for low power wearable biomedical device.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
The document describes a proposed low-voltage low-dropout (LDO) regulator using 90-nm CMOS technology. It converts an input of 1V to an output of 0.85-0.5V. Key features include a simple operational transconductance amplifier as the error amplifier with current splitting to boost gain and bandwidth. A power noise cancellation mechanism minimizes the power transistor size. A fast transient accelerator provides extra current during load transients. The proposed LDO achieves high efficiency, small output variation, and high power supply rejection while occupying a small area of only 0.0041 mm2.
Vlsi implementation of a programmable low drop out voltage regulatoreSAT Journals
This document summarizes the VLSI implementation of a programmable low drop-out voltage regulator. It begins by introducing low drop-out voltage regulators and their importance in applications requiring low noise and high accuracy power rails. It then discusses key design considerations for low voltage, low power LDO regulators including fast transient response, high power supply rejection, and programmability. The document presents the schematic and CMOS layout of the proposed 32nm programmable LDO regulator design. The design uses an operational transconductance amplifier as the error amplifier, along with a common-source amplifier and current-sourcing PMOS transistor in the output stage to achieve fast transient response while operating below 1V with low power consumption and program
This 3 sentence summary provides the key details about the document:
The document describes the design of a low-voltage low-dropout (LDO) voltage regulator that can operate from an input of 1V down to an output of 0.85V-0.5V. It uses a simple symmetric operational transconductance amplifier as the error amplifier with a current splitting technique to boost gain and bandwidth. Simulation results showed the proposed LDO regulator achieved 99.94% current efficiency, a 28mV output variation for a 0-100mA load transient, and 50dB power supply rejection from 0-100kHz, while only requiring an area of 0.0041mm2.
IRJET- Implementation of Combined SVL Technique in Domino Inverter using Micr...IRJET Journal
This document discusses the implementation of a combined self-controllable voltage level (SVL) technique in a domino inverter to reduce power consumption. The combined SVL technique incorporates both upper and lower SVL circuits. The lower SVL circuit increases the back gate bias of transistors, raising their threshold voltage and reducing leakage current. The upper SVL circuit decreases the supply voltage, reducing drain induced barrier lowering and also raising threshold voltage. Simulations using Microwind at 90nm show the combined SVL domino inverter has 27.7% lower power consumption than a standard static CMOS inverter. The combined SVL technique is an effective way to reduce power dissipation in domino logic circuits.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions to decrease power consumption while maintaining the quick transient response to signal variations. LDO voltage regulators, as power management devices should adjust to modern technological and industrial trends. To increase the current capability with a minimum standby quiescent current under small-signal operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout. As a result, the efficiency gets increased.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism
reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of
IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions
to decrease power consumption while maintaining the quick transient response to signal variations. LDO
voltage regulators, as power management devices should adjust to modern technological and industrial
trends. To increase the current capability with a minimum standby quiescent current under small-signal
operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the
dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout.
As a result, the efficiency gets increased.
IRJET- Comparison of Power Dissipation in Inverter using SVL TechniquesIRJET Journal
This document compares the power dissipation of different inverter circuit designs including static CMOS, domino, and domino with self-controllable voltage level (SVL) techniques. It finds that an upper SVL domino circuit has the lowest power consumption of 25.167 μW, which is 35.88% less than a static CMOS inverter. SVL techniques like upper and lower SVL help reduce leakage power by increasing threshold voltage. Simulation results in a 90nm technology show that an upper SVL domino inverter has lower power dissipation and propagation delay compared to other designs.
This document presents a high-efficiency LED driving circuit based on a buck converter topology. The circuit is designed to operate under a wide input voltage range of 85V to 265V and drive a series of high-power LEDs. The operation principles and power loss factors of the circuit are analyzed in detail. A prototype is designed and tested to drive 16 series-connected LUMILEDS LEDs, achieving an efficiency of 92% at 350mA output current. Experimental results show the circuit achieves over 90% efficiency under variable input and output voltages, validating the design.
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUITVLSICS Design
This document summarizes a research paper that proposes a new low voltage current mirror circuit using a bulk-driven technique. The proposed circuit consists of 4 PMOS and 5 NMOS transistors and can operate at a supply voltage of +0.85V. It uses bulk connections to reduce the threshold voltage of the PMOS transistors. The document describes the circuit operation and provides its AC equivalent model. It was simulated in Cadence using a 180nm process and was found to function as a current mirror.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
Power Dissipation of VLSI Circuits and Modern Techniques of Designing Low Pow...IJSRD
This paper focus on the various sources of power dissipation in modern VLSI circuits. This paper also discuss the importance of designing low power VLSI circuits along with various techniques of power reduction and its advantages and disadvantages. It is basically a comparative study between various power reduction techniques in modern VLSI circuits.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
This document describes the design and simulation of a 1.2V to 0.9V, 40mA low dropout voltage regulator (LDO) using a 90nm CMOS technology. Key aspects of the LDO design are discussed, including the voltage divider network, two-stage operational amplifier error amplifier, PMOS pass device, and simulation results. The designed LDO achieves a gain of 68.18dB with no load and 58.39dB with full load, and maintains output voltage regulation against changes in input voltage and load current.
Similar to A low quiescent current low dropout voltage regulator with self-compensation (20)
Square transposition: an approach to the transposition process in block cipherjournalBEEI
The transposition process is needed in cryptography to create a diffusion effect on data encryption standard (DES) and advanced encryption standard (AES) algorithms as standard information security algorithms by the National Institute of Standards and Technology. The problem with DES and AES algorithms is that their transposition index values form patterns and do not form random values. This condition will certainly make it easier for a cryptanalyst to look for a relationship between ciphertexts because some processes are predictable. This research designs a transposition algorithm called square transposition. Each process uses square 8 × 8 as a place to insert and retrieve 64-bits. The determination of the pairing of the input scheme and the retrieval scheme that have unequal flow is an important factor in producing a good transposition. The square transposition can generate random and non-pattern indices so that transposition can be done better than DES and AES.
Hyper-parameter optimization of convolutional neural network based on particl...journalBEEI
The document proposes using a particle swarm optimization (PSO) algorithm to optimize the hyperparameters of a convolutional neural network (CNN) for image classification. The PSO algorithm is used to find optimal values for CNN hyperparameters like the number and size of convolutional filters. In experiments on the MNIST handwritten digit dataset, the optimized CNN achieved a testing error rate of 0.87%, which is competitive with state-of-the-art models. The proposed approach finds optimized CNN architectures automatically without requiring manual design or encoding strategies during training.
Supervised machine learning based liver disease prediction approach with LASS...journalBEEI
In this contemporary era, the uses of machine learning techniques are increasing rapidly in the field of medical science for detecting various diseases such as liver disease (LD). Around the globe, a large number of people die because of this deadly disease. By diagnosing the disease in a primary stage, early treatment can be helpful to cure the patient. In this research paper, a method is proposed to diagnose the LD using supervised machine learning classification algorithms, namely logistic regression, decision tree, random forest, AdaBoost, KNN, linear discriminant analysis, gradient boosting and support vector machine (SVM). We also deployed a least absolute shrinkage and selection operator (LASSO) feature selection technique on our taken dataset to suggest the most highly correlated attributes of LD. The predictions with 10 fold cross-validation (CV) made by the algorithms are tested in terms of accuracy, sensitivity, precision and f1-score values to forecast the disease. It is observed that the decision tree algorithm has the best performance score where accuracy, precision, sensitivity and f1-score values are 94.295%, 92%, 99% and 96% respectively with the inclusion of LASSO. Furthermore, a comparison with recent studies is shown to prove the significance of the proposed system.
A secure and energy saving protocol for wireless sensor networksjournalBEEI
The research domain for wireless sensor networks (WSN) has been extensively conducted due to innovative technologies and research directions that have come up addressing the usability of WSN under various schemes. This domain permits dependable tracking of a diversity of environments for both military and civil applications. The key management mechanism is a primary protocol for keeping the privacy and confidentiality of the data transmitted among different sensor nodes in WSNs. Since node's size is small; they are intrinsically limited by inadequate resources such as battery life-time and memory capacity. The proposed secure and energy saving protocol (SESP) for wireless sensor networks) has a significant impact on the overall network life-time and energy dissipation. To encrypt sent messsages, the SESP uses the public-key cryptography’s concept. It depends on sensor nodes' identities (IDs) to prevent the messages repeated; making security goals- authentication, confidentiality, integrity, availability, and freshness to be achieved. Finally, simulation results show that the proposed approach produced better energy consumption and network life-time compared to LEACH protocol; sensors are dead after 900 rounds in the proposed SESP protocol. While, in the low-energy adaptive clustering hierarchy (LEACH) scheme, the sensors are dead after 750 rounds.
Plant leaf identification system using convolutional neural networkjournalBEEI
This paper proposes a leaf identification system using convolutional neural network (CNN). This proposed system can identify five types of local Malaysia leaf which were acacia, papaya, cherry, mango and rambutan. By using CNN from deep learning, the network is trained from the database that acquired from leaf images captured by mobile phone for image classification. ResNet-50 was the architecture has been used for neural networks image classification and training the network for leaf identification. The recognition of photographs leaves requested several numbers of steps, starting with image pre-processing, feature extraction, plant identification, matching and testing, and finally extracting the results achieved in MATLAB. Testing sets of the system consists of 3 types of images which were white background, and noise added and random background images. Finally, interfaces for the leaf identification system have developed as the end software product using MATLAB app designer. As a result, the accuracy achieved for each training sets on five leaf classes are recorded above 98%, thus recognition process was successfully implemented.
Customized moodle-based learning management system for socially disadvantaged...journalBEEI
This study aims to develop Moodle-based LMS with customized learning content and modified user interface to facilitate pedagogical processes during covid-19 pandemic and investigate how teachers of socially disadvantaged schools perceived usability and technology acceptance. Co-design process was conducted with two activities: 1) need assessment phase using an online survey and interview session with the teachers and 2) the development phase of the LMS. The system was evaluated by 30 teachers from socially disadvantaged schools for relevance to their distance learning activities. We employed computer software usability questionnaire (CSUQ) to measure perceived usability and the technology acceptance model (TAM) with insertion of 3 original variables (i.e., perceived usefulness, perceived ease of use, and intention to use) and 5 external variables (i.e., attitude toward the system, perceived interaction, self-efficacy, user interface design, and course design). The average CSUQ rating exceeded 5.0 of 7 point-scale, indicated that teachers agreed that the information quality, interaction quality, and user interface quality were clear and easy to understand. TAM results concluded that the LMS design was judged to be usable, interactive, and well-developed. Teachers reported an effective user interface that allows effective teaching operations and lead to the system adoption in immediate time.
Understanding the role of individual learner in adaptive and personalized e-l...journalBEEI
Dynamic learning environment has emerged as a powerful platform in a modern e-learning system. The learning situation that constantly changing has forced the learning platform to adapt and personalize its learning resources for students. Evidence suggested that adaptation and personalization of e-learning systems (APLS) can be achieved by utilizing learner modeling, domain modeling, and instructional modeling. In the literature of APLS, questions have been raised about the role of individual characteristics that are relevant for adaptation. With several options, a new problem has been raised where the attributes of students in APLS often overlap and are not related between studies. Therefore, this study proposed a list of learner model attributes in dynamic learning to support adaptation and personalization. The study was conducted by exploring concepts from the literature selected based on the best criteria. Then, we described the results of important concepts in student modeling and provided definitions and examples of data values that researchers have used. Besides, we also discussed the implementation of the selected learner model in providing adaptation in dynamic learning.
Prototype mobile contactless transaction system in traditional markets to sup...journalBEEI
1) Researchers developed a prototype contactless transaction system using QR codes and digital payments to support physical distancing during the COVID-19 pandemic in traditional markets.
2) The system allows sellers and buyers in traditional markets to conduct fast, secure transactions via smartphones without direct cash exchange. Buyers scan sellers' QR codes to view product details and make e-wallet payments.
3) Testing showed the system's functions worked properly and users found it easy to use and useful for supporting contactless transactions and digital transformation of traditional markets. However, further development is needed to increase trust in digital payments for users unfamiliar with the technology.
Wireless HART stack using multiprocessor technique with laxity algorithmjournalBEEI
The use of a real-time operating system is required for the demarcation of industrial wireless sensor network (IWSN) stacks (RTOS). In the industrial world, a vast number of sensors are utilised to gather various types of data. The data gathered by the sensors cannot be prioritised ahead of time. Because all of the information is equally essential. As a result, a protocol stack is employed to guarantee that data is acquired and processed fairly. In IWSN, the protocol stack is implemented using RTOS. The data collected from IWSN sensor nodes is processed using non-preemptive scheduling and the protocol stack, and then sent in parallel to the IWSN's central controller. The real-time operating system (RTOS) is a process that occurs between hardware and software. Packets must be sent at a certain time. It's possible that some packets may collide during transmission. We're going to undertake this project to get around this collision. As a prototype, this project is divided into two parts. The first uses RTOS and the LPC2148 as a master node, while the second serves as a standard data collection node to which sensors are attached. Any controller may be used in the second part, depending on the situation. Wireless HART allows two nodes to communicate with each other.
Implementation of double-layer loaded on octagon microstrip yagi antennajournalBEEI
This document describes the implementation of a double-layer structure on an octagon microstrip yagi antenna (OMYA) to improve its performance at 5.8 GHz. The double-layer consists of two double positive (DPS) substrates placed above the OMYA. Simulation and experimental results show that the double-layer configuration increases the gain of the OMYA by 2.5 dB compared to without the double-layer. The measured bandwidth of the OMYA with double-layer is 14.6%, indicating the double-layer can increase both the gain and bandwidth of the OMYA.
The calculation of the field of an antenna located near the human headjournalBEEI
In this work, a numerical calculation was carried out in one of the universal programs for automatic electro-dynamic design. The calculation is aimed at obtaining numerical values for specific absorbed power (SAR). It is the SAR value that can be used to determine the effect of the antenna of a wireless device on biological objects; the dipole parameters will be selected for GSM1800. Investigation of the influence of distance to a cell phone on radiation shows that absorbed in the head of a person the effect of electromagnetic radiation on the brain decreases by three times this is a very important result the SAR value has decreased by almost three times it is acceptable results.
Exact secure outage probability performance of uplinkdownlink multiple access...journalBEEI
In this paper, we study uplink-downlink non-orthogonal multiple access (NOMA) systems by considering the secure performance at the physical layer. In the considered system model, the base station acts a relay to allow two users at the left side communicate with two users at the right side. By considering imperfect channel state information (CSI), the secure performance need be studied since an eavesdropper wants to overhear signals processed at the downlink. To provide secure performance metric, we derive exact expressions of secrecy outage probability (SOP) and and evaluating the impacts of main parameters on SOP metric. The important finding is that we can achieve the higher secrecy performance at high signal to noise ratio (SNR). Moreover, the numerical results demonstrate that the SOP tends to a constant at high SNR. Finally, our results show that the power allocation factors, target rates are main factors affecting to the secrecy performance of considered uplink-downlink NOMA systems.
Design of a dual-band antenna for energy harvesting applicationjournalBEEI
This report presents an investigation on how to improve the current dual-band antenna to enhance the better result of the antenna parameters for energy harvesting application. Besides that, to develop a new design and validate the antenna frequencies that will operate at 2.4 GHz and 5.4 GHz. At 5.4 GHz, more data can be transmitted compare to 2.4 GHz. However, 2.4 GHz has long distance of radiation, so it can be used when far away from the antenna module compare to 5 GHz that has short distance in radiation. The development of this project includes the scope of designing and testing of antenna using computer simulation technology (CST) 2018 software and vector network analyzer (VNA) equipment. In the process of designing, fundamental parameters of antenna are being measured and validated, in purpose to identify the better antenna performance.
Transforming data-centric eXtensible markup language into relational database...journalBEEI
eXtensible markup language (XML) appeared internationally as the format for data representation over the web. Yet, most organizations are still utilising relational databases as their database solutions. As such, it is crucial to provide seamless integration via effective transformation between these database infrastructures. In this paper, we propose XML-REG to bridge these two technologies based on node-based and path-based approaches. The node-based approach is good to annotate each positional node uniquely, while the path-based approach provides summarised path information to join the nodes. On top of that, a new range labelling is also proposed to annotate nodes uniquely by ensuring the structural relationships are maintained between nodes. If a new node is to be added to the document, re-labelling is not required as the new label will be assigned to the node via the new proposed labelling scheme. Experimental evaluations indicated that the performance of XML-REG exceeded XMap, XRecursive, XAncestor and Mini-XML concerning storing time, query retrieval time and scalability. This research produces a core framework for XML to relational databases (RDB) mapping, which could be adopted in various industries.
Key performance requirement of future next wireless networks (6G)journalBEEI
The document provides an overview of the key performance indicators (KPIs) for 6G wireless networks compared to 5G networks. Some of the major KPIs discussed for 6G include: achieving data rates of up to 1 Tbps and individual user data rates up to 100 Gbps; reducing latency below 10 milliseconds; supporting up to 10 million connected devices per square kilometer; improving spectral efficiency by up to 100 times through technologies like terahertz communications and smart surfaces; and achieving an energy efficiency of 1 pico-joule per bit transmitted through techniques like wireless power transmission and energy harvesting. The document outlines how 6G aims to integrate terrestrial, aerial and maritime communications into a single network to provide ubiquitous connectivity with higher
Noise resistance territorial intensity-based optical flow using inverse confi...journalBEEI
This paper presents the use of the inverse confidential technique on bilateral function with the territorial intensity-based optical flow to prove the effectiveness in noise resistance environment. In general, the image’s motion vector is coded by the technique called optical flow where the sequences of the image are used to determine the motion vector. But, the accuracy rate of the motion vector is reduced when the source of image sequences is interfered by noises. This work proved that the inverse confidential technique on bilateral function can increase the percentage of accuracy in the motion vector determination by the territorial intensity-based optical flow under the noisy environment. We performed the testing with several kinds of non-Gaussian noises at several patterns of standard image sequences by analyzing the result of the motion vector in a form of the error vector magnitude (EVM) and compared it with several noise resistance techniques in territorial intensity-based optical flow method.
Modeling climate phenomenon with software grids analysis and display system i...journalBEEI
This study aims to model climate change based on rainfall, air temperature, pressure, humidity and wind with grADS software and create a global warming module. This research uses 3D model, define, design, and develop. The results of the modeling of the five climate elements consist of the annual average temperature in Indonesia in 2009-2015 which is between 29oC to 30.1oC, the horizontal distribution of the annual average pressure in Indonesia in 2009-2018 is between 800 mBar to 1000 mBar, the horizontal distribution the average annual humidity in Indonesia in 2009 and 2011 ranged between 27-57, in 2012-2015, 2017 and 2018 it ranged between 30-60, during the East Monsoon, the wind circulation moved from northern Indonesia to the southern region Indonesia. During the west monsoon, the wind circulation moves from the southern part of Indonesia to the northern part of Indonesia. The global warming module for SMA/MA produced is feasible to use, this is in accordance with the value given by the validate of 69 which is in the appropriate category and the response of teachers and students through a 91% questionnaire.
An approach of re-organizing input dataset to enhance the quality of emotion ...journalBEEI
The purpose of this paper is to propose an approach of re-organizing input data to recognize emotion based on short signal segments and increase the quality of emotional recognition using physiological signals. MIT's long physiological signal set was divided into two new datasets, with shorter and overlapped segments. Three different classification methods (support vector machine, random forest, and multilayer perceptron) were implemented to identify eight emotional states based on statistical features of each segment in these two datasets. By re-organizing the input dataset, the quality of recognition results was enhanced. The random forest shows the best classification result among three implemented classification methods, with an accuracy of 97.72% for eight emotional states, on the overlapped dataset. This approach shows that, by re-organizing the input dataset, the high accuracy of recognition results can be achieved without the use of EEG and ECG signals.
Parking detection system using background subtraction and HSV color segmentationjournalBEEI
Manual system vehicle parking makes finding vacant parking lots difficult, so it has to check directly to the vacant space. If many people do parking, then the time needed for it is very much or requires many people to handle it. This research develops a real-time parking system to detect parking. The system is designed using the HSV color segmentation method in determining the background image. In addition, the detection process uses the background subtraction method. Applying these two methods requires image preprocessing using several methods such as grayscaling, blurring (low-pass filter). In addition, it is followed by a thresholding and filtering process to get the best image in the detection process. In the process, there is a determination of the ROI to determine the focus area of the object identified as empty parking. The parking detection process produces the best average accuracy of 95.76%. The minimum threshold value of 255 pixels is 0.4. This value is the best value from 33 test data in several criteria, such as the time of capture, composition and color of the vehicle, the shape of the shadow of the object’s environment, and the intensity of light. This parking detection system can be implemented in real-time to determine the position of an empty place.
Quality of service performances of video and voice transmission in universal ...journalBEEI
The universal mobile telecommunications system (UMTS) has distinct benefits in that it supports a wide range of quality of service (QoS) criteria that users require in order to fulfill their requirements. The transmission of video and audio in real-time applications places a high demand on the cellular network, therefore QoS is a major problem in these applications. The ability to provide QoS in the UMTS backbone network necessitates an active QoS mechanism in order to maintain the necessary level of convenience on UMTS networks. For UMTS networks, investigation models for end-to-end QoS, total transmitted and received data, packet loss, and throughput providing techniques are run and assessed and the simulation results are examined. According to the results, appropriate QoS adaption allows for specific voice and video transmission. Finally, by analyzing existing QoS parameters, the QoS performance of 4G/UMTS networks may be improved.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Generative AI Use cases applications solutions and implementation.pdfmahaffeycheryld
Generative AI solutions encompass a range of capabilities from content creation to complex problem-solving across industries. Implementing generative AI involves identifying specific business needs, developing tailored AI models using techniques like GANs and VAEs, and integrating these models into existing workflows. Data quality and continuous model refinement are crucial for effective implementation. Businesses must also consider ethical implications and ensure transparency in AI decision-making. Generative AI's implementation aims to enhance efficiency, creativity, and innovation by leveraging autonomous generation and sophisticated learning algorithms to meet diverse business challenges.
https://www.leewayhertz.com/generative-ai-use-cases-and-applications/
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...PriyankaKilaniya
Energy efficiency has been important since the latter part of the last century. The main object of this survey is to determine the energy efficiency knowledge among consumers. Two separate districts in Bangladesh are selected to conduct the survey on households and showrooms about the energy and seller also. The survey uses the data to find some regression equations from which it is easy to predict energy efficiency knowledge. The data is analyzed and calculated based on five important criteria. The initial target was to find some factors that help predict a person's energy efficiency knowledge. From the survey, it is found that the energy efficiency awareness among the people of our country is very low. Relationships between household energy use behaviors are estimated using a unique dataset of about 40 households and 20 showrooms in Bangladesh's Chapainawabganj and Bagerhat districts. Knowledge of energy consumption and energy efficiency technology options is found to be associated with household use of energy conservation practices. Household characteristics also influence household energy use behavior. Younger household cohorts are more likely to adopt energy-efficient technologies and energy conservation practices and place primary importance on energy saving for environmental reasons. Education also influences attitudes toward energy conservation in Bangladesh. Low-education households indicate they primarily save electricity for the environment while high-education households indicate they are motivated by environmental concerns.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELijaia
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Home security is of paramount importance in today's world, where we rely more on technology, home
security is crucial. Using technology to make homes safer and easier to control from anywhere is
important. Home security is important for the occupant’s safety. In this paper, we came up with a low cost,
AI based model home security system. The system has a user-friendly interface, allowing users to start
model training and face detection with simple keyboard commands. Our goal is to introduce an innovative
home security system using facial recognition technology. Unlike traditional systems, this system trains
and saves images of friends and family members. The system scans this folder to recognize familiar faces
and provides real-time monitoring. If an unfamiliar face is detected, it promptly sends an email alert,
ensuring a proactive response to potential security threats.
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...Transcat
Join us for this solutions-based webinar on the tools and techniques for commissioning and maintaining PV Systems. In this session, we'll review the process of building and maintaining a solar array, starting with installation and commissioning, then reviewing operations and maintenance of the system. This course will review insulation resistance testing, I-V curve testing, earth-bond continuity, ground resistance testing, performance tests, visual inspections, ground and arc fault testing procedures, and power quality analysis.
Fluke Solar Application Specialist Will White is presenting on this engaging topic:
Will has worked in the renewable energy industry since 2005, first as an installer for a small east coast solar integrator before adding sales, design, and project management to his skillset. In 2022, Will joined Fluke as a solar application specialist, where he supports their renewable energy testing equipment like IV-curve tracers, electrical meters, and thermal imaging cameras. Experienced in wind power, solar thermal, energy storage, and all scales of PV, Will has primarily focused on residential and small commercial systems. He is passionate about implementing high-quality, code-compliant installation techniques.
Supermarket Management System Project Report.pdfKamal Acharya
Supermarket management is a stand-alone J2EE using Eclipse Juno program.
This project contains all the necessary required information about maintaining
the supermarket billing system.
The core idea of this project to minimize the paper work and centralize the
data. Here all the communication is taken in secure manner. That is, in this
application the information will be stored in client itself. For further security the
data base is stored in the back-end oracle and so no intruders can access it.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.
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in order to obtain low output impedance at the output of LDO [10]. This method sustain low impedance at
output node and keep this pole at higher frequency. However the trade-off is the higher dropout voltage is
required by NMOS pass transistor, thus lower efficiency is obtained. An additional low-impedance loading
network at output node of LDO has also been suggested [11]. This method is able to maintain a competitive
low dropout voltage using PMOS as output stage and sustain low impedance at the output node. However,
excessive amount of current is needed by this circuit to sustain the output in low impedance. Thus, the higher
quiescent current has resulting a lower efficiency LDO design.
Figure 1. Conceptual LDO design for SoC application
To attain the issue of high quiescent current in LDO, there are research studies had been done, such
as reduced the dropout voltage or reduce the low quiescent current during operation mode [12, 13]. However
not many researches were being done to reduce quiescent current particularly during very small output load
current, which means during its idle state. According to the statistic, electronics devices are under stand-by or
idle mode at most of the time. Analog circuitries particularly LDOs are the major modules that constantly
consuming current even in its idle state in order to keep the power supply working for the rest of the
circuities. Therefore, this compromises the efficiency performance since the stand-by quiescent current
carries a higher weight in efficiency. The efficiency percentage is given by
( )
(1)
where is quiescent current and is the output load current. Therefore reducing quiescent current to
maintain a higher efficiency at very small or zero output load current is deemed to be important. Prior to this,
this paper is focus on reducing the LDO’s quiescent current even during output load current is near to zero, A
method had been suggested by using self-reduction quiescent current circuitry [14]. This circuitry uses
minimum quiescent current during high output loading current in order to obtain a better efficiency. It only
allows adequate amount of additional current to be supplied to attain LDO stability during very low output
load current. An improved version of such circuitry design is proposed in this paper. In this work, a sense and
control circuit with low-impedance circuit is introduced. The circuit enables a self-adjusted minimum
quiescent current to sustain the low output impedance during output load current is very small. At the same
time, a self-compensation method is used to sustain the stability. This self-compensation mechanism has also
contributed to the further reduction of total quiescent current.
2. PROPOSED LDO CIRCUIT DESIGN
2.1. Schematic and circuit implementation
The schematic of the proposed LDO circuit design is shown in Figure 2 and Figure 3. The proposed
circuit is mainly consists of biasing circuit, transconductance amplifier (OTA), pass transistor power PMOS
(MP), low-impedance circuit, sensing and control (SAC) circuit, and feedback network (resistors R1 and R2).
As shown in Figure 2, the biasing circuit is formed by transistor Mb1, Mb2 and resistor Rb that supply bias
current to the rest of the circuitry. The OTA amplifier consists of an input differential amplifier (M1~M5) and
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a gain stage amplifier (M7~M10). Transistor M6 is biased from the SAC circuit to control an auxiliary current
for the differential amplifier. The output of the gain stage forms a push-pull stage to charge and discharge the
gate capacitance of the power PMOS, MP. The gate capacitance of MP is large due to the huge transistor size
of this power PMOS to regulate the tremendous amount of current to the output load circuit. MP output
impedance, is given by (2), where is the channel length modulation.
(2)
Figure 2. Proposed LDO circuit design (op-amp)
As shown in Figure 3, the low-impedance circuit consists of M18~M21. The source of PMOS
transistor, M21 is connected to the output node of the LDO to provide a low impedance node. The total output
impedance at VOUT node, is given by (3), where is the output impedance of M21, and is the
output load resistance. The current from M12 is mirrored to M21 through current mirror M14, M18 and M20.
Transistor M19 is used to keep transistor M20 in vigilant to maintain a fast response if M18 is turn off.
( ) (3)
Figure 3. Proposed LDO circuit design
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The sensing and control (SAC) circuit consists of sensing circuit (MPT, Rt1 and Rt2) and a differential
circuit (M11~M15). The size of sensing transistor, MPT is scaled to a ratio of 100 times smaller than MP.
Changes on output load current, that flow through MP will reflected to MPT with 100 times smaller
scale. Voltage level VPT is scaled by the resistor divider Rt1 and Rt2 to be compared with a fixed reference
voltage, Vth. If reduces below , it reflects to VPT, and start the differential mode
comparison operation.
2.2. Stability analysis and circuit operation
Figure 4 shows the open-loop domain configuration of the proposed LDO. It shows total three
amplifier stages, which is the differential amplifier, gain stage, and the power PMOS as the third stage.
Power PMOS is a common-source amplifier. Each stage corresponding transconductance, output impedance
and parasitic capacitance are denoted in the configuration as , , , , , , , ,
and respectively.
Figure 4. Proposed LDO open-loop configuration
The output impedance of the first stage, is small due to the diode-connected active load which
imposed approximately at its output. Therefore first stage gain is small and the pole is located at
higher frequency and doesn’t affect the stability. The second stage has a large output impedance ( ) due to
the active load formed by current mirror circuit. Therefore gain is higher. At this node, large gate
capacitance of power PMOS contributes to a high value , and therefore the dominant pole ( ) is
located at this node. The third stage output impedance, has a wide variation range which depending on
the large output load current, as per (2) and (3). Due to the large MP size, the is high, thus contributes to
high gain . The parasitic capacitance and output load capacitance contribute to second pole ( )
frequency and dependent on variation. A compensation capacitor is connected between the output of
first and third stage, and gate-drain capacitance of MP between second and third stage, are giving a pole
splitting effect for frequency compensation. The low frequency gain ( ), dominant pole ( ) and
second pole ( ) are respectively given by:
(4)
( )
(5)
( ) ( )
(6)
The transfer function, T(s) is given by (7):
T(s)=
( )
( )
≈
(
( )
)
( )( [
( ) ( )
]
( )
( )
(7)
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The loop stability analysis to be focused in this work is on the worst case scenario where is
below . When falls below 100μA, becomes very large and so does as shown in (2) and
(3). This causes frequency to reduce tremendously moving toward UGF, and compromise the minimum
requirement of phase margin if √ . A solution is proposed to reduce using low-impedance
circuit. From (3), small value from low-impedance circuit dominates instead of . If reduces
below , the sensing circuit will cause VPT to decrease below Vth. M12 will start to draw more current
compare M11. As reduces, more current will be mirrored from M12 to M21 to obtain smaller impedance
value, . Thus prevent from further shifting to lower frequency. If is not low enough to
compromise the loop stability, only adequate amount of current is used to maintain the loop stability. In other
words, self-reduction current is performed when starts to increase from zero. However, at worst case
stability phenomenon where is zero, this current can be high. Instead of using excessive current to
maintain frequency, a self-compensation circuit method is proposed. The total gain is lowered without
influencing in order to shift UGF to lower frequency, away from as shown in Figure 5. This is done
by the SAC circuit with a current feedback. As reduces, VPT decreases, and drain current of M11 starts to
reduce. Lower current is mirrored from M11 to M6, and reduces the first stage gain.
Figure 5. Bode plot for < 100μA
Therefore the total gain has been reduced but location is not affected. In other words, as
reduces, a self-compensation mechanism take effect where the UGF is automatically reduces in order to
obtain a better phase margin. The proposed SAC circuit has not only reduced the excessive at low-
impedance circuit, but at same time, it further reduced the tail current at first stage amplifier. This has
contributed to the reduction of total quiescent current.
3. RESULTS AND DISCUSSION
The proposed LDO in this work has been implemented using CMOS process technology.
The frequency response at high load current is stable with phase margin higher than . This work focuses
on very low output load current phenomenon. The close-loop frequency response of proposed LDO at very
low load current is plotted as shown in Figure 6. When the load current is reduced, the decrement of second
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pole can be seen. It’s due to the self-reduction of additional current at low-impedance circuitry. It shows that
the gain is decreasing when the load current is reduced to zero, and the UGF shifted to lower frequency and
attained loop stability with phase margin higher than . The gain during zero load current doesn’t
compromise the application of LDO since it’s not in regulating mode. Maintaining adequate phase margin to
attain loop stability at zero load current is more important so that a quick response is obtained when the load
current is suddenly required at the LDO output. The resulst also shown an almost linear decrement of UGF
with the reduction of load current from 100μA.
Figure 6. LDO frequency response for very small load current
Figure 7(a) shows the graph of versus , where is the current used to keep output
impedance low during small load current. When increased from zero to , has reduced from
to for VCC=1.20V. This shows the self-reduction mechanism of current used in low-impedance
circuit. Figure 7(b) shows the graph of total quiescent current, versus . When reduces from
, the total quiescent current of LDO has been reduced from to for VCC=1.20V. The total
quiescent current reduction is around 30%.
(a) (b)
Figure 7. (a) (b) , versus of LDO
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Figure 8 shows the efficiency performance of proposed LDO at load current below 100μA. The
result shows 60% efficiency even at very low load current at 25μA. The efficiency has became almost
constant at 70% and above when load current increased to 50μA.
Figure 8. Efficiency versus Iload
The die picture of the LDO is shown in Figure 9. Table 1 shows the comparison between the recent
reported LDO designs and this work. The reported LDO designs with proximity technology are chosen for
the comparison. This LDO is designed to deliver a maximum load current of 100mA. The proposed lower
power LDO supply voltage is 1.2V and the output voltage is 1.0V with dropout voltage of 200mV. The total
quiescent current is only at zero output load current, and at full output load current .
Figure 9. Die picture of proposed LDO
Table 1. Comparison of published LDO results
Published
LDO
Technology
(μm)
Supply
Voltage (V)
Dropout
Voltage (mV)
Output
voltage
(V)
Max. Load
Current
(mA)
Min.
Load
Current
(μA)
Max.
Quiescent
Current
(μA)
Compensation
Cap, Cc (F)
[11] 0.18 1.2 200 1.0 100 0 53.5 10p
[15] 0.13 >1.313 >113 1.2 70 - 93 external
[14] 0.13 1.2 100 1.1 100 - 27 8p
[16] 0.13 1.2 200 1.0 50 50 37.3 -
This work 0.13 1.2 200 1.0 100 0 17.7 8p
4. CONCLUSION
A low quiescent current LDO with self-compensation has been presented in this work. The proposed
LDO has improved the loop stability and efficiency issues at worst case scenario where output load current
is very low. These techniques are implemented by low-impedance circuit and SAC circuits. The
8. ISSN: 2302-9285
Bulletin of Electr Eng and Inf, Vol. 8, No. 1, March 2019 : 65 – 73
70
variation of is sensed and feedback by SAC circuit. Firstly, the current used for keeping output
impedance low is self-reduced as slowly increases from zero. Secondly, a self-compensation method is
introduced for frequency compensation, instead of using excessive current to keep frequency higher. The
current feedback of the SAC circuit has also further reduced quiescent current. The results have shown that
this LDO has achieved the goal of reducing quiescent current by adopting current self-reduction technique.
On top of that, a self-compensation circuit technique on loop stability has also further decreased quiescent
current.The total quiescent current reduction has contributed to a higher efficiency of the LDO at low
load current.
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BIOGRAPHIES OF AUTHORS
Chu-Liang Lee received his B.Sc. degree in Physics (Hon.) and M.Sc. degree in electronic
engineering (majoring microelectronic) from Universiti Putra Malaysia (UPM), Selangor,
Malaysia in 1997 and 2001 respectively. He is currently working toward Ph.D. degree at
Universiti Putra Malaysia, Selangor, Malaysia. From 2001 to 2005, he was an Integrated Circuit
Design Engineer with Malaysia Microelectronic Solutions Sdn. Bhd., where he was involved
with digital IC design from front-end to back-end, mainly for smartcard products. From 2005 to
2006, he switched to analog integrated circuit design with Mycrosem Electronics Sdn. Bhd., a
start-up company which involved fan driver IC using bipolar process. From 2006 to 2008, he
joined BlueChips Technology Bhd. as analog integrated circuit design engineer where he
involved DC/DC converter design using BCD and CMOS process. He was also involved in chip
testing and failure debugging of IC chips. He then joined PHY Semiconductor Sdn. Bhd. and
involved in optical transmitter and receiver design from 2008 to 2009, before joining academic
as a lecturer in Multimedia University, Cyberjaya, Malaysia. His research interests include
digital and analog integrated circuit design.
9. Bulletin of Electr Eng and Inf ISSN: 2302-9285
A low quiescent current low dropout voltage regulator with self-compensation (Chu-Liang Lee)
71
Roslina Mohd Sidek received the B.Sc. degree in Washington DC in 1990, and the M.Sc. and
Ph.D. degree from University of Southampton, United Kingdom in 1993 and 1999 respectively.
She is currently Associate Professor in Department of Electrical and Electronic Engineering,
University Putra Malaysia. She had involved in several industrial collaboration projects, namely
Flash Memory Design with MyMS Sdn Bhd, CMOS ESD Devices project wih Silterra Sdn Bhd,
and GaAs Devices and Circuits with TMRnD. She is also a member of professional affiliation of
MIEEE and MIEM, and registered with BEM. Her areas of expertise is in Semiconductor
Devices and Modelling, Integrated Circuit Fabrication, Integrated Circuit Design and Testing.
Nasri bin Sulaiman is a senior lecturer at the Department of Electrical and Electronic
Engineering, Faculty of Engineering, Universiti Putra Malaysia. He received a bachelor degree
in electronics and computer engineering from the Universiti Putra Malaysia (UPM), Malaysia in
1994 and a master degree in microelectronics system design from the University of
Southampton, United Kingdom in 1999. He also obtained a Ph.D degree in adaptive hardware
from the University of Edinburgh, United Kingdom in 2007. His areas of interest include
evolutionary algorithms, digital signal processing, digital communications and low power
VLSI designs
Fakhrul Zaman Rokhani received the B.S. degree in University of Technology Malaysia, and
the M.S. and Ph.D. degree from the University of Minnesota, USA. He was with Intel Penang
Design Center as visiting professor designing chipset for Intel Core i3/i5/i7 processor on 32nm
Intel process technology, was with Huawei Technologies for CEO coaching program, visiting
scholar at the ASIC & Systems State Key Lab in Fudan University, China, visiting assistant
professor at Al-Neelain University, Sudan, visiting professor at Celal Bayar University, Turkey
and engineer at MIMOS. He serves as an Editor-in-Chief for IEEE CASS (M) newsletter and
associate editor for IEEE CASS society newsletter, past chair for IEEE Consumer Electronics
(M) Chapter, executive committee in the IEEE CASS (M) Chapter and was a Treasurer for the
IEEE GOLD. He serves on the technical program committees and publication chair for many
flagship IEEE conferences.