The document proposes a new level shifter circuit that can operate over a wide voltage range from 0.3V to 1.2V. It summarizes existing level shifter techniques and identifies limitations like high power consumption and large transistor sizes. The proposed circuit uses multiplexers in a feedback loop to bias the pull-up transistors for faster switching. Simulations show the new design has lower delay, power and energy compared to other approaches while converting between different voltage domains in smart system-on-chips.

1. A Multi VDD Wide Voltage Range Up Level
Shifter for Smart SoC Applications
Presented by
D Baba Fayaz,
Department of Electronics and Communication Engineering,
National Institute of Technology Warangal.10-09-2020 1

2. Outline
• Motivation
• Introduction
• Existing Techniques of Level Shifters
• Proposed Level Shifter
• Simulation Results
• Comparison Table
• Conclusion
• References
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3. Motivation
• In scale down technology nodes power
consumption is one of the major drawback in
todays SOC designs.
• Scaling of device features not only increases the
performance of the circuit but also increases the
leakage power.
• Scaling the power supply (VDD) causes the
degrading in performance of the circuit.
• Multiple supply voltage domain(MSVD)
technique is emerging as an efficient method to
reduce both dynamic and static power in today
SOCs.
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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4. Introduction to Level Shifter
 Level shifter cell is used to convert from one
voltage to another voltage level.
 It is required when the chip is operating at multiple
voltage domains.
 The situation where dynamic voltage scaling is
used and the voltage relation between the source
and destination might change and that leads to
unreliable functioning. In that case we need this
level shifter.
Applications : Interconnecting two logic families like
CMOS and TTL
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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5. Existing Techniques of Level Shifters
• Level shifter circuits are typically based on one of these approaches
1. Differential cascade voltage switch (DCVS) level shifter.
2. Current mirror based level shifter.
3. Single ended input level shifter.
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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6. DCVS (or) STANDARD LEVEL SHIFTER
• In this configuration, Input of NMOS transistors are controlled by
a low voltage input signal, which is shifted to high voltage at the
output of the level shifter.
• The gate of PL and PR transistors is connected to high voltage
supply due to that NL and NR struggle to sink more current than
the PMOS pull-up transistors source.
Drawbacks
• This configuration needs larger NMOS transistors with widths
typically ten times larger than PMOS transistors by this both delay
and power consumption also increases.
• Very weak pull down network even if the NMOS transistors are
significantly larger than the PMOS transistors.
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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7. CURRENT MIRROR BASED LEVEL SHIFTER
• A semi static current mirror is used to limit the current and
therefore the strength of the pull up device is weakened when
the pull down device is pulling down the output node.
• This circuit overcomes the contention problem which is in
DCVS circuit.
• However, this structure suffers from the static current flowing
through NL and PL during the “High” logic levels of input
signal.
Drawbacks
• This method leads to large standby current.
• Power consumption increases significantly due to static current
path.
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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8. SINGLE ENDED LEVEL SHIFTER
• A single ended level shifter is to mitigate the drawbacks of
Standard and Current mirror level LS.
• Low power applications can be easily carried out by using
this single ended level shifter using zero steady state
current and only one supply is required at which shift of
input logic signal is to be done.
Drawbacks
• A high resistive path is required through N2 as compared
to N1 to minimize charge leakage at OUT while OUT_bar
is transitioning to logic low.
• It suffers from higher leakage current and operation is
restricted with high range of input and output supplies.
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9. PARAMETER VALUE
Technology 90nm
VDDH 1.2
VDDL=VIN 0.3
Output voltage 1.2
Temperature -25 to 125
Cout (Load) 1fF – 100fF
Frequency 1MHz
Tools used: Cadence virtuoso IC617
Design Specifications of proposed level shifter
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10. PROPOSED LEVEL SHIFTER CIRCUIT TOPOLOGY
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11. D
VDDL
SELECT
Gate
of PL
MUX_L
D_B
VDDL
SELECTGate
of PR
MUX_R
INTERNAL BLOCKS OF MULTIPLEXER
• The operation of multiplexer is mainly depends on the select input. For MUXL, when the select is HIGH,
nmos transistor will ON and we get output as D and when input is LOW, pmos transistor will ON and we get
output as VDDL and that will fed to transistor PL.
• Similarly for MUXR when select input is HIGH nmos transistor will ON and we get output as VDDL and
when input is LOW pmos transistor will ON and we get DB as output that output will be given to transistor
PR.
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12. Structure of the Proposed Level Shifter
• The proposed level shifter is based on standard level shifter and it mitigates the drawbacks of
existing level shifters and exhibits symmetric operation between the input and output.
• The main advantage of Proposed topology is feedback loop it consists of two multiplexers i.e.,
MUXL and MUXR. Multiplexers are based on pass transistor logic, each multiplexer has two
transistors and the output of MUXs are connected to the gate of the PMOS pull up transistors.
• The output node D_B is connected as select line input of this multiplexers and based upon this
select input multiplexer chooses one of its input as output.
• The proposed configuration eliminates the need of large size NMOS pull down transistors i.e., NL
and NR because the driving voltage of PMOS pull up network is very low (i.e., VDDL).
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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13. Operation of the Proposed Level Shifter
Two possible transition states exists for this LS, when output is High and the next
transition is falling, or when the output is Low and the next transition is rising.
 In First case, when the output is high, upcoming transition is falling. For this, the gate
of PL is connected to node D and the gate of PR is connected to node low supply voltage
“VDDL”, this connection biases PR into cutoff region, which degrades the strength of PR.
Without any contention from PR node D discharges through the pull down transistor NR
and node D_B is charged to full voltage by pull up transistor PL.
 In Second case, when the output is Low, upcoming transition is Rising. For this, the gate
of PR is connected to node low supply voltage “VDDL” and gate of PL is connected to
node D_B, this connection biases PL into cutoff region and degrades the strength of PL.
Without any contention from PL node D_B discharges through the transistor NL and
node D will charges to full voltage by the transistor PR.
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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14. Example of Operation
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15. • The proposed level shifter exhibits higher performance and speed improvement is due to the feedback loop
that sets up the circuit for next transition as compared with the other level shifters.
• This configuration eliminates the need for the large NMOS pull down transistors NL and NR, because the
relevant PMOS pull up transistor is maintained at a low voltage bias for the upcoming transition.
• Symmetric rise and fall transition times of the proposed level shifter is preserved over the maximum
operating range.
• The delay, power and energy of the proposed level shifter has reduced and significant improvement in
performance is achieved.
Advantages
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16. Schematic Implementation
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17. Input and Output response
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18. Simulations
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Fig: Delay vs VDDL across different process corners Fig: Power vs VDDL across different process corners

19. Simulations
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Fig: Delay across different Load conditions Fig: Power across different Load conditions

20. Simulations
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Fig: Delay vs Temp across different process corners Fig: Power vs Temp across different process corners

21. Simulations
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Fig: Histogram of the output response across 1000 samplesFig: Output response across different load conditions

22. Simulations
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Fig: Histogram of the Delay response across 1000 samples Fig: Histogram of the power response across 1000 samples

23. Simulations
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Fig: Total Power Consumed by the circuit

24. Layout of the Proposed circuit
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25. Design
(90nm)
Voltage
conversion
range (V)
Delay
(nS)
Static
Power
(nw)
Average
power
(uW)
Energy/
transition
(fJ)
(EDP)
(fJ nS)
f = 1MHz
Area
(transistor
count)
Results
DCVS
Level shifter
0.5 V to 1.2 V 23.60 112.2 8.242 8.24 194.51 8 simulated
Current
mirror Level
shifter
0.4 V to 1.2 V 13.05 413.2 3.058 3.05 39.90 8
simulated
Wilson
current
mirror Level
shifter
0.4 V to 1.2 V 10.31 413.8 1.812 1.81 18.68 9 simulated
Advanced
Level shifter
[Ref 1]
0.6 V to 1.2 V 6.09 2959 16.63 16.6 101.27 29 simulated
Proposed
Level shifter
0.3 V to 1.2 V 3.65 960 1.43 1.43 5.24 12 simulated
Comparison Table
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26. Conclusion
 The proposed Level Shifter was compared to the existing state-of-the-art LS
circuits using various simulation setups and the better results were obtained for
the proposed level shifter.
 The circuits were designed and simulated in 90nm CMOS technology the
proposed level shifter shifts the input voltage of 0.3 V to 1.2 V. Moreover,
while converting it exhibits an average delay of 3.65 ns and power
consumption of 1.43 µW.
 This level shifter could be used and can produce low power consumption
in spite of the overhead, based on the data obtained from the simulation
as discussed in this work.
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A Multi VDD Wide Voltage Range Up Level Shifter for Smart
SOC Applications
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27. References
1. A. shapiro and E. G. Friedman, “power efficient level shifter for 16nm FinFET
near threshold circuits”, IEEE Trans. Very large scale Integr. (VLSI) Syst., vol. 24,
no. 2, pp. 774-778, Feb. 2016.
2. S. Lütkemeier and U. Ruckert, “A subthreshold to above-threshold level shifter
comprising a Wilson current mirror,” IEEE Trans. CircuitsSyst. II, Exp. Briefs, vol.
57, no. 9, pp. 721–724, Sep. 2010.
3. B. H. Calhoun and D. Brooks, “Can subthreshold and near-threshold circuits go
mainstream?” IEEE Micro, vol. 30, no. 4, pp. 80–85, Jul./Aug. 2010.
4. S.-C. Luo, C.-J. Huang, and Y.-H. Chu, “A wide-range level shifter using a modified
Wilson current mirror hybrid buffer,” IEEE Trans Circuits Syst. I, Reg. Papers, vol.
61, no. 6, pp. 1656–1665,Jun. 2014.
5. M. Lanuzza, P. Corsonello, and S. Perri, “Fast and wide range voltage conversion
in multisupply voltage designs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,
vol. 59, no. 12, pp. 922–926, Mar. 2014.
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