This document describes novel multi-threshold voltage level converters that minimize power consumption without compromising speed. Conventional feedback-based level converters rely on feedback circuits that cause slow response times and short circuit currents. The novel converters proposed use multiple transistor threshold voltages to directly drive high voltage gates from low voltage signals without static currents. When used in an integrated circuit, the multi-threshold converters decrease power by 47% and optimize delay by 50% compared to feedback converters in a 0.18-μm technology.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
A New Soft-Switched Resonant DC-DC ConverterIDES Editor
This paper presents a new soft-switched resonant dcdc
converter using a passive snubber circuit. The proposed
converter uses a new zero voltage and zero current switching
(ZVZCS) strategies to get ZVZCS function. Besides operating
at constant frequency, all semiconductor devices operate at
soft-switching without additional voltage and current stresses.
In order to validate the proposed converter, computer
simulations and experimental results were conducted. The
paper indicates the effective converter operation region of the
soft-switching action and its efficiency improvement results
on the basis of experimental evaluations using laboratory
prototype.
A New Soft-Switched Resonant DC-DC ConverterIDES Editor
This paper presents a new soft-switched resonant
dc-dc converter using a passive snubber circuit. The
proposed converter uses a new zero voltage and zero current
switching (ZVZCS) strategies to get ZVZCS function.
Besides operating at constant frequency, all semiconductor
devices operate at soft-switching without additional voltage
and current stresses. In order to validate the proposed
converter, computer simulations and experimental results
were conducted. The paper indicates the effective converter
operation region of the soft-switching action and its
efficiency improvement results on the basis of experimental
evaluations using laboratory prototype.
DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TE...VLSICS Design
Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed investigation. In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly. In this work adiabatic technique is used for reduction of average power
dissipation. Simulation of 6T SRAM cell has been done for 180nm CMOS technology. It shows that average power dissipation is reduced up to 75% using adiabatic technique and also shows the effect on static noise margin.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
A New Soft-Switched Resonant DC-DC ConverterIDES Editor
This paper presents a new soft-switched resonant dcdc
converter using a passive snubber circuit. The proposed
converter uses a new zero voltage and zero current switching
(ZVZCS) strategies to get ZVZCS function. Besides operating
at constant frequency, all semiconductor devices operate at
soft-switching without additional voltage and current stresses.
In order to validate the proposed converter, computer
simulations and experimental results were conducted. The
paper indicates the effective converter operation region of the
soft-switching action and its efficiency improvement results
on the basis of experimental evaluations using laboratory
prototype.
A New Soft-Switched Resonant DC-DC ConverterIDES Editor
This paper presents a new soft-switched resonant
dc-dc converter using a passive snubber circuit. The
proposed converter uses a new zero voltage and zero current
switching (ZVZCS) strategies to get ZVZCS function.
Besides operating at constant frequency, all semiconductor
devices operate at soft-switching without additional voltage
and current stresses. In order to validate the proposed
converter, computer simulations and experimental results
were conducted. The paper indicates the effective converter
operation region of the soft-switching action and its
efficiency improvement results on the basis of experimental
evaluations using laboratory prototype.
DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TE...VLSICS Design
Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed investigation. In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly. In this work adiabatic technique is used for reduction of average power
dissipation. Simulation of 6T SRAM cell has been done for 180nm CMOS technology. It shows that average power dissipation is reduced up to 75% using adiabatic technique and also shows the effect on static noise margin.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Zuken - Improve pcb quality and cost with concurrent power integrity analysis...Zuken
This presentation will look at the increasing challenges with power distribution systems on modern high-speed PCBs.
This presentation will consider:
a)The problem:
-
IC input impedance behavior
-
Resonance behavior of PDS.
- Role of decoupling capacitors
b)
EDA methodology for concurrent power integrity simulation throughout PCB design process.
Optimized Hybrid Phase Disposition PWM Control Method for Multilevel InverterIDES Editor
This paper presents a new variation of hybrid
phase disposition pulse width modulation technique suitable
for cascaded multilevel inverter. A hybrid PDPWM is
developed based on low frequency PWM and high
frequency Sinusoidal PWM. An optimized sequential
switching scheme introduced in this proposed method to
equalize electro static and electro magnetic stress among the
power devices. It is confirmed that the proposed technique
offers significantly lower switching losses and switching
transitions. Furthermore, the proposed hybrid PDPWM
offers better harmonic performance compared to its
conventional PWM counterpart. Simulation results are
included in this paper in order to confirm the effectiveness
of the proposed technique.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time
variation on switching losses in a Zero Voltage Switching
(ZVS) synchronous buck converter (SBC) circuit. In high
frequency converter circuits, switching losses are
commonly linked with high and low side switches of SBC
circuit. They are activated externally by the gate driver
circuit. The duty ratio, dead time and resonant inductor
are the parameters that affect the efficiency of the circuit.
These variables can be adjusted for the optimization
purposes. The study primarily focuses on varying the
settings of input pulses of the MOSFETs in the resonant
gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter
circuit. Using the predetermined inductor of 9 nH, the
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and
compared to the findings from previous work. It has
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
SBC design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Review of Step down Converter with Efficient ZVS OperationIJRST Journal
This paper presents the review of step down converter with efficient ZVS operation. The designed buck converter uses ZCS technique and the function is realized so that the power form is converted from 12V DC 5V DC (1A). A detailed analysis of zero current switching buck converters is performed and a mathematical analysis of the mode of operation is also presented. In order to reduce the switching losses in associated with conventional converters; resonant inductor and resonant capacitor (LC resonant circuit) is applied which helps to turn on-off the switch at zero current. The dc-dc buck converter receives the energy from the input source, when the switch is turned-on. The buck–buck converters have characteristics that warrant a more detailed study. The buck converters under discontinuous conduction mode /continuous conduction mode boundary.
A Multi VDD Wide Voltage Range Up Level Shifter For Smart SoC Applicationsbaba fayaz
This paper presents a wide voltage range up level
shifter which is capable to convert or shift low levels of the input
voltage into high output voltage with less delay and power
dissipation. power consumption has become a major problem
in modern integrated circuits and system on chip (SoC). To
reduce static power as well as dynamic power consumption scale
down the supply voltages and operate the circuit near-threshold
voltages and also using multiple supply voltages for critical and
noncritical blocks. The proposed design in a 90nm technology
that shifts the input voltage of 0.3 V into 1.2 V of the output
voltage. For a VDDL of 0.3 V and VDDH of 1.2 V, it exhibits
delay of 3.65 ns, the average power consumption of 1.43 uW and energy per one transition is 1.43 pJ at 1 MHz input pulse signal with equal rise time and fall time.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Zuken - Improve pcb quality and cost with concurrent power integrity analysis...Zuken
This presentation will look at the increasing challenges with power distribution systems on modern high-speed PCBs.
This presentation will consider:
a)The problem:
-
IC input impedance behavior
-
Resonance behavior of PDS.
- Role of decoupling capacitors
b)
EDA methodology for concurrent power integrity simulation throughout PCB design process.
Optimized Hybrid Phase Disposition PWM Control Method for Multilevel InverterIDES Editor
This paper presents a new variation of hybrid
phase disposition pulse width modulation technique suitable
for cascaded multilevel inverter. A hybrid PDPWM is
developed based on low frequency PWM and high
frequency Sinusoidal PWM. An optimized sequential
switching scheme introduced in this proposed method to
equalize electro static and electro magnetic stress among the
power devices. It is confirmed that the proposed technique
offers significantly lower switching losses and switching
transitions. Furthermore, the proposed hybrid PDPWM
offers better harmonic performance compared to its
conventional PWM counterpart. Simulation results are
included in this paper in order to confirm the effectiveness
of the proposed technique.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time
variation on switching losses in a Zero Voltage Switching
(ZVS) synchronous buck converter (SBC) circuit. In high
frequency converter circuits, switching losses are
commonly linked with high and low side switches of SBC
circuit. They are activated externally by the gate driver
circuit. The duty ratio, dead time and resonant inductor
are the parameters that affect the efficiency of the circuit.
These variables can be adjusted for the optimization
purposes. The study primarily focuses on varying the
settings of input pulses of the MOSFETs in the resonant
gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter
circuit. Using the predetermined inductor of 9 nH, the
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and
compared to the findings from previous work. It has
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
SBC design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Review of Step down Converter with Efficient ZVS OperationIJRST Journal
This paper presents the review of step down converter with efficient ZVS operation. The designed buck converter uses ZCS technique and the function is realized so that the power form is converted from 12V DC 5V DC (1A). A detailed analysis of zero current switching buck converters is performed and a mathematical analysis of the mode of operation is also presented. In order to reduce the switching losses in associated with conventional converters; resonant inductor and resonant capacitor (LC resonant circuit) is applied which helps to turn on-off the switch at zero current. The dc-dc buck converter receives the energy from the input source, when the switch is turned-on. The buck–buck converters have characteristics that warrant a more detailed study. The buck converters under discontinuous conduction mode /continuous conduction mode boundary.
A Multi VDD Wide Voltage Range Up Level Shifter For Smart SoC Applicationsbaba fayaz
This paper presents a wide voltage range up level
shifter which is capable to convert or shift low levels of the input
voltage into high output voltage with less delay and power
dissipation. power consumption has become a major problem
in modern integrated circuits and system on chip (SoC). To
reduce static power as well as dynamic power consumption scale
down the supply voltages and operate the circuit near-threshold
voltages and also using multiple supply voltages for critical and
noncritical blocks. The proposed design in a 90nm technology
that shifts the input voltage of 0.3 V into 1.2 V of the output
voltage. For a VDDL of 0.3 V and VDDH of 1.2 V, it exhibits
delay of 3.65 ns, the average power consumption of 1.43 uW and energy per one transition is 1.43 pJ at 1 MHz input pulse signal with equal rise time and fall time.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Fuzzy Logic Controller Based on Voltage Source Converter-HVDC with MMC TopologyIJMTST Journal
This paper presents Modular Multi Level Converters (MMC) are used for high voltage high power DC to AC conversion. The MMCs with increased number of levels offer close to sine wave operation with reduced THD on the AC side. This is a new type of voltage source converter (VSC) topology. The use of this converter in a high-voltage direct current (HVDC) system is called by a MMC-HVDC system. The MMC-HVDC has the advantage in terms of scalability, performance, and efficiency over two-and three-level VSC-HVDC. The proposed HVDC system offers the operational flexibility of VSC based systems in terms of active and reactive power control, in addition to improved ac fault ride-through capability and the unique feature of current-limiting capability during dc side faults. The proposed VSC-HVDC system, in this project assesses its dynamic performance during steady-state and network alternations, including its response to AC and DC side faults. In this project using a fuzzy controller and the proposed topology is implemented in MATLAB/SIMULINK environment and the simulation results are observed.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
A Non-isolated Hybrid Boost Three Level DC-DC Converter with High Step-up Con...IJSRD
Nowadays renewable energy sources are increasingly used to meet the world’s increasing demand for energy. In grid connected photovoltaic (PV) generation systems, a single PV array can supply lower dc voltage. In order to connect PV array to the grid, the voltage has to be boosted to higher levels that is demanded by the grid side. A hybrid boost three level dc-dc converter based on traditional single phase three level diode clamped inverter can be used to connect low voltage PV array to the high voltage grid. Only one inductor, two capacitors in series, and those power switches and diodes, which are needed to establish the topology with high voltage gain. Pulse width modulation (PWM) control method is used for the control of power switches. Power switches of this converter works with duty cycles closer to 0.5. This hybrid three level dc-dc converter works with high gain without a transformer or coupled inductor. In addition, voltages across the capacitors in series are balanced in both steady and dynamic states. Therefore capacitor voltage balancing circuitry can be avoided. Also, blocking voltages of the power switches are half of the output dc voltage. This hybrid converter is suitable for PV generation systems connected to the grid with parallel- connected low-voltage PV arrays.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IMPLEMENTATION OF DISCONTINUOUS INDUCTOR CURRENT MODE IN CUK CONVERTERS FED B...Journal For Research
This paper presents a bridgeless Cuk converter-fed brushless DC (BLDC) motor drive. A Bridgeless Cuk converter is constructed to operate at discontinuous inductor current mode to improve the quality of power and power factor at the AC mains for better speed control. The bridgeless converter is designed for obtaining the low conduction losses and requirement of low size of heat sink for the switches. TI-TMS320-F2812-based Digital Signal Processor (DSP) is used for the development of the hardware prototype of proposed BLDC motor drive.
Extremely high duty cycle of boost converter may result in higher conduction losses. To achieve a high
conversion ratio without operating at extremely high duty ratio, some converters based on transformers or coupled
inductors or tapped inductors have been provided. However, the leakage inductance in the transformer, coupled
inductor or tapped inductor will cause high voltage spikes in the switches and reduce system efficiency. A novel
single switch cascaded dc-dc converter of boost and buck boost converters have extended voltage conversion ratio
to d/(1-d)2. The features of the converter are high voltage gain; only one switch for realizing the converter, the
number of magnetic components is small etc. So comparing with other topologies cascaded converter is more
effective. Simulation of the converter for a dc input voltage and fixed duty cycle was done, and the same was
verified experimentally for a low input voltage. The software used for simulation was MatlabR2014a
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Power Dissipation of VLSI Circuits and Modern Techniques of Designing Low Pow...IJSRD
This paper focus on the various sources of power dissipation in modern VLSI circuits. This paper also discuss the importance of designing low power VLSI circuits along with various techniques of power reduction and its advantages and disadvantages. It is basically a comparative study between various power reduction techniques in modern VLSI circuits.
A hybrid converter topologies which can supply simultaneously AC as well as DC from a single DC source. The new Hybrid Converter is derived from the single switch controlled Boost converter by replacing the controlled switch with voltage source inverter (VSI). This new hybrid converter has the advantages like reduced number of switches as compared with conventional design having separate converter for supplying AC and DC loads, provide DC and AC outputs with an increased reliability, resulting from the inherent shoot through protection in the inverter stage. For controlling switches PWM control, based upon unipolar Sine-PWM is described.
1. LOW POWER AND OPTIMAL DELAY MULTI THRESHOLD VOLTAGE LEVEL
CONVERTERS
Abstract: directly driven by the low voltage level signal
Minimizing power consumption without provided by the driver. The operation of the pull-up
compromising speed in any integrated circuit (IC) transistors is controlled by an internal feedback
is a challenge. Employing multiple supply mechanism isolated from the low voltage swing
voltages (multi-Vdd) is an effective technique to input signal, thereby avoiding the formation of
achieve this. In order to minimize the power static dc current paths within the circuit[1].
dissipation in an integrated circuit, voltage level (a.i) Feedback Level converter:
converter circuits are required. There are two
novel multi-threshold voltage (multi-Vth) based
level converters are proposed. When these novel
level converters are applied in an integrated
circuit and compared with the previous level
converter which are of feed back based circuit.
The power dissipation is decreased in this
approach up to 47% and the Delay is optimized by
50% with multi threshold based level converter in
a 0.18- µm technology.
Index: multi-threshold, level converters, power
dissipation
I. Introduction
Power dissipation reduction in an Figure 1: Feedback level converter
integrated circuit (ICs) is the most demanding issue
for present chip-design. When a low voltage level The feedback-based level converter is shown in
signal directly drives a gate that is connected to a Figure 1: transistor M1 and M2 experience a low
higher supply voltage, the pull-up network of the gate overdrive voltage (VDDL-VTH) during the
receiver cannot be fully turned off. A receiver operation of the circuit. Transistor M1 and M2 need
driven by a low voltage level signal therefore to be sized larger to produce more current as
produces static dc current. In order to suppress this compared to the transistor M 3 and M4 ,
dc current, specialized voltage level converter respectively. When the input is at 0 V is turned off.
circuits are employed between a low voltage driver Node1 is charged to VDDL.M1 is turned on. Node 3 is
and a full voltage level receiver. The main cause discharged to 0 V turning M4 on. Node2 is charged
for static power dissipation is due to low level to turning M3 off. The output is pulled down to 0
signal the voltage level converter circuits are V. When the input transitions to VDDL, M2 is turned
inserted in critical region of integrated circuit to on. Node1 is discharged, turning M1 off. Node2 is
converter the low level signal to high level signal discharged, turning M3on. Node3 is charged up to
which is the main cause for power dissipation, VDDH turning M4 off. The output transitions to
previously level converters are of feed back based VDDH. A feedback loop, isolated from the input,
which rely on some feed back circuit for controls the operation of M3 and M4 during both
controlling the operation of pull up network transitions of the output.
transistor to avoid power dissipation within the Due to the transitory contention between the
level converter but these feedback based level pull-up and the pull-down networks and the large
converters have many disadvantages like circuit size of the NMOS transistors (M1 and M2),
has slow response due to feed back circuit it also however, Feedback level converter dissipates
suffers form short circuit current and trapper significant short-circuit and dynamic switching
inverters are required to drive the circuit at very power. To maintain functionality with the lower
low voltage this further increases the power values of VDDL, the sizes of M1 and M2 need to be
consumptions, to over avoid these the novel multi- further increased in order compensate for the gate
Vth based level converters are proposed. overdrive degradation. The load seen by the
previous stage is therefore increased, thereby
II. Implementation further degrading the speed and increasing the
(a)Feedback-Based Level Converters: power consumption. Tapered buffers are required
The feedback-based level converters rely to drive M1 and M2 at very low voltages. These
on some form of feedback circuitry for controlling tapered buffers further increase the power
the operation of the pull-up network transistors in consumption of feedback level converter.
order to avoid static dc current within the level
converter. In feedback-based voltage level (b) Multi-Vth level converters:The Multi-Vth
converter circuits, the pull-up transistors are not level converters employ a multi-CMOS technology
978-1-4244-8971-8/10$26.00 c 2010 IEEE
2. in order to eliminate the static dc current. The high the output node is initially charged to VDDH-Vthn-M1-
threshold voltage pull-up transistors in this level Vthn-M3 and VDDL-Vthn-M1 through M1.
converter are directly driven by the low level
signals without producing a static dc current Multi-Vth level converter has fewer
problem. transistors as compared feedback level converters.
(b.i) Multi-Vth Level converters (MLC1): Furthermore, the elimination of the slow feedback
circuitry reduces the short-circuit power of Multi-
Vth level converter as compared to feedback based
level converter. No increase in the size of M1 is
required for achieving functionality at lower input
voltages with the proposed circuit. Therefore,
particularly for the very low values of VDDL, Multi-
Vth level converter consumes lower power,
occupies significantly smaller area, and imposes a
much smaller load capacitance[1].
(c) Application of level converter in an
integrated circuit:
Figure 3: Multi-Vth Level converter (MLC1)
The level converter is shown in Figure 3 Multi
Vth level converter is composed of two cascaded
inverters with dual- transistors. The threshold
voltage of M2(VTH-M2) is more negative (higher
׀Vth )׀for avoiding static dc current in the first
inverter when the input is at VDDL.׀Vth-M2 ׀is
required to be higher than VDDH-VDDL for
eliminating the static dc current. The Multi Vth
level converter operates as follow input is at 0 V,
M2 is turned on.M1 is cutoff.Node1 is pulled up to
VDDH. The output is discharged to 0 V. When the Figure 5.Circuit in which level converters are
input transitions to VDDL, M1 is turned on. M2 is inserted into needed portions.
turned off since VGS, M2>VTH, M2. Node1 is Circuit with shaded portion activates in VDDL
discharged to 0 V. The output is charged to VDDH[1]. In Figure 5 the integrated circuit has a
(b.ii) Multi-Vth Level converters (MLC2): critical path from flip-flop A (FF A) to flip-flop B
(FF B). Due to excessive slack in the gates or flip-
flops off the critical path, the timing constraints
could be met even if we partially use VDDL gates.
However, the structure has a problem while
implementing it in CMOS large scale integrated
circuits. DC current flows at a VDDH gate due to the
direct connection of a VDDL gate to a VDDH one.
This becomes a problem in low-power CMOS
circuits. A typical way to block the static current is
to insert a level-converter circuit in between the
circuit where there is direct connection for low
voltage to higher voltage [2] [4]. The level
converter converts the voltage level from VDDL to
VDDH.
Figure 4: Multi-Vth Level converter (MLC2)
The level converter is shown in Figure 3
Multi-Vth level converter is composed of two
cascaded inverters with dual- transistors. In this
level converter when the input is at 0 V, Node 1 is
pulled high to VDDL turning M2 off .The output
node is discharged to 0 V through the pass
transistor M1. When the input transitions to VDDL,
3. III. Results:
Figure 6.Layout for the circuit of an IC in which Figure 8.Layout for the circuit of an IC in which
feed back level converters are inserted into needed Multi Vth level converters are inserted into needed
portions. portions.
In Figure 6 Integrated circuits feed back level In Figure 8 Integrated circuits Multi Vth
converters is inserted where is a transfer of low level converters is inserted where is a transfer of
voltage level to high voltage level to avoid the low voltage level to high voltage level to avoid the
static current dissipation, the input is given across static current dissipation, the input is given across
the filp flop A and the output is take across filp the filp flop A and the output is take across filp
flop B then power and delay is calculated for this flop B then power and delay is calculated for this
integrated circuit. integrated circuit.
Figure 9.Waveform for the circuit of an IC in
which Multi Vth level converters are inserted into
needed portions.
Figure 7.Waveform for the circuit of an IC in
Figure 9 shows the output waveforms of
which feed back level converters are inserted into
the above layout where the Multi Vth level
needed portions.
converters are inserted at critical region, the output
is taken across filp flop B, power and delay is
Figure 7 shows the output waveforms of the above
calculated.
layout where the feedback level converters are
inserted at critical region, the output is taken across
filp flop B, power and delay is calculated.
4. power dissipation and the speed is increased. This
proves the circuit that having multi threshold and
multi voltage level converters will reduce the
(a) Comparison of power and delay at power dissipation with out scarifying speed.
different values References:
Using different level converters in an [1] Sherif A. Tawfik and Volkan Kursun,”Low
integrated circuit the delay and power is calculated Power and High Speed Multi Threshold Voltage
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Integr. (VLSI) syst., vol 17, No.5.May2009
Optimized Optimized [2] Stephan Henzler, Power Management of
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Figure 8. Plot for percentage of delay and power 495–498.
with respective voltage
In the Figure 8 the power is optimized to 47% and
delay has reduced to 50% with the different input
voltage levels.
IV Conclusion:
The aim of this paper is to demonstrate
the successful implementation of the “Multi Level
Converter”. After a brief overview of the
background information, design considerations
with particular interest on the selection of voltage
level converter, the operation of the multi threshold
voltage level converter were discussed. This
particularly made to decrease the power dissipation
without affecting speed. It is found to be 47% and
Delay is optimized by 50% Thus, the feedback
based level converter is replacing with the multi
threshold based level converter to decrease the