Microcontroller pic 16 f877 registers memory ports

Microcontroller (PIC)
PIC 16F877 Microcontroller: Registers, I/O Ports, Memory
Nilesh Bhaskarrao Bahadure
Ph.D, ME, BE
nbahadure@gmail.com
https://www.sites.google.com/site/nileshbbahadure/home
July 1, 2021
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Overview
1 Syllabus
2 Course Objectives & Outcomes
3 Objectives
4 Architecture of PIC16F877 Microcontroller
CPU Registers
Parallel I/O Ports
5 Memory Organization of PIC16F877
6 Special Function Register
Status Register
Option Register
PCON Register
7 Data EEPROM and FLASH Program Memory
PIR2 Register
PIE2 Register
8 University Questions
9 References
10 Thank You
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Syllabus
Unit Heading No. of Lectures
Unit 2: PIC 16F877 Microcon-
troller
No of lectures - 14
PIC 16F877- features, architecture, functional pin description, pro-
gram memory and data memory organization, STATUS register, OP-
TION REG register, Power Control Register (PCON), Data EEPROM
and FLASH Program Memory.
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Course Objectives
1 To expose the students to the fundamentals of PIC Microcontroller
16F877 architecture and its Peripherals.
2 To introduce the advanced features in PIC Microcontroller 16F877.
3 To make student develop and practice assembly language and C
language programming techniques
4 To enable student demonstrate and perform hardware interfacing and
design.
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Course Outcomes
At the end of the course, the student shall be able to,
1 Describe how PIC microcontroller and its peripherals function.
2 Interpret advanced features in PIC Microcontroller 16F877.
3 Program an embedded system in assembly and C.
4 Design, implement and test a single-processor embedded systems for
real-time applications
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Objectives
Upon completion of this chapter, you will be able to:
Examine the data RAM file register of the PIC
microcontrollerManipulate data using the WREG and MOVE
instructionsPerform simple operations such as ADD and MOVE using
the file register and access bank in the PIC microcontrollerExplain the
purpose of the status registerDiscuss data RAM memory space
allocation in the PIC microcontrollerList SFR’s of the PIC
microcontrollerUnderstand the RISC and Harward architectures of the
PIC microcontroller
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Architecture of PIC16F877 Microcontroller
1
2
3
4
5
6
7
8
Figure : Basic Architecture of PIC Microcontroller
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Architecture of PIC16F877 Microcontroller...
Figure : PIC16F877 MCU Block Diagram 8 / 79

Architecture of PIC16F877 Microcontroller...
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CPU Registers
The CPU registers are used in the execution of the instruction of the PIC
microcontroller. The PIC PIC16F877 Microcontroller has the following
registers.
1 Working Register-W (Similar to Accumulator)
2 Status Register
3 FSR - File Select Register (Indirect Data memory address pointer)
4 INDF
5 Program Counter
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Working Register:
Working Register:
Working Register is used by many instructions as the source of an operand.
It also serves as the destination for the result of instruction execution and
it is similar to accumulator in other microprocessors and microcontrollers.
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Status Register:
Status Register:
go to status register
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FSR -(File Select Register):
FSR -(File Select Register):
It is the pointer used for indirect addressing. In the indirect addressing
mode the 8-bit register file address is first written into FSR. It is a special
purpose register that serves as an address pointer to any address through
out the entire register file.
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INDF - (Indirect File):
INDF - (Indirect File):
It is not a physical register addressing but this INDF will cause indirect
addressing. Any instruction using the INDF register actually access the
register pointed to by the FSR.
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PROGRAM COUNTER
PROGRAM COUNTER
PIC PIC16F877A has a 13 bit program counter in which PCL is the lower
8-bits of the PC and PCLATH is the write buffer for the upper 5 bits of
the PC.
Figure : Program Counter Regiter
PCLATH (program counter Latch can be read or from or written to
without affecting the Program Counter(PC).The upper 3 bits of PCLATH
remain zero.It is only when PCL is written to that PCLATH is
automatically written into the PC at the same time.
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Parallel I/O Ports
Most of the PIC16cx/7x family controllers have 33 I/O lines and five I/O
ports They are PORT A, PORT B, PORT C , PORT D and PORT E.
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PORT A:
PORT A:
Port A is a 6-bit wide bi-directional port. Its data direction register is
TRISA setting TRISA bit to 1 will make the corresponding PORT A Pin an
input. Clearing a TRIS a bit will make the corresponding pin as an output.
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PORT B:
PORT B:
Port B is an 8-bit wide, bi-directional port. Four of the PORT B pins RB7
- RB4 have an interrupt-on- change feature. Only the pins configured as
inputs can cause this interrupt to occur.
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PORT C and D:
PORT C
Port C is an 8-bit wide, bidirectional port. Bits of the TRISC Register
determine the function of its pins. Similar to other ports, a logic one 1 in
the TRISC Register configures the appropriate port pin as an input.
PORT D:
Port D is an 8-bit wide bi-directional port. In addition to I/O port, Port D
also works as 8-bit parallel slave port or microprocessor port. When
control bit PSPMODE (TRISE:4) is set.
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PORT E:
PORT E:
It is a 3-bit bi-directional port. Port E bits are multiplexed with analog
inputs of ADC and they serve as control signals (RD, WR, CS) for parallel
slave port mode of operation.
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Memory Organization of PIC16F877
The memory of a PIC 16F877 chip is divided into 3 sections. They are
1 Program memory
2 Data memory and
3 Data EEPROM
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Program memory
Program memory
Program memory contains the programs that are written by the user. The
program counter (PC) executes these stored commands one by one.
Usually PIC16F877 devices have a 13 bit wide program counter that is
capable of addressing 8K14 bit program memory space. This memory is
primarily used for storing the programs that are written (burned) to be
used by the PIC. These devices also have 8K*14 bits of flash memory that
can be electrically erasable /reprogrammed. Each time we write a new
program to the controller, we must delete the old one at that time. The
figure below shows the program memory map and stack.
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Program memory
Program counters (PC) is used to keep the track of the program execution
by holding the address of the current instruction. The counter is
automatically incremented to the next instruction during the current
instruction execution.
The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack.
The stack space is not a part of either program or data space and the
stack pointers are not readable or writable. In the PIC microcontrollers,
this is a special block of RAM memory used only for this purpose.
Each time the main program execution starts at address 0000 - Reset
Vector. The address 0004 is “reserved” for the “interrupt service routine”
(ISR).
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PIC16F87XA Data Memory Organization
Data memory
The data memory of PIC16F877 is separated into multiple banks which
contain the general purpose registers (GPR) and special function registers
(SPR). According to the type of the microcontroller, these banks may
vary. The PIC16F877 chip only has four banks (BANK 0, BANK 1, BANK
2, and BANK4). Each bank holds 128 bytes of addressable memory.
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Data memory
The banked arrangement is necessary because there are only 7 bits are
available in the instruction word for the addressing of a register, which
gives only 128 addresses. The selection of the banks are determined by
control bits RP1, RP0 in the STATUS registers Together the RP1, RP0
and the specified 7 bits effectively form a 9 bit address. The first 32
locations of Banks 1 and 2, and the first 16 locations of Banks2 and 3 are
reserved for the mapping of the Special Function Registers (SFR’s).
BANK RP1 RP0
0 0 0
1 0 1
2 1 0
3 1 1
A bit of RP1 & RP0 of the STATUS register selects the bank access.
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Data EEPROM and FLASH
The data EEPROM and Flash program memory is readable and writable
during normal operation (over the full VDD range). This memory is not
directly mapped in the register file space. Instead, it is indirectly addressed
through the Special Function Registers. There are six SFRs used to read
and write this memory:
1 EECON1
2 EECON2
3 EEDATA
4 EEDATH
5 EEADR
6 EEADRH
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The EEPROM data memory allows single-byte read and writes. The Flash
program memory allows single-word reads and four-word block writes.
Program memory write operations automatically perform an erase-before
write on blocks of four words. A byte write in data EEPROM memory
automatically erases the location and writes the new data
(erase-before-write). The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip charge pump, rated to
operate over the voltage range of the device for byte or word operations.
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Special Function Register
The special function registers are also memory registers which is used for
special dedicated functions. These registers perform various dedicated
functions inside the PIC chip. Each special function inside this PIC chip is
controlled by using these registers. These registers are used by the CPU
and peripheral modules for controlling the desired operation of the device.
These registers are normally implemented as in the form of static RAM
memory. A list of these registers is given in the tables below. The Special
Function Registers can be classified into two sets: core (CPU) and
peripheral. Those registers associated with the core functions are
described in detail in this section. The figures below shows SFR memory
map of PIC16F877.
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Status Register
The Status register contains the arithmetic status of the Arithmetic Logic
Unit, the Reset status of the PIC and the Bank Selection bits, direct and
indirect. The Status register is accessible from all 4 banks. The bits of the
Status register as as follows:
Status Register
Bit 7 6 5 4 3 2 1 0
Access R/W R/W R/W R R R/W R/W R/W
Initial 0 0 0 1 1 x x x
Name IRP RP1 RP0 -TO -PD Z DC C
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Status Register... I
1 Bit 0: C: Carry/-Borrow:
This bit is Readable and Writable and after a reset it’s value will be
unknown. If an instruction executed has an effect on this bit, then
this bit becomes automatically and temporarily Read Only. The Carry
bit watches if a carry-out from the MSB bit occurs. The values it can
get are:
0: No carry-out from the MSB of the result occurred
1: A carry-out from the MSB of the result occurred
2 Bit 1: DC: Digit Carry/-Borrow:
this bit becomes automatically and temporarily Read Only. The Digit
Carry bit watches if a carry out from the 4th lower order of the byte is
occurred. The values it can get are:
0: No carry-out from 4th lower order of the byte occurred
1: A carry-out from the 4th lower order of the byte occurred
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Status Register... II
3 Bit 2: Z: Zero
this bit becomes automatically and temporarily Read Only. The Zero
bit watches if the result of an arithmetic or logic operation was zero.
The values it can get are:
0: The result of an arithmetic or logic operation was not zero
1: The result of an arithmetic or logic operation was zero
4 Bit 3: -PD: Power Down
This bit is Read Only and after a reset it will get the value 1. The
Power Down bit watches if the ’SLEEP’ instruction was executed.
0: The ’SLEEP’ instruction was executed
1: Power Up or the ’CLRWDT’ instruction was executed
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Status Register... III
5 Bit 4: -TO: Time Out
This bit is Read Only and after a reset it will get the value 1. The
Power Down bit watches if a Watchdog timer time out occurred. The
values it can get are:
0: A Watchdog timer time out occured
1: Power Up, ’SLEEP’ or ’CLRWDT’ instruction was executed
6 Bit 6 to 5: RP1 : 0 : Register Bank Selection
Those bits are Readable and Writable and after a reset it will all get
the value 0. Their task is to select the active Register Bank in use.
00: Bank 0 is selected
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Status Register... IV
7 Bit 7: IRP: Register Bank Selection used with indirect addressing
During the indeterminate pages of this book, the indirect addressing
shall be discussed and explained. The indirect addressing is a way of
accessing registers (General Purpose or Special Function Registers)
without directly accessing their memory position, but throughout an
indirect addressing register. When this register is used, the current
bank selected is different than the indirect current bank selected. The
values it can get are:
0: Indirect addressing current bank selected is Bank 0 and Bank 1
1: Indirect addressing current bank selected is Bank 2 and Bank 3
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Option Register
The Option Reg register is a Readable and Writable register that is used
to control some modules of the PIC. This register is only available from
bank 1 and bank 3. The bits of the Option Reg register as as follows:
Option Reg Register
Bit 7 6 5 4 3 2 1 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Initial 1 1 1 1 1 1 1 1
Name -RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0
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Option Reg Register... I
1 Bit 2 to 0: PS2:0 - Prescaller rate selection
Those bits are Readable and Writable and after a reset they will get
the value ’1’. They are used to set the Prescaller rate. The values it
can get are:
Bit value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128
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Option Reg Register... II
2 Bit 3: PSA - Prescaller Assignment
This bit is Readable and Writable and after a reset it will get the
value 1. This bit is used to assign the prescaller to to the Watchdog
timer or the Timer 0 module. The values it can get are:
0: The prescaller is assigned to the Timer 0 module (TMR0)
1: The prescaller is assigned to the Watchdog timer (WDT)
3 Bit 4: TOSE - Timer 0 Source Edge Select
value 1. It is used to select the RA4/TOCKI pin clock edge (High to
Low or Low to High) on which the Timer 0 will count. The values it
can get are:
0: Increment on Low to High
1: Increment on High to Low
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Option Reg Register... III
4 Bit 5: T0CS - Timer 0 Clock Source Select
value 1. This bit will define the Timer 0 module clock source. It can
be either the RA4/TOCKI pin or the Internal Instruction Cycle Clock
(CLKO). The values it can get are:
0: Timer 0 clock source is the Internal instruction cycle clock (CLKO)
1: Timer 0 clock source is the RA4/TOCKI pin
5 Bit 6: INTEDG - RB0/INT pin Interrupt Edge Select
This bit is Readable and Writable and after a reset it will get the value
1. By altering this bit, you can select the RB0/INT pin pulse edge
that the RB0/INT interrupt will occur. The values it can get are:
0: The RB0/INT interrupt will occur on the falling edge of the
RB0/INT pin
1: The RB0/INT interrupt will occur on the rising edge of the
RB0/INT pin
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Option Reg Register... IV
6 Bit 7: -RBPU - PORTB Pull-up Enable
value 1. The RB ports have an internal programmable pull-up resistor
to minimize the use of external pull-up resistors when needed. This
bit will enable or disable those resistors. The values it can get are:
0: The RB pull-up resistors are enabled
1: The RB pull-up resistors are disabled
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PCON Register
The Power Control (PCON) register contains flag bits to allow
differentiation between a Power-on Reset (POR), a Brown-out Reset
(BOR), a Watchdog Reset (WDT) and an external MCLR Reset. The
structure of this register is given below.
Option Reg Register
Bit 7 6 5 4 3 2 1 0
Access U-0 U-0 U-0 U-0 U-0 U-0 R/W R/W
Name - - - - - - POR BOR
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PCON Register... I
1 bit 7-2: Unimplemented: Read as ‘0’
2 bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a
Power-on Reset occurs)
3 bit 0: BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a
Brown-out Reset occurs)
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Data EEPROM and FLASH Program Memory The data EEPROM and
Flash program memory is readable and writable during normal operation
by electrically erasing or direct writing methods. The memory of this
register space is not directly mapped in the register memory space. It can
be indirectly addressed through SFR registers. The commonly used SFR
registers (for read and write this memory) for this purpose are given below.
1 EECON1
2 EECON2
3 EEDATA
4 EEDATH
5 EEADR
6 EEADRH
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Data EEPROM and FLASH Program Memory... When interfacing a data
memory location into this EEPROM, the EEDATA holds 8 bit data (for
reading and writing) and the register EEADR holds the address of the
EEPROM location. The PIC16F8XX devices have 128 or 256 bytes of
data EEPROM (depends on the type of devices).
The address range of EEPROM memory starts from 00h to FFh (256 byte
devices) and 80h to FFh (128 bytes devices). When interfacing the
program memory block, the EEDATA and EEDATH registers form a
two-byte word that holds the 14-bit data for read/write and the EEADR
and EEADRH registers form a two-byte word that holds the 13-bit address
of the program memory location being accessed. These devices have 4 or
8K words of program Flash, with an address range from 0000h to 0FFFh
for the PIC16F873A/874A and 0000h to 1FFFh for the
PIC16F876A/877A. Addresses above the range of the respective device
will wrap around to the beginning of program memory. The EEPROM
data memory allows single-byte read and writes.
The Flash program memory allows single-word reads and four-word block
writes. Program memory write operations automatically perform an
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erase-before write on blocks of four words. A byte write in data EEPROM
memory automatically erases the location and writes the new data
(erase-before-write). The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip charge pump, rated to
operate over the voltage range of the device for byte or word operations.
When the device is code-protected, the CPU may continue to read and
write the data EEPROM memory.
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Data EEPROM and FLASH Program Memory...
EEADR and EEADRH
EEADR register pair can be address up to a maximum of 256 bytes of
data EEPROM or up to a maximum of 8K words of program EEPROM.
When selecting a data address value, only the LS (least significant) Byte
of the address is written to the EEADR register. When selecting a
program address value, the MS Byte (most significant) of the address is
written to the EEADRH register and the LS Byte (least significant) is
written to the EEADR register. If the device contains less memory than
the full address reach of the address register pair, the Most Significant bits
of the registers are not implemented. For example, if the device has 128
bytes of data EEPROM, the Most Significant bit of EEADR is not
implemented on access to data EEPROM.
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EECON1 and EECON2 Registers
EECON1 is memory accessible control register. The control bit, EEPGD,
determines the type of memory that will be access (program memory or
data memory). When clear, as it is when reset, any subsequent operations
will operate on the data memory. When set, any subsequent operations
will operate on the program memory.
Control bits, RD and WR, initiate read and write or erase, respectively.
These bits cannot be cleared, only set, in software. They are cleared in
hardware at completion of the read or write operation. The inability to
clear the WR bit in software prevents the accidental, premature
termination of a write operation. The WREN bit, when set, will allow a
write or erase operation. On power-up,the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is interrupted by a
MCLR or a WDT Time-out Reset during normal operation. In these
situations, following Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged in the EEDATA and
EEADR registers. Interrupt flag bit, EEIF in the PIR2 register, is set when
the write is complete. It must be cleared in software. EECON2 is not a 50 / 79

EECON1 Register
Bit 7 6 5 4 3 2 1 0
Access R/W-X U-0 U-0 U-0 R/W-X R/W-0 R/S-0 R/S-0
Name EEPGD – – – WRERR WREN WR RD
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EECON1 Register... I
1 Bit 7 (EEPGD): Program/Data EEPROM Select bit which select
program memory or data memory according to the applications. If
this bit is ’1’, it can be access program memory and if this bit is ’0’ ,it
can be access data memory.
1 = Accesses program memory
0 = Accesses data memory
2 Bit 6-4 (Unimplemented): Read as ’0’
3 Bit 3 (WRERR): this bit used as an EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any
WDT Reset during normal operation
0 = the write operation completed
4 Bit 2 (WREN): this bit generally acts as an EEPROM Write Enable
bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
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EECON1 Register... II
5 Bit 1 (WR): Write Control bit which control the writing instructions.
1 = Initiates a write cycle. The bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
6 Bit 0 (RD): Read Control bit which controls the read instructions.
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit
can only be set (not cleared) in software.
0 = Does not initiate an EEPROM read
Registers/bites that associated with data EEPROM and FLASH
program memories in PIC16F877 are given in the table below.
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Figure : Data EEPROM and FLASH Program Memory
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PIR2 Register The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt, EEPROM write operation
interrupt and the comparator interrupt. The structure of this register is
given below.
PIR2 Register
Bit 7 6 5 4 3 2 1 0
Access U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
Name – CMIF – EEIF BCLIF – – CCP2IF
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PIR2 Register... I
1 Bit 7 Unimplemented: Read as ’0’
2 Bit 6 (CMIF): Comparator Interrupt Flag bit
1 = the comparator input has changed (must be cleared in software)
0 = the comparator input has not changed
4 Bit 4 (EEIF): EEPROM Write Operation Interrupt Flag bit.
1 = the write operation completed (must be cleared in software)
0 = the write operation is not complete or has not been started
5 Bit 3 (BCLIF): Bus Collision Interrupt Flag bit.
1 = A bus collision has occurred in the SSP when configured for I2C
Master Mode
0 = No bus collision has occurred
6 Bit 2-1 Unimplemented: Read as ’0’
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PIR2 Register... II
7 Bit 0 (CCP2IF): CCP2 Interrupt Flag bit. This also works in three
modes. They ere
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
This mode is not used.
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PIE2 Register The PIE2 register contains the individual enable bits for the
CCP2 peripheral interrupt, the SSP bus collision Interrupt, EEPROM write
operation interrupt and the comparator interrupt. The structure of this
register is given below.
PIE2 Register
Bit 7 6 5 4 3 2 1 0
Access U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
Name – CMIE – EEIE BCLIE – – CCP2IE
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PIE2 Register... I
2 Bit 6 (CMIF): Comparator Interrupt Enable Flag bit
1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
4 Bit 4 (EEIE): EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
5 Bit 3 (BCLIE): Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
6 Bit 2-1 Unimplemented: Read as ’0’
7 Bit 0 (CCP2IE): CCP2 Interrupt Enable bit.
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
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Que - 1
2018 (SLR - TJ-221) - Marks 1
PIC 16F877 devices . . . . . . bit program counter capable of addressing
. . . . . . program memory.
(a) 8, 256K x 8
(b) 16, 64K x 8
(c) 13, 8K x 14
(d) 14, 8K x 13
Answer
(c) 13, 8K x 14
60 / 79

Que - 2
2018 (SLR - TJ-221) - Marks 1
In capture mode which timer is used?
(a) Timer 0
(b) Timer 1
(c) Timer 2
(d) Timer 3
Answer
(b) Timer 1
61 / 79

Que - 3
2018 (SLR - TJ-221) - Marks 1
The PWMM period is specified by
(a) PR2
(b) TMR2
(c) CCPCON
(d) None of the above
Answer
(a) PR2
62 / 79

Que - 4
2018 (SLR - TJ-221) - Marks 1
SPI means
(a) Serial port interface
(b) Serial peripheral inetrafce
(c) Syncronous port interface
(d) Syncronous peripheral interace
Answer
(b) Serial peripheral inetrafce
63 / 79

Que - 5
2018 (SLR - TJ-221) - Marks 1
PSA (Prescale assignment) bit in option regiter equals 1 then
(a) Prescalar is enable
(b) Prescalar is disable
(c) Prescalar assigned to WDT
Answer
(c) Prescalar assigned to WDT
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Que - 6
2017 (SLR-TJ-205, SLR-VB-179) - Marks 1
In compare mode . . . . . . is used
(a) Timer 0
(b) Timer 1
(c) Timer 2
(d) Timer 3
Answer
(b) Timer 1
65 / 79

Que - 7
2017 (SLR - TJ-205) - Marks 1
CCP means
(a) Capture Control Protocol
(b) Capture/Control PWM
(c) Compare Control Protocol
Answer
(b) Capture/Control PWM
66 / 79

Que - 8
2017 (SLR - TJ-205) - Marks 1
The reset vector and interrupt vector for PIC are
(a) 00074, 00044
(b) 00044, 0007
(c) 00h, 07h
(d) 0000h, 0004h
Answer
(d) 0000h, 0004h
67 / 79

Que - 9
2017 (SLR - TJ-205) - Marks 1
FLASH program memory, data memory (RAM) and data memory
(EEPROM) for PIC16F877 are
(a) 8Kx8, 368x8, 256x8
(b) 14Kx8, 14Kx8, 256x8
(c) 8Kx14, 368x16, 256x8
(d) 8Kx14, 368x8, 256x8
Answer
(d) 8Kx14, 368x8, 256x8
68 / 79

Que - 10
2017 (SLR - TJ-205) - Marks 1
The CALL and GOTO instruction provides . . . . . . bits of address to allow
branching within any . . . . . . program memory page.
(a) 13 bit, 8K
(b) 16 bit, 64K
(c) 11 bit, 2K
Answer
(a) 13 bit, 8K
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Que - 11
2017 (SLR - TJ-205) - Marks 1
PIC has . . . . . . bit mulltichannel analog to digital converter
(a) 12
(b) 14
(c) 10
(d) 20
Answer
(a) 13 bit, 8K
70 / 79

Que - 12
2017 (SLR-TJ-205, SLR-VB-179) - Marks 1
Sink and source capability of PIC is
(a) 20 mA
(b) 25 mA
(c) 40 mA
(d) 50 mA
Answer
(b) 25 mA
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Que - 13
2017 (SLR-TJ-205) - Marks 4
Differentiate between Von-Neumann architecture and Harvard architecture
Answer
Explain Von-Neumann architecture and Harvard architecture
72 / 79

Que - 14
2017 (SLR-TJ-205) - Marks 8
List features of PIC and explain PCON, OPTION and STATUS registers of
PIC
Answer
Explain Features and PCON, OPTION and STATUS registers
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Que - 15
2017 (SLR-VB-179) - Marks 1
PIC has power saving . . . . . . mode
(a) Sleep
(b) Standby
(c) Power up
(d) Power Down
Answer
(a) Sleep
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Que - 16
2017 (SLR-VB-179) - Marks 3
Differentiate between CISC and RISC architectures
Answer
Explain CISC and RISC
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Que - 17, 18 and 19
2017 (SLR-VB-179) - Marks 8
Draw and Explain block diagram of PIC 16F877
2017 (SLR-VB-179) - Marks 8
Write a short note on brown out reset and also explain PCON, INTCON
and STATUS registers of PIC
2017 (SLR-VB-179) - Marks 8
Explain with neat diagram program memory and data memory
organization of PIC
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Que - 20, 21, 22 and 23
2016 (SLR-EP-142) - Marks 5
List the features of PIC microcontroller
2016 (SLR-EP-142) - Marks 8
Explain PCON, OPTION and STATUS registers of 16F877 and explain
memory mapping in it
2016 (SLR-EP-142) - Marks 8
Explain the different memories available in PIC 16F877
2016 (SLR-EP-142) - Marks 5
Write a note on watchdog timer
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References
[1, 2, 3, 4]
Muhammad Ali Mazidi, Rolin D. McKinlay, and Danny Causey.
PIC Microcontroller and Embedded Systems - Using Assembly and C
for PIC18.
Pearson International Edition, Upper Saddle River, NJ, 2008.
Martin P. Bates.
Programming 8 - bit PIC Microcontrollers in C with Interactive
Hardware Simulation.
Newnes Press Private Limited, United Kingdom, 2008.
Ajay V. Deshmukh.
Microcontrollers Theory and Applications.
Tata McGraw Hill, New Delhi, India, 2008.
John B. Peatman.
Design with PIC Microcontroller.
Prentice Hall, New Delhi, India, 1997.
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Microcontroller pic 16 f877 registers memory ports

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