The document provides information about the 8086 and 80386 microprocessors. It discusses the 8086's 16-bit architecture and its 14 registers including the accumulator, base, count, and data registers. It also describes the 8086's addressing modes. For the 80386, it discusses its 32-bit architecture with 32-bit general purpose registers and segment registers. It outlines the 80386's register organization, flag register, descriptor registers, addressing modes including scaled indexed mode, control registers, and debug registers.

1. By
MD Nabil Shahriar(110EC0644)
Under Professor S K Patra
Department of electronics & communication Engineering
National Institute of technology Rourkela
Note: This document holds contents from various sources including internet sources & referred text
books. It doesn’t hold any copyright claim.

2. 8086 Microprocessor:
In 1976, when Intel began designing the 8086 processor, which was the first 16 bit
microprocessor. Memory was very expensive. Personal computers at the time, typically
had four thousand bytes of memory. Even when IBM introduced the PC five years later,
64K was still quite a bit of memory; one megabyte was a tremendous amount. Intel’s
designers felt that 64K memory would remain a large amount throughout the lifetime of
the 8086. The only mistake they made was completely underestimating the lifetime of
the8086. They figured it would last about five years, like their earlier 8080 processor.
People were running up against the one megabyte limit
of 8086 . So Intel gave us the 80386 in 1985. This processor could address up to maximum
16 megabytes ofmemory.
Register Organization:
• The 8086 has four groups of the user accessible internal registers. They are
the instruction pointer, four data registers, four pointer and index register,
four segment registers.
• The 8086 has a total of fourteen 16-bit registers including a 16 bit register
called the status register, with 9 of bits implemented for status and control
flags.
• Most of the registers contain data offsets within 64 KB memory segment.
There are four different 64 KB segments for instructions, stack, data and extra
data. To specify where in 1 MB of processor memory these 4 segments are
located the processor uses four segment registers:

3. • Code segment (CS) is a 16-bit register containing address of 64 KB segment
with processor instructions. The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP) register. CS register cannot
be changed directly. The CS register is automatically updated during far jump,
far call and far return instructions.
• Stack segment (SS) is a 16-bit register containing address of 64KB segment
with program stack. By default, the processor assumes that all data referenced
by the stack pointer (SP) and base pointer (BP) registers is located in the stack
segment. SS register can be changed directly using POP instruction.
• Data segment (DS) is a 16-bit register containing address of 64KB segment
with program data. By default, the processor assumes that all data referenced
by general registers (AX, BX, CX, and DX) and index register (SI, DI) is located in
the data segment. DS register can be changed directly using POP and LDS
instructions.
• Extra segment (ES) is a 16-bit register containing address of 64KB segment,
usually with program data. By default, the processor assumes that the DI
register references the ES segment in string manipulation instructions. ES
register can be changed directly using POP and LES instructions.
• It is possible to change default segments used by general and index registers
by prefixing instructions with a CS, SS, DS or ES prefix.
• All general registers of the 8086 microprocessor can be used for arithmetic
and logic operations. The general registers are:
• Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16- bit register AX. AL in this case contains
the low-order byte of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations and string manipulation.
• Base register consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX. BL in this case contains the
low-order byte of the word, and BH contains the high-order byte. BX register
Usually contains a data pointer used for based, based indexed or register
indirect addressing.

4. • Count register consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX. When combined, CL
register contains the low-order byte of the word, and CH contains the high
order byte. Count register can be used in Loop, shift/rotate instructions and as
a counter in string manipulation,.
• Data register consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX. When combined, DL
register contains the low-order byte of the word, and DH contains the high
order byte. Data register can be used as a port number in I/O operations. In
integer 32-bit multiply and divide instruction the DX register contains high
order word of the initial or resulting number.
• The following registers are both general and index registers:
• Stack Pointer (SP) is a 16-bit register pointing to program stack.
• Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP
register is usually used for based, based indexed or register indirect
addressing.
• Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed
and register indirect addressing, as well as a source data address in string
manipulation instructions.
• Destination Index (DI) is a 16-bit register. DI is used for indexed, based
indexed and register indirect addressing, as well as a destination data address
in string manipulation instructions.
Other registers:
• Instruction Pointer (IP) is a 16-bit register.
• Flags is a 16-bit register containing 9 one bit flags.
• Overflow Flag (OF) - set if the result is too large positive number, or is too
small negative number to fit into destination operand.

5. • Direction Flag (DF) - if set then string manipulation instructions will auto-
decrement index registers. If cleared then the index registers will be auto-
incremented.
• Interrupt-enable Flag (IF) - setting this bit enables makeable interrupts.
• Single-step Flag (TF) - if set then single-step interrupt will occur after the
next instruction.
• Sign Flag (SF) - set if the most significant bit of the result is set.
• Zero Flag (ZF) - set if the result is zero.
• Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3
in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of
the result is even.
• Carry Flag (CF) - set if there was a carry from or borrows to the most
significant bit during last result calculation.
Addressing Modes:
• Implied - the data value/data address is implicitly associated with the
instruction.
• Register - references the data in a register or in a register pair.
• Immediate - the data is provided in the instruction.
• Direct - the instruction operand specifies the memory address where data is
located.
• Register indirect - instruction specifies a register containing an address,
where data is located. This addressing mode works with SI, DI, BX and BP
registers.

6. • Based: - 8-bit or 16-bit instruction operand is added to the contents of a base
register (BX or BP), the resulting value is a pointer to location where data
resides.
• Indexed: - 8-bit or 16-bit instruction operand is added to the contents of an
index register (SI or DI), the resulting value is a pointer to location where data
resides.
• Based Indexed: - the contents of a base register (BX or BP) is added to the
contents of an index register (SI or DI), the resulting value is a pointer to
location where data resides.
• Based Indexed with displacement: - 8-bit or 16-bit instruction operand is
added to the contents of a base register (BX or BP) and index register (SI or DI),
the resulting value is a pointer to location where data resides.

7. 80386 Microprocessor:
The Intel 80386, also known as the i386, or just 386, was a 32-
bit microprocessor introduced by Intel in 1985. The first versions had 275,000
transistors and were used as the central processing unit (CPU) of
many workstations and high-end personal computers of the time. As the
original implementation of the 32-bit extension of the 8086 architecture, the
80386 instruction set, programming model, and binary encodings are still
the common denominator for all 32-bit x86 processors
Register Organisation
• The 80386 has eight 32 - bit general purpose registers which may be used as
either 8 bit or 16 bit registers.
• A 32 - bit register known as an extended register, is represented by the
register name with prefix E.
• Example: A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc.
• The 16 bit registers BP, SP; SI and DI in 8086 are now available with their
extended size of 32 bit and are names as EBP, ESP, ESI and EDI.
• AX represents the lower 16 bit of the 32 bit register EAX.

8. • BP, SP, SI, DI represents the lower 16 bit of their 32 bit Counterparts, and can
be used as independent 16 bit registers.
• The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS.
• The CS and SS are the code and the stack segment registers respectively,
while DS, ES, FS, GS are 4 data segment registers.
• A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP.
• Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of
the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always
set at 1.Two extra new flags are added to the 80286 flag to derive the flag
register of 80386. They are VM and RF flags.
• VM - Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086
mode within the protection mode. This is to be set only when the 80386 is in
protected mode. In this mode, if any privileged instruction is executed an
exception 13 is generated. This bit can be set using IRET instruction or any
task switch operation only in the protected mode.
• RF- Resume Flag: This flag is used with the debug register breakpoints. It is
checked at the starting of every instruction cycle and if it is set, any debug fault
is ignored during the instruction cycle. The RF is automatically reset after
Successful execution of every instruction, except for IRET and POPF
instructions.
• Also, it is not automatically cleared after the successful execution of JMP,
CALL and INT instruction causing a task switch. These instructions are used to
set the RF to the value specified by the memory data available at the stack.
• Segment Descriptor Registers: This registers are not available for
programmers, rather they are internally used to store the descriptor
information, like attributes, limit and base addresses of segments.
• The six segment registers have corresponding six 73 bit descriptor registers.
Each of them contains 32 bit base address, 32 bit base limit and 9 bit
attributes. These are automatically loaded when the corresponding segments
are loaded with selectors.

9. • Scaled Indexed Mode: Contents of the index register are multiplied by a
scale factor that may be added further to get the operand offset.
• Control Registers: The 80386 has three 32 bit control registers CR), CR2 and
CR3 to hold global machine status independent of the executed task. Load and
store instructions are available to access these registers.
• System Address Registers: Four special registers are defined to refer to the
descriptor tables supported by 80386.
• The 80386 supports four types of descriptor table, viz. global descriptor table
(GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task
state segment descriptor (TSS).
• Debug and Test Registers: Intel has provided a set of 8 debug registers for
hardware debugging. Out of these eight registers DR0 to DR7, two registers
DR4 and DR5 are Intel reserved.
• The initial four registers DR0 to DR3 store four program controllable
breakpoint addresses, while DR6 and DR7 respectively hold breakpoint status
and breakpoint control information.
• Two more test register are provided by 80386 for page cacheing namely test
control and test status register.
• Addressing Modes:
The 80386 supports overall eleven addressing modes to facilitate efficient
execution of higher level language programs.
• In case of all those modes, the 80386 can now have 32-bit immediate or 32-
bit register operands or displacements.
• The 80386 has a family of scaled modes. In case of scaled modes, any of the
index register values can be multiplied by a valid scale factor to obtain the
displacement.

10. • The valid scale factor are 1, 2, 4 and 8.
• The different scaled modes are as follows.
• Based Scaled Indexed Mode: Contents of the index register are multiplied by
a scale factor and then added to base register to obtain the offset.
• Based Scaled Indexed Mode with Displacement: The Contents of the index
register are multiplied by a scaling factor and the result is added to a base
register and displacement to get the offset of an operand.