The document provides information about the Intel 8086 microprocessor, including its architecture, components, and instruction set. It describes the 16-bit architecture and three-bus system. It explains that the 8086 CPU is divided into the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles address generation and data transfer, while the EU decodes and executes instructions. The document outlines the various registers, addressing modes, and categories of instructions supported by the 8086 architecture.

1. Module 1
Intel 8086 Microprocessor
Architecture Review,
Assembler and Programming
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PADHMAKUMAR PK, M-Tech
Lecturer in Electronics
GPTC Kottayam

2. Intel 8086
• The Intel 8086 is a 16-bit microprocessor
intended to be used as the CPU in a
microcomputer.
• The term “16-bit” means that its arithmetic
logic unit, internal registers, and most of its
instructions are designed to work 16-bit
binary words. It has 16-bit data bus and 20-bit
address bus.

3. 8086 CPU ARCHITECTURE
• The microprocessors functions as the CPU in a digital
computer. Its job is to generate all system timing
signals and synchronize the transfer of data between
memory, I/O, and itself. It accomplishes this task via
the three-bus system architecture (Address, Data and
Control Buses)
• The microprocessor must recognize, decode, and
execute program instructions fetched from the
memory unit. This requires an Arithmetic-Logic Unit
(ALU) within the CPU to perform arithmetic and logical
(AND, OR, NOT, compare, etc) functions.

4. Architecture of 8086

5. • The 8086 CPU is divided into two independent
functional parts, the bus interface unit or BIU,
and the execution unit or EU

6. BIU - The Bus Interface Unit
The BIU provides H/W functions, including
generation of the memory and I/O addresses for
the transfer of data between the outside world -
outside the CPU, that is- and the EU

7. EU- The Execution Unit
• The EU receives program instruction codes
and data from the BIU, executes these
instructions, and store the results in the
general registers. By passing the data back to
the BIU, data can also be stored in a memory
location or written to an output device.
• The EU has no connection to the system
buses. It receives and outputs all its data
through the BIU.

8. The Bus Interface Unit - Blocks
• The BIU handles all data and addresses on the
buses for the execution unit such as it sends out
addresses, fetches instructions from memory,
reads data from ports and memory as well as
writes data to ports and memory. In BIU there are
so many functional groups or parts these are as
follows.
• Instruction Queue
• Segment Registers
• Instruction Pointer (IP)

9. Instruction Queue
• To increase the execution speed, BIU fetches as many
as six instruction bytes ahead to time from memory.
The pre-fetched instruction bytes are held for the EU in
a first in first out group of registers called a instruction
queue.
• When the EU is ready for its next instruction, it simply
reads the instruction from this instruction queue. This
is much faster than sending out an address to the
system memory and to send back the next instruction
byte. Fetching the next instruction while the current
instruction executes is called pipelining.

10. Segment Registers
• The BIU contains four 16-bit segment registers.
• the extra segment (ES) register,
• the code segment (CS) registers,
• the data segment (DS) registers, and
• the stack segment (SS) registers.
• These segment registers are used to hold the
upper 16 bits of the starting address for each of
the segments. The part of a segment starting
address stored in a segment register is often
called the segment base.

11. • 1. Code Segment (CS): The CS register is used
for addressing a memory location in the Code
Segment of the memory, where the
executable program is stored.

12. • 2. Data Segment (DS): The DS contains most
data used by program. Data are accessed in
the Data Segment by an offset address or the
content of other register that holds the offset
address.

13. • 3. Stack Segment (SS): SS defined a section of
memory to store addresses and data while a
subprogram executes.

14. • 4. Extra Segment (ES): ES is additional data
segment that is used by some of the string to
hold the extra destination data.

16. • Instruction Pointer (IP)
• In the BIU, the next register, below the
segment register is instruction pointer. The
instruction pointer (IP) holds the 16-bit
address of the next code byte within this code
segment.

17. The Execution Unit-Blocks
• The execution unit (EU) tells the BIU where to fetch instructions or
data from, decodes instructions, and executes instructions.
• The functional parts of the execution unit are control circuitry or
system, instruction decoder, and Arithmetic logic unit (ALU).
• Control circuitry to perform various internal operations. A decoder
in the EU translates instructions fetched from memory to generate
different internal or external control signals that required
performing the operation. The EU has a 16-bit ALU, which can
perform arithmetic operations such as add, subtract etc. and logical
operations such as AND, OR, XOR, increment, decrement etc
• The various registers in EU are
• Flag Register
• General Purpose Registers
• Stack Pointer Register
• Pointer and Index Registers

18. Flag Register
• A 16-bit flag register is a flip-flop which indicates some
condition produced by the execution of an instruction
or controls certain operations of the EU. They are
modified automatically by CPU after mathematical
operations. It has 9 flags and they are divided into two
categories:
• 1. Conditional Flags
• 2. Control Flags

19. Conditional Flags
• Conditional flags represent result of last arithmetic or logical instructions.
• Carry Flag (CF): This flag will be set to one if the arithmetic operation produces the
carry in MSB position. It is also used in multiple-precision arithmetic.
• Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e.
carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag; it is used
internally by the processor to perform Binary to BCD conversion.
• Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits
of the result contains even number of 1’s, the Parity Flag is set to one and for odd
number of 1’s, the Parity Flag is reset i.e. zero.
• Zero Flag (ZF): It is set to one; if the result of arithmetic or logical operation is zero
else it is reset.
• Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit.
If the result of operation is negative, sign flag is set to one.
• Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.

20. Control Flags
• Control flags are intentionally set or reset to control certain
operations of the processor with specific instructions put in the
program from the user. Control flags are as follows:
• 1. Trap Flag (TP): It is used for single step control. It allows user to
execute one instruction of a program at a time for debugging.
When trap flag is set, program can be run in single step mode.
• 2. Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used
to allow/prohibit the interruption of a program. If it is set, the
maskable interrupt is enabled and if it is reset, the interrupt is
disabled.
• 3. Direction Flag (DF): It is used in string operation. If it is set, string
bytes are accessed from higher memory address to lower memory
address. When it is reset, the string bytes are accessed from lower
memory address to higher memory address.

21. General Purpose Registers
• The EU has eight general purpose registers
labeled AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually for temporary
storage of 8-bit data. The AL register is also called
the accumulator. Certain pairs of these general
purpose registers can be used together to store
16-bit data. The valid register pairs are AH and
AL, BH and BL, CH and CL and DH and DL. These
register pairs is referred to the AX, BX, CX, and DX
resp.

22. • 1. AX Register: For 16-bit operations, AX is called
the accumulator register that stores operands for
arithmetic operations.
• 2. BX Register: This register is mainly used as a
base register. It holds the starting base location of
a memory region within a data segment.
• 3. CX Register: It is defined as a counter. It is
primarily used in loop instruction to store loop
counter.
• 4. DX Register: DX register is used to contain I/O
port address for I/O instruction.

23. Pointer and Index Registers
• 8086 has two pointer registers (Stack Pointer SP,
and Base pointer BP)and two index registers
(Source Index SI, and Destination Index DI).
• Source index (SI) register, base pointer (BP)
registers, and Destination Index (DI) registers can
be mainly used for temporary storage of 16-bit
data just like a general purpose registers.

24. Stack Pointer Register
• The stack pointer (SP) register contains the 16-
bit offset from the start of the segment to the
memory location where a word was most
recently stored on the stack.
• The memory location where a word was most
recently stored is called the top of stack.

25. Physical Memory Generation
• 8086 can support 1MB memory, ranging from 00000h to FFFFFh.
• Even addressed 16 bits can be accessed together and Odd
addressed 16 bits can be accessed in two memory cycles.
• All physical locations are addressed in Segment Base Offset mode
• 20 bit physical address is generated by combining a 16 bit offset
value located in a base register or an index register or a pointer
register, and 16 bit base value from any one of the four segment
registers (DS,CS,ES,SS)
• The source of offset address may be either – BP, BX, SI, DI or IP
depending on the type of memory reference.
• The value of segment register is shifted left by 4bit with LSBs being
filled with 0s, thereafter, the offset value is added to the LSBs of the
shifted contents of the segment register. The resulted contents of
the addition is 20bit physical address.

26. FETCH AND EXECUTE
• Although the 8086 functions as a stored program computer, organization of
the CPU into a separate BIU and EU allows the fetch and execute cycles to
overlap.
1. The BIU outputs the contents of the instruction pointer register (IP) onto
the address bus, causing the selected byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next instruction fetch.
3. Once inside the BIU, the instruction is passed to the queue. This is a first-
in, first-out storage register sometimes likened to a "pipeline".
4. Assuming that the queue is initially empty, the EU immediately draws this
instruction from the queue and begins execution.
5. While the EU is executing this instruction, the BIU proceeds to fetch a
new instruction. Depending on the execution time of the first instruction,
the BIU may fill the queue with several new instructions before the EU is
ready to draw its next instruction.

27. Pipelineing

28. • The BIU is programmed to fetch a new instruction whenever the queue space for additional bytes.
The advantage of this pipelined architecture is that the EU can execute instructions almost
continually instead of having to wait for the BIU to fetch a new instruction.
• There are three conditions that will cause the EU to enter a "wait" mode.
• The first occurs when an instruction requires access to a memory location not in the queue. The
BIU must suspend fetching instructions and output the address of this memory location. After
waiting for the memory access, the EU can resume executing instruction codes from the queue
(and the BIU can resume filling the queue).
• The second condition occurs when the instruction to be executed is a "jump" instruction. In this
case control is to be transferred to a new (nonsequential) address. The queue, however, assumes
that instructions will always be executed in sequence and thus will be holding the "wrong"
instruction codes. The EU must wait while the instruction at the jump address is fetched. Note that
any bytes presently in the queue must be discarded (they are overwritten).
• One other condition can cause the BIU to suspend fetching instructions. This occurs during
execution of instructions that are slow to execute. For example, the instruction AAM (ASCII Adjust
for Multiplication) requires 83 clock cycles to complete. At four cycles per instruction fetch, the
queue will be completely filled during the execution of this single instruction. The BIU will thus
have to wait for the EU to pull over one or two bytes from the queue before resuming the fetch
cycle.
• A subtle advantage to the pipelined architecture should be mentioned. Because the next several
instructions are usually in the queue, the BIU can access memory at a somewhat "leisurely" pace.
This means that slow-mem parts can be used without affecting overall system performance.

29. Addressing Modes of 8086
Whenever any processor executes an instruction, it performs
the specified operation on the data.
An instruction consists of two parts
• OPCODE and
• OPERAND.
• Opcode means operational code, ie code of the operation
to be performed
• Operand means data, on which the operation is to be
performed
The operand reside in one of the internal registers of the
processor, stored in the memory or held at any I/O port.

30. • The method by which the operand/data is addressed in
an instruction is referred to as the Addressing mode, ie
the addressing technique to access various types of
operands
• Register addressing
• Immediate Addressing
• Direct Addressing
• Register indirect addressing
• Register relative Addressing
• Based Indexed Addressing
• Relative Based Indexed Addressing

31. Instruction Types in 8086
• 8086 has 117 basic instructions. The istruction set of 8086
can be divided into the following groups
• Data Transfer Instructions
• Arithmetic Instructions
• Logic Instructions
• Shift Instructions
• Rotate Instructions
• Flag Control Instructions
• Jump instructions
• Subroutine Handling Instructions
• Loop Handling Instructions
• String Handling Instructions

32. Data Transfer Instructions
• This group of instructions includes Move byte or word, Exchange byte or word,
Translate byte, Load data segment, Load effective address and Load extra segment
instructions.
• Move byte or word instructions
MOV D,S
• Exchange byte or word instructions
XCHG D,S
• Translate byte instructions
XLAT (content of AL replaced by contents of the accessed lookup table location)
• Load data segment instructions
LDS (load DS register and other specified register from memory)
• Load effective address instructions
LEA (Load effective address of operand into specified register)
• Load extra segment instructions
LES (Load ES register and other specified register from memory)

33. Arithmetic Instructions
• This group of instructions for addition, subtraction, comparison,
multiplication, and division operations on unsigned or signed binary
bytes or words, unpacked or packed decimal bytes or ASCII
numbers.
• Addition Instructions
ADD D,S ADC D,S INC D AAA DAA
• Subtraction Instructions
SUB D,S SBB D,S DEC D NEG D AAS DAS
• Comparison Instructions
CMP D,S
• Multiplication Instructions
MUL S IMUL S AAM
• Division Instructions
DIV S IDIV S AAD CBW CWD

34. Logic Instructions
• There are four basic operations in this group
AND, OR, XOR and NOT
AND D,S
OR D,S
XOR D,S
NOT D

35. Shift Instructions
• Two basic shift instructions are
Logical Shift and Arithmetic Shift
SHL/SAL/SHR/SAR D, count
There are four possible shift instructions
SHL Shift logical left
SAL Shift Arithmetic Left
SHR Shift Logical Right
SAR Shift Arithmetic Right

36. Rotate Instructions
• There are four rotate instructions
• ROL D, Count (Rotate left by number of bits
positions equal to count)
• ROR D, Count (Rotate right by number of bits
positions equal to count)
• RCL D, Count (Rotate left through carry by
number of bits positions equal to count)
• RCR D, Count (Rotate Right through carry by
number of bits positions equal to count)

37. Flag Control Instructions
• This group of instructs will affect the settings of flags
• LAHF and SAHF are used to read the flags and to
change their status
• STC (set carry flag)
• CLC (clear carry flag)
• CMC (complement carry flag)
• STI (set interrupt flag)
• CLI (clear interrupt flag)
• STD (set direction flag)
• CLD (clear direction flag)

38. Jump instructions
• There are two types of jump instructions
Unconditional jump and Conditional Jump
• Depending upon the length of jump there are
Intrasegment jump and Intersegment jump)

39. Subroutine Handling Instructions
• The subroutine handling instructions are
CALL RET PUSH POP
Call Operand
Ret or Ret operand
Push S
Pop D

40. Loop Handling Instructions
• There are three loop handling instructions
• LOOP
• LOOPE/LOOPZ
• LOOPNE/LOOPNZ

41. String Handling Instructions
• Strings means a series of data words or bytes that
reside in consecutive memory locations. The string
handling instructions are
• Move string byte/word: MOVSB MOVSW
• Compare string CMPSB/CMPSW
• Scan string SCASB/SCASW
• Load string LODSB/LODSW
• Store string STOSB/STOSW

42. Assembler
• Self Assembler
• Cross Assembler

43. Assembler Directives
• Data Definition Directives
• Program Organization Directives
• Alignment Directives
• Program Termination Directives
• Value Returning Attribute Directives
• Procedure Definition Directives
• Macro Definition Directives
• Data control Directive
• Header file inclusion directives
• Branch Displacement Directives

46. Module 2
Interfacing of 8086 with
Peripheral ICs
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Lecturer in Electronics
GPTC Kottayam

47. Basic interrupt processing
• There are three sources of interrupts in 8086
• External signal on NMI Pin
• External signal on INTR Pin
• Execution of instruction INT (Software Interrupt)

48. Major actions during interrupt process
• It decrements the stack pointer by 2 and pushes the flag
register on the stack
• It disables the 8086 INTR interrupt input by clearing the
interrupt flag (IF) in the flag register
• It resets the trap flag (TF) in the flag register
• It decrements the stack pointer by 2 and pushes the current
code segment register contents on the stack
• It decrements the stack pointer again by 2 and pushes the
current instruction pointer contents on the stack
• It does an indirect far jump to the start of the procedure
corresponds to the interrupt

49. Interrupt Response
Push Flags
Clear IF
Clear TF
PUSH CS
PUSH IP
Fetch ISR Address
POP IP
POP CS
POP Flags
Main Program ISS
Push Registers
POP Registers
IRET

50. Interrupt Vector Table
(Interrupt Pointer Table)
Type 0 Pointer
Divide error
Type 1 Pointer
Single Step
Type 2 Pointer
Non- Maskable
Type 3 Pointer
1 Byte INT Instruction
Type 4Pointer
Overflow
Type 5 Pointer
Reserved
Type 31 Pointer
Reserved
Type 32 Pointer
Available
Type 255 Pointer
Available
Dedicated
Interrupts
Pointers (5)
Reserved
Interrupts
Pointers (27)
Available
Interrupts
Pointers (224)
000H
008H
16 Bits
004H
00CH
010H
014H
07FH
080H
3FFH
CS Base Address
IP Offset

51. 8086 Interrupt Types
• Divide by Zero Interrupt (Type 0)
• Single Step Interrupt (Type 1)
• Non- Maskable Interrupt (Type2)
• Breakpoint Interrupt (Type 3)
• Overflow Interrupt (Type 4)
• Software Interrupts (Type 0 to Type 255)
• INTR Interrupts (Type 0 to Type 255)

52. Divide by Zero Interrupt (Type 0)
• If the result of a DIV operation or IDIV
operation is too large to fit in the destination
register
• For a type 0 interrupt, the 8086 pushes the
flag register on stack, reset IF and TF, and
pushes the return address

53. Single Step Interrupt (Type 1)

54. Non- Maskable Interrupt (Type2)

55. Breakpoint Interrupt (Type 3)

56. Overflow Interrupt (Type 4)

57. Software Interrupts
(Type 0 to Type 255)

58. INTR Interrupts
(Type 0 to Type 255)

59. Priority of 8086 Interrupts
• Divide Error, INT n, INTO
• NMI
• INTR
• Single Step

60. 8259 Priority Interrupt Controller

61. 8279
Programmable Keyboard and Display Interface

62. Matrix Keyboard

63. Matrix Keyboard

64. Matrix Keyboard Key press detection Algorithm

65. Multiplexed Dynamic Display

66. • We can interface a keyboard and dynamic display to a
microprocessor using its ports. The disadvantages of
this method of interfacing keyboard and display with
8086 is that the processor has to refresh the display and
check the status of the keyboard periodically using
polling technique. Thus a considerable amount of CPU
time is wasted, reducing the system operating speed.
• Intel’s 8279 is a general purpose keyboard display
controller that simultaneously drives the display of a
system and interfaces a keyboard with the CPU, leaving
it free for its routine task

67. 8279
• Hardware to interface a matrix keyboard and Multiplexed display
• Advantages is that it relieves the processor from checking keyboard
and refreshing the display
• Disadvantage is its cost
• 40 pin IC with two major segments – Keyboard and Display
• Keyboard segments can be connected to a 64 contact key matrix.
• Keyboard entries are debounced and stored in the internal FIFO
memory, an interrupt is generated with each entry.
• Display segment can provide a 16 character scanned display interface
• Display segment has 16 x 8 R/W memory, used to read/write for
display purpose.
• Display can be either right entry or left entry format.
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68. Signal description

69. Block Diagram of 8279
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70. Keyboard Section
• This section has eight lines (RL0-RL7), can be connected to eight
columns of a keyboard, plus two additional lines; Shift and
CNTL/STB (Control/Strobe). The status of Shift Key and Control
Key can be stored along with a key closure.
• Keys are automatically debounced, and the keyboard can operate in
two modes: Two Key Lockout and N-Key rollover
• In Two Key Lockout, if two keys are pressed simultaneously, only
first key is recognized
• In N-key rollover, simultaneous keys are recognized and their codes
are stored in the internal buffer.
• Keyboard section include a 8x8 FIFO RAM, can store 8 keyboard
entries.
• The status logic keeps track of the number of entries and provides an
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71. Scan Section
• This section has a scan counter and four scan lines (SL0-SL3)
• These four scan lines can be decoded using a 4 to 16 decoder to
generate 16-lines for scanning
• These lines can be connected to the rows of a matrix keyboard and
digit drivers for the multiplexed display.
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72. Display Section
• This section has eight output lines divided into two groups A0-A3
and B0-B3.
• These lines can be used, either as a group of eight lines or as two
groups of four, in conjunction with the scan lines for the multiplexed
display.
• Display can be blanked using BD line.
• This section include 16x8 display RAM, MPU can read from or write
into any of these registers.
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73. MPU Interface Section
• This section include eight bidirectional data lines (DB0-DB7), One
Interrupt Request Line (IRQ), and Six lines for interfacing , including
the buffer address line (A0)
• When A0 is high, signals are interpreted as control words or status.
• When A0 is low, signals are interpreted as data.
• The IRQ line goes high whenever data entries are stored in the FIFO.
This signal is used to interrupt the MPU to indicate the availability of
data
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74. Interfacing 8279 With a MPU
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75. Interfacing 8279 with a MPU
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76. DMA – Direct Memory Access
• Direct Memory Access (DMA)allows devices to transfer data without
subjecting the processor a heavy overhead. Otherwise, the processor
would have to copy each piece of data from the source to the
destination. This is typically slower than copying normal blocks of
memory since access to I/O devices over a peripheral bus is generally
slower than normal system RAM.
• During this time the process or would be unavailable for any other
tasks involving processor bus access. But it can continue to work on
any work which does not require bus access.
• DMA transfers are essential for high performance embedded systems
where large chunks of data need to be transferred from the
input/output devices to or from the primary memory.
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77. DMA Controller
• A DMA controller is a device, usually peripheral to a CPU that is
programmed to perform a sequence of data transfers on behalf of the
CPU. A DMA controller can directly access memory and is used to
transfer data from one memory location to another, or from an I/O
device to memory and vice versa.
• A DMA controller manages several DMA channels, each of which
can be programmed to perform a sequence of these DMA transfers.
Devices, usually I/O peripherals, that acquire data that must be read
(or devices that must output data and be written to) signal the DMA
controller to perform a DMA transfer by asserting a hardware DMA
request (DRQ) signal. A DMA request signal for each channel is
routed to the DMA controller. This signal is monitored and responded
to in much the same way that a processor handles interrupts.
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78. • When the DMA controller sees a DMA request, it responds by
performing one or many data transfers from that I/O device into
system memory or vice versa.
• Channels must be enabled by the processor for the DMA controller to
respond to DMA requests.
• The number of transfers performed, transfer modes used, and
memory locations accessed depends on how the DMA channel is
programmed.
• A DMA controller typically shares the system memory and I/O bus
with the CPU and has both bus master and slave capability.
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79. 8237 DMA Controller
• The 8237A Multimode Direct Memory Access (DMA) Controller is a
peripheral interface circuit for microprocessor systems. It is designed to
improve system performance by allowing external devices to directly
transfer information from the system memory. Memory-to-memory transfer
capability is also provided.
• The 8237A offers a wide variety of programmable control features to
enhance data throughput and system optimization and to allow dynamic
reconfiguration under program control.
• The 8237A is designed to be used in conjunction with an external 8-bit
address latch. It contains four independent channels and may be expanded
to any number of channels by cascading additional controller chips.
• The three basic transfer modes allow programmability of the types of DMA
service by the user. Each channel can be individually programmed to Auto
initialize to its original condition following an End of Process (EOP). Each
channel has a full 64K address and word count capability.

80. 8237 Block Diagram
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81. Interfacing 8237 with a MPU
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82. DMA Execution
The process of data transfer from the peripheral to the system memory
under DMA controller can be classified into two modes :
• The Slave Mode and
• Master Mode
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83. Slave Mode
• In bus slave mode, the DMA controller is accessed by the CPU,
which programs the DMA controller's internal registers to setup
DMA transfers. The internal registers consist of source and
destination address registers and transfer count registers for each
DMA channel, as well as control and status registers for initiating,
monitoring, and sustaining the operation of the DMA controller.
Steps:
• The MPU Selects the DMA controller through Chip Select
• The MPU Writes the command mode and terminal count in channel
registers by accessing through A0 – A3 and through control signals
IOR and IOW
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84. Master Mode
In bus master mode, the DMA controller acquires the system bus (address, data, and
control lines) from the CPU to perform the DMA transfers. Because the CPU releases
the system bus for the duration of the transfer, the process is sometimes referred to as
cycle stealing.
Steps:
• After the initialization, the 8237 in master mode keeps checking for a DMA request
• When peripheral is ready for data transfer, it sends a high signal to DRQ
• When DRQ has been received and the channels are enabled, the control logic sets
HRQ(Hold request) high
• In the next cycle, MPU relinquishes the buses and sends HLDA (Hold acknowledge)
to 8237
• After receiving HLDA, control logic sends DACK(DMAAcknowledge) the
acknowledgement to the peripheral
• Meanwhile 8237 enables AEN(Address Enable). AEN disables the MUP de-
multiplexed address bus A7 – A0. The entire A7 – A0 of the 8237 becomes output.
• The low order byte of the memory location is placed on the A7 – A0 of the 8237
• When AEN is high, ADSTB(Address Strobe) signal goes high and places the high
order byte of the memory location, on address bus A15-A8.
• Data transfer continues until the count reaches zero.
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85. MODULE - III
80286, 80386 and 80486

86. Features of 80286
• Multi user, multi tasking high performance processor in 1983
• Memory protection and memory management capabilities
• 68 pin PLCC, LCC and PGA packages
• 24 bit address lines
• 16 MB physical memory and 1GB virtual memory
• Two operating modes, Real address mode (RAM) and
Protected Virtual Address Mode (PVAM)
• 6 times faster than 8086
• It has four processing units – Bus unit (BU), Instruction unit
(IU), Address unit (AU), and Execution unit (EU)
• Separate address and data buses

87. Architecture of 80286

89. Processing Units in 80286
• Bus Unit (BU)
• Instruction Unit (IU)
• Execution unit (EU)
• Address Unit (AU)

90. Operating Modes of 80286
• The Real Address Mode (RAM)
• The Protected Virtual Address Mode (PVAM)

91. Features of 80386
• First 32 bit processor in 1985
• 32 bit data bus and registers
• 132 pin PGA package
• +5 v single supply
• 32 bit non pipelined address and data bus
• 4GB physical memory and 64 TB virtual memory
• Uses CHMOS – III technology
• Down compatible with 8086 and 80286
• 129 basic instructions
• Multi tasking, multi user system with memory management
• It has 6 functional units – Bus interface unit (BIU), Execution
Unit (EU), Segment unit (SU), Paging unit (PU), Instruction
decode unit (IDU), and Code Prefetch Unit (CPU).
• Available in 80386 SX, 80386 DX and 80386 SL versions

93. Functional units of 80386
• Bus Interface Unit
• Instruction pre fetch unit (code Prefetch unit)
• Instruction pre-decode unit
• Segmentation unit
• Paging unit
• Execution Unit

94. Operating modes of 80386
• Real Address Mode
• Protected Virtual Address Mode
• Virtual 8086 Mode

95. MODULE - IV
PENTIUM PROESSORS

96. Pentium Processor-features

97. Pentium microprocessors
• A 32-bit microprocessor introduced by Intel in 1993.
• It contains 3.3 million transistors, nearly triple the
number contained in its predecessor, the 80486 chip.
• The Pentium processor has been superseded by the
Pentium Pro and Pentium II microprocessors.
• Since 1993, Intel has developed the Pentium III and
more recently the Pentium 4 microprocessors.

98. • Intel builds on the technology it developed with the
Pentium II microprocessors.
• The Pentium III processor comes with a Synchronized
Dynamic Random Access Memory (SDRAM), allowing for
an extremely fast transfer of data between the
microprocessor and the memory.
• 70 new instructions, called Streaming SIMD Extensions,
enhance multimedia and 3D performance.
• An advanced transfer cache and system buffering are able
to meet higher data bandwidth requirements.
Pentium microprocessors – P-III

99. • Launched February 1999 - Available in speed levels
of 450, 500, 550, and 600MHz
• .25 Micron Manufacturing Process
• 32KB of Level 1 Cache (operating at CPU's full core
speed)
• 512KB of Level 2 Cache (operating at ½ of CPU's
core speed)
• 100 MHz front-side bus speed
• MMX support
• The branch prediction/recovery pipeline was
doubled to include 10-stages from the P-II.
Pentium microprocessors – P-III

100. • The next generation of microprocessors from Intel.
• Pentium 4 is the product of a serious redesign.
• The move from Pentium II to Pentium III added two
million transistors.
• The Pentium 4 sports a whopping 42 million - 14
million more than the currently available Pentium III
Coppermine processors. (Actually, 55 million for
redundancy/reliability.)
Pentium microprocessors – P-4

101. • The Pentium 4 is significantly larger than its predecessor.
• The P4 was first etched using the same .18-micron,
aluminum trace process as the P-III Coppermine.
• The current P4 etching is the .13-micron process
• Now that the Pentium 4 is upon us the pipeline depth has
been doubled once again to 20 stages - NetBurst
microarchitecture .
• By doubling the depth of the branch prediction pipe, the
penalty associated with mis-predictions is greatly
increased.
• This results in a lower average number of instructions
successfully executed per clock cycle.
Pentium microprocessors – P-4

102. • To compensate for the lower IPC, Intel has
implemented:
– Execution Trace Cache
– Dynamic Execution Engine
• A 32-bit microprocessor, hyper-pipelined technology,
a rapid execution engine and a quad-pumped
100MHz-system bus, delivering the equivalent of
3.2GB/s of bandwidth- three times the bandwidth of
the Pentium III
• It transfers data at the equivalent of 400MHz bus
speed
Pentium microprocessors – P-4

103. Superscalar Architecture
• Superscalar processing is the ability to initiate multiple
instructions during the same clock cycle.
• A typical Superscalar processor fetches and decodes the incoming
instruction stream several instructions at a time.
• Superscalar architecture exploit the potential of ILP(Instruction
Level Parallelism). The outcomes of conditional branch
instructions are usually predicted in advance to ensure
uninterrupted stream of instructions
• Instructions are initiated for execution in parallel based on the
availability of operand data, rather than their original program
sequence. This is referred to as dynamic instruction scheduling.
• Upon completion instruction results are re-sequenced in the
original order.

104. Super scalar execution

105. Hardware Organization of a superscalar processor

106. Pentium Pro
• L1 cache: 8, 8 KiB (data, instructions)
• L2 cache: 256, 512 KiB (one die) or 1024 KiB (two
512 KiB dies) in a multi-chip module clocked at CPU-
speed
• Socket: Socket 8
• Front side bus: 60 and 66 MHz
• VCore: 3.1–3.3 V
• Fabrication: 0.50 µm or 0.35 BiCMOS
• Clock rate: 150, 166, 180, 200 MHz, (capable of 233
MHz on some motherboards)
• First release: November 1995

107. Pentium Pro Architecture

108. Hyper-Threading Technology
• Intel® Hyper-Threading Technology (Intel® HT
Technology)1 uses processor resources more efficiently,
enabling multiple threads to run on each core. As a
performance feature, it also increases processor
throughput, improving overall performance on
threaded software.
• Intel HT Technology is available on the Intel® Core™
processor family, the Intel® Core™ M processor family,
and the Intel® Xeon® processor family. By combining
one of these Intel® processors and chipsets with an
operating system and BIOS supporting Intel HT
Technology.

109. Features of HT
• Hyper-Threading Technology is a form of simultaneous
multithreading technology introduced by Intel.
• Architecturally, a processor with Hyper-Threading
Technology consists of two logical processors per core,
each of which has its own processor architectural state.
Each logical processor can be individually halted,
interrupted or directed to execute a specified thread,
independently from the other logical processor sharing
the same physical core
• Run demanding applications simultaneously while
maintaining system responsiveness
• Keep systems protected, efficient, and manageable
while minimizing impact on productivity

111. Multi-core technology
• Multi-core is the term used to describe two or more CPUs
working together on the same chip.
• It is a type of architecture where a single physical processor
contains the core logic of two or more processors.
• These processors are packaged into a single integrated
circuit (IC). These single integrated circuits are called a die.
• Multi-core can also refer to multiple dies packaged together.
• Multi-core technology can be used in desktops, mobile PCs,
servers and workstations.

112. Architecture of Multi core processor

113. Comparison of Pentium Pro, P-II, P-III