1. Function of segment register and flag register.
Segment registers hold the segment address of various items. They are only
available in 16 values. They can only be set by a general register or special
instructions. Some of them are critical for the good execution of the program and
you might want to consider playing with them when you'll be ready for multisegment programming
: Holds the Code segment in which your program runs.
Changing its value might make the computer hang.
: Holds the Data segment that your program accesses.
Changing its value might give erronous data.
: These are extra segment registers available for
far pointer addressing like video memory and such.
: Holds the Stack segment your program uses.
Sometimes has the same value as DS.
Changing its value can give unpredictable results,
mostly data related.
carry flag (CF)- indicates a carry after addition or a borrow after subtraction, also
indicates error conditions.
parity flag (PF)- is a logic “0” for odd parity and a logic “1” for even parity.
auxiliary carry flag (AF)- important for BCD addition and subtraction; holds a carry
(borrow) after addition (subtraction) between bits position 3 and 4. Only used for DAA
and DAS instructions to adjust the value of AL after a BCD addition (subtraction).
zero flag (ZF)- indicates that the result of an arithmetic or logic operation is zero.
sign flag (SF)- indicates arithmetic sign of the result after an arithmetic operation.
overflow flag (OF)- a condition that occurs when signed numbers are added or
subtracted. An overflow indicates that the result has exceeded the capacity of the
* trap flag (TF) - used for single stepping through a program;
* interrupt flag (IF) - used to allow or prohibit the interruption of a program;
* direction flag (DF) - used with string instructions.
Difference between procedures and Macros
S- 71 page
3.Difference 8085 and 8086
4.Program convert lowercase to uppercase
6. Describe the difference between the instructions MOV AX, 2437H and
MOV AX, [2437H]
MOV AX, 2437H moves the 16 bit number 2437H into accumulator.
MOV AX, [2437H] moves the 16 bit number present in the memory location whose
address is represented by the offset 2437H
7. 8259A programmable interrupt controller
Short for direct memory access, a technique for transferring data from main memory to a
device without passing it through the CPU. Computers that have DMA channels can transfer
data to and from devices much more quickly than computers without a DMA channel can.
This is useful for making quick backups and for real-time applications.
Some expansion boards, such as CD-ROM cards, are capable of accessing the computer's
DMA channel. When you install the board, you must specify which DMA channel is to be
RISC processor [ R educed I nstruction S et C omputer], computer arithmetic-logic unit that
uses a minimal instruction set, emphasizing the instructions used most often and optimizing
them for the fastest possible execution. Software for RISC processors must handle more
operations than traditional CISC [ C omplex I nstruction S et C omputer] processors, but RISC
processors have advantages in applications that benefit from faster instruction execution,
such as engineering and graphics workstations and parallel-processing systems. They are
also less costly to design, test, and manufacture. In the mid-1990s RISC processors began to
be used in personal computers instead of the CISC processors that had been used since the
introduction of the microprocessor.
9.Interernal structure of 8086
8086 has two blocks BIU and EU. Bus Interface Unit and Execution unit. Dividing the works
between them speeds up the processing.
The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
EU decode and executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the system
bus and system performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address adde
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
Decodes instructions fetched by the BIU
Generate control signals,
10. Difference between RISC and CISC processor