A 3-bit synchronous down counter uses 3 negative edge triggered T flip-flops connected in series to count from 7 to 0 on each clock pulse. The T input of the first flip-flop is 1, while the T inputs of the second and third flip-flops are connected to the inverted outputs of the previous flip-flops. All flip-flops change state synchronously on the negative edge of the clock signal, allowing the counter to decrement in unison on each clock cycle.

1. 3 BIT SYNCHRONOUS
DOWN COUNTER
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Presented by: Rabin BK
BSc.CSIT 2nd Semester

2. Introduction to Counter
3 bit synchronous down counter
References
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3. A sequential circuit that goes through a prescribed sequence of states
upon the application of input pulses
• Input pulses may originate from external sources and occur at defined
interval or at random
Counter is found in almost all the digital logic for counting the number
of occurrences of an event
Useful for generating timing sequences to control operations in digital
system
An n bit binary counter counts from 0 to 2n-1or vice-versa and consists
of n flip-flops
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Introduction to Counter

4. All the flip-flops receive the same clock signal, so it is called
as Synchronous counter
Since it counts from 23-1 = 7 to 0, it is called down counter
Consists of 3 T flip-flops and one 2-input AND gate
All the flip-flops are negative edge triggered and the outputs
of flip-flops change (affect) synchronously
The T inputs of first, second and third flip-flops are
1, 𝑄0
′
, 𝑄0
′
. 𝑄1
′
respectively
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3 bit synchronous down counter
T flip-flops

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6. References
Books reference
• Digital Logic and Computer Design, M. Morris Mano
Web reference:
• https://www.tutorialspoint.com/digital_circuits/digital_circuits_counters
.htm
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7. Queries
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