During the CXL Forum at OCP Summit, Arm Director of Segment Marketing Parag Beeraka provides and overview of the Arm portfolio of CXL products for the Data Center
2. Enabling CXL devices within the Data
Center with Arm Solutions
Parag Beeraka, Senior Director of Segment Marketing, Arm
3. Arm product portfolio for the Data Center
CPU Interconnect and System Reference Designs
• V Series
• N Series
• E Series
• Scalable Coherent Mesh Fabric
(CMN)
• NI NoC Network on-chip non-
coherent fabric
• GIC
• MMU
• V1 Reference Design
• N2 Reference Design
4. Arm is enabling Rapid Pace of Innovation with
CXL E-series
Efficient Throughput
N-series
Efficient Performance
V-series
Maximum Performance and Optimal TCO
Performance Performance per watt Throughput efficiency
2020
2023+
2019
2019
V1
Platform
DDR5, PCIe g5
CMN
V1
V2
Platform
DDR5, PCIe g5,
CXL 2.0
CMN
V2
Poseidon
Platform
CMN
V ...
DDR5, PCIe g6,
CXL 3.0
N1
Platform
DDR4, PCIe g4
CMN
N1
N2
Platform
CMN
N2
DDR5, PCIe g5,
CXL 2.0
DDR4, PCIe g4
CMN
E1
Platform
E1
N-series
Next
CMN
N-Next
DDR5, PCIe g6,
CXL 3.0 CMN
E2
Platform
Cortex-A510
DDR5, PCIe g5,
CXL 2.0
DDR5, PCIe g6,
CXL 3.0
CMN
E-series
Next
E-Next
2023+
2023+
Arm Neoverse CPUs along with CMN Interconnect enable CXL
2022
5. Disaggregation of Compute and Memory in Data
Center
• Inefficiency of DRAM memory
utilization
• Memory channel bandwidth and
capacity per core declining
• Reduce Total Cost of Ownership
(TCO)
• Workloads becoming more and
more divergent
Problem Statement Solutions with CXL
CXL Memory Expansion CXL Memory Pooling
CXL memory pooling
controller
CXL memory expansion cards
in the rack and separate racks
CXL
CPU
DPU
CPU
DPU
6. CXL Memory Pooling Solution Proposal
Arm is in a unique position to provide
CXL memory pooling solution
o Lowest latency Coherent Mesh
Network (CMN) product based on
collaboration with hyperscalers
o Arm CPUs for Fabric and SoC
management
o Provide end-end CXL optimized
solutions with Host and Device side
knowledge
CXL memory
pooling
controller
CPU
Arm
CMN
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
D
D
R
P
H
Y
E
P
CXL
Arm CPU
for fabric
mgmt
Arm CPU
for SoC
mgmt
CXL
CXL
CXL
DPU
Host
Device
4-8 CXL
Inputs &
8 DDR
controllers
with
CXL
8. Enabling CXL support in Arm CMN portfolio
CXL/CCIX Gateway (CCG)
• Upper Link Layer for CXL.mem and
CXL.cache
• CCIX-SMP Socket - Socket
• CXL/CXS Flit formation
• Link & Protocol Credits
CMN-Kampos
Interconnect
CHI.e
CXL ARB/
MUX
PCIe
FlexBus
PHY
PCIe-Gen5 x16
FlexBus
CCIX 2.0 or CXL Host/Device
External Interface
3rd
Party CXL & PCIe IP
CXL.io & PCIe
Data Link Layer
CXL.io
& PCIe
Transaction
Layer
RN-D
HN-I
DTI
MMU-
Woolf
(Host only)
CHI.e
CCG
CXL / CCIX
Upper Link Layer
- CXL Flit formation
- Packing and Un-Packing
- Link Credit Manager
CXL / CCIX
Lower Link Layer
- CRC handling (generate/
check)
- Link Layer Control
- Link layer Retry Handling
512b
CXL.cache & CXL.mem
& CCIX 2.0 Link Layer
MMU
Ongoing Interoperability
with a few 3rd party CXL
IP and PHYs
9. Arm works with 3rd party vendors on CXL
Interoperability
CMN-Host
Arm
Neoverse
CPU Cluster
GIC SCP
Memory
Controller
C1
Memory
Controller
C0
Host
CHIP-0
CMN-Device
SCP
Memory
Controller
C1
Memory
Controller
C0
Device
CHIP-1
3rd
Party
CXL3.0
Controller
3rd
Party
CXL3.0
Controller
10. Arm can provide memory pooling with Hardware
Coherency
Controller
CPU
DPU
Host
CPU
DPU
Host
CPU
DPU
Host …
CXL Link w/
BISnp Channel
CXL Link w/
BISnp Channel
CXL Link w/
BISnp Channel
CXL Link w/
BISnp Channel
Arm CMN
Interconnect with
Snoop Filters
D
D
R
D
D
R
D
D
R
D
D
R
D
D
R
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Arm CPU
for fabric
mgmt
Arm CPU
for SoC
mgmt
Arm CXL
Gateway
(CCG)
Shared
Memory
Region
(HDM-DB)
Pooled
Memory
Region
Memory Pooling Controller
Arm CXL
Gateway
(CCG)
CXL Link w/
BISnp Channel
Arm CXL
Gateway
(CCG)
CXL Link w/
BISnp Channel
11. CXL Device side support in CMN portfolio
Product: CMN
Availability Released Released
CXL Version CXL 1.1 CXL 2.0
Bifurcation - Yes
Max System Level
Cache(SLC)/Node
4MB 4MB
SLD Yes Yes
Reset - Yes
P2P / UIO - Yes
Features planned for future CMN releases
• Security - IDE
• MemSpecRd
• Telemetry
• Multi-host (MH-SLD)
• DSA Mode – reduced latency/area for non-coherent use-
cases
• Pooled memory (MH-SLD with DCD)
• Extended metadata
• Multiple logical devices ( MH-MLD, SH-MLD)
• Memory Sharing via HDM-DB (Back Invalidation)
12. Arm is Driving Technology Leadership Across
Standards
AMBA CHI, UCIe and CXL deliver leadership die-to-die and chip-to-chip fabric solutions
Arm AMBA
CHI
Compute
Cluster
13. AMBA CHI CTC extends Arm Architecture to
Multichip
Single interface to enable capabilities and diverse solutions
AMBA CHI: Protocol for Arm architecture aware solutions
Transport: Standard (UCIe/CXL/PCIe) or 3rd Party (NVLINK)
arm
Neoverse
A
A
A M
A Accelerator
M Memory
• A unified interface for handling:
• Compute, Device and Memory device
attach
• Coherent and IO Coherent accelerator
traffic
• Architectural features extended across
chip(let)
• Virtualization (DVM), Interrupts, Timers
• Telemetry and Resource Management
(MPAM)
• Security for trust, memory protection and
Arm Confidential Compute
• Localized managed memory
• Composable with die re-use across
different solutions
14. • Call to Action
• Please bring your ideas, feedback to Composable Memory Systems (CMS) -
OCP Subproject
• Summary
• Arm can provide a solution for CXL Memory pooling solution with
Arm’s interconnect and CPU product portfolio
• Arm has also invested in doing interoperability with ecosystem to
further expedite the solution development
Call to Action and Summary
