This guide covers the deployment of Aruba remote access points (RAP) in fixed telecommuter and micro branch office sites, and it is considered part of the base designs guides within the VRD core technologies series. This guide covers the design recommendations for remote network deployment and it explains the various configurations needed to implement a secure, high-performance virtual branch office (VBN) solution with Aruba RAPs.
The Aruba Mobility Access Switch family of products provides various features including voice VLAN, Link Layer Discovery Protocol – Media Endpoint Discovery (LLDP-MED), and Quality of Service (QoS) to enable successful deployment of VoIP in enterprise networks. This application note addresses traditional techniques and introduces new device-aware support to deploy VoIP phones. This document is intended for all system engineers and network administrators who are deploying a VoIP solution in an enterprise network.
To learn more, visit us at http://www.arubanetworks.com/wlan. Join the discussion at https://community.arubanetworks.com
This guide covers Aruba Mobility Controllers and is considered part of the foundation guides within the VRD core technologies series. This guide will help you understand the capabilities and options you have when deploying an Aruba Mobility Controller. This guide describes operating modes for the mobility controller, licensing, forwarding modes, logical and physical deployment, redundancy, and how to select the appropriate mobility controller based on scalability requirements. Version 9 includes information on the 7200 series controller.
This webinar will cover how to bring up Aruba Mobility Master, Managed Device & Access Point and also go through some basic troubleshooting commands.Check out the webinar recording where this presentation was used: http://community.arubanetworks.com/t5/Wireless-Access/Technical-Webinar-Recording-Slides-Bringing-up-Aruba-Mobility/td-p/307599
Register for the upcoming webinars: https://community.arubanetworks.com/t5/Training-Certification-Career/EMEA-Airheads-Webinars-Jul-Dec-2017/td-p/271908
This guide covers the deployment of Aruba remote access points (RAP) in fixed telecommuter and micro branch office sites, and it is considered part of the base designs guides within the VRD core technologies series. This guide covers the design recommendations for remote network deployment and it explains the various configurations needed to implement a secure, high-performance virtual branch office (VBN) solution with Aruba RAPs.
The Aruba Mobility Access Switch family of products provides various features including voice VLAN, Link Layer Discovery Protocol – Media Endpoint Discovery (LLDP-MED), and Quality of Service (QoS) to enable successful deployment of VoIP in enterprise networks. This application note addresses traditional techniques and introduces new device-aware support to deploy VoIP phones. This document is intended for all system engineers and network administrators who are deploying a VoIP solution in an enterprise network.
To learn more, visit us at http://www.arubanetworks.com/wlan. Join the discussion at https://community.arubanetworks.com
This guide covers Aruba Mobility Controllers and is considered part of the foundation guides within the VRD core technologies series. This guide will help you understand the capabilities and options you have when deploying an Aruba Mobility Controller. This guide describes operating modes for the mobility controller, licensing, forwarding modes, logical and physical deployment, redundancy, and how to select the appropriate mobility controller based on scalability requirements. Version 9 includes information on the 7200 series controller.
This webinar will cover how to bring up Aruba Mobility Master, Managed Device & Access Point and also go through some basic troubleshooting commands.Check out the webinar recording where this presentation was used: http://community.arubanetworks.com/t5/Wireless-Access/Technical-Webinar-Recording-Slides-Bringing-up-Aruba-Mobility/td-p/307599
Register for the upcoming webinars: https://community.arubanetworks.com/t5/Training-Certification-Career/EMEA-Airheads-Webinars-Jul-Dec-2017/td-p/271908
Technical Overview of Cisco Catalyst 9200 Series SwitchesRobb Boyd
TechWiseTV's Cisco Container Platform live workshop took place on July 18th.
For the first time in the industry, a single family of fixed, stackable, and modular switches are running on the same IOS-XE operating system along with a common ASIC.
Cisco’s Catalyst 9200 rounds out the lower end of its incredible Catalyst 9000 family of switches. The 9200 is designed for small, medium, and branch deployments, providing greater modularity, redundancy, and stackability than the Catalyst 2960 it replaces.
Register now.
Watch the replay: http://cs.co/90028sLgC
We’re going to make this as simple as Cisco’s new Software-Defined Access makes building and managing more secure enterprise networks:
Do you want to streamline device provisioning and host onboarding? Automate policy and segmentation? Get performance insights you didn’t think possible? Of course you do.
Register for the workshop today to get performance insights you didn’t think possible.
Resources:
Watch the New Era of Networking playlist: http://cs.co/90058sI1U
Join us at this session to hear about the challenges you might face as you try to support a large group of mobile users and devices for 802.1x authentication. While username & password authentication (eg. 802.1x PEAP) is easily deployed, requiring each device to authenticate with its own unique credential (eg. certificate-based 802.1x EAP-TLS) is a much secure implementation. Join us as we discuss ways to identify the most appropriate 802.1x authentication mechanisms for variety of environments and user profiles.
To learn more, visit us at http://www.arubanetworks.com/wlan. Join the discussion at https://community.arubanetworks.com
Cisco® Application Centric Infrastructure (ACI) is an innovative architecture that radically simplifies, optimizes, and accelerates the entire application deployment lifecycle. Cloud, mobility, and big data applications are causing a shift in the data center model. Cisco ACI redefines the power of IT, enabling IT to be more responsive to changing business and application needs, enhancing agility, and adding business value. Cisco ACI delivers a transformational operating model for next-generation data center and cloud applications. This Cisco ACI hands lab will step you through from the ACI Fabric concepts to deployment. • Cisco ACI Overview • ACI Fabric Discovery • ACI Building Basic Network Constructs • ACI Building Policy Filters and Contracts • : Deploying a 3-Tier Application Network Profile • ACI Integrating with VMware • Deploying a Service Graph with Application Network Profile • Exploring Monitoring and Troubleshooting
AWS storage solutions are designed to deliver secure, scalable, and durable storage for businesses looking to achieve efficiency and scalability within their backup & recovery environments, without the need for an on-premises infrastructure. In this session, you will learn how to deliver lower costs and greater scale with nearly seamless integration into your existing backup & recovery processes to achieve fast, simple wins that demonstrate the scale and flexibility of cloud services for storage. Presented by CommVault & Dow Jones.
MIPI DevCon 2016: How MIPI Debug Specifications Help Me to Develop System SWMIPI Alliance
In this presentation, Norbert Schulz of Intel Corporation will discuss good system debug practices and different MIPI standards for creating state-of-the-art software debug solutions. Many software designers still arbitrarily insert text messages into their code to find errors in the same way as their predecessors did 40 years ago. With the Narrow Interface for Debug and Test (MIPI NIDnT), System Trace Protocol (MIPI STP) and System SW-Trace (SyS-T), a user can analyze IoT, automotive or mobile device software behavior in an easy, low-invasive manner through debug or functional ports, such as a USB Type-C™ connector.
Heterogeneous Computing : The Future of SystemsAnand Haridass
Charts from NITK-IBM Computer Systems Research Group (NCSRG)
- Dennard Scaling,Moore's Law, OpenPOWER, Storage Class Memory, FPGA, GPU, CAPI, OpenCAPI, nVidia nvlink, Google Microsoft Heterogeneous system usage
How to Select Hardware for Internet of Things Systems?Hannes Tschofenig
With the increasing commercial interest in Internet of Things (IoT) the question about a reasonable hardware configuration surfaces again and again.
Peter Aldworth, a hardware engineer with more than 19 years of experience, discusses this topic in a presentation given to the IETF community.
Technical Overview of Cisco Catalyst 9200 Series SwitchesRobb Boyd
TechWiseTV's Cisco Container Platform live workshop took place on July 18th.
For the first time in the industry, a single family of fixed, stackable, and modular switches are running on the same IOS-XE operating system along with a common ASIC.
Cisco’s Catalyst 9200 rounds out the lower end of its incredible Catalyst 9000 family of switches. The 9200 is designed for small, medium, and branch deployments, providing greater modularity, redundancy, and stackability than the Catalyst 2960 it replaces.
Register now.
Watch the replay: http://cs.co/90028sLgC
We’re going to make this as simple as Cisco’s new Software-Defined Access makes building and managing more secure enterprise networks:
Do you want to streamline device provisioning and host onboarding? Automate policy and segmentation? Get performance insights you didn’t think possible? Of course you do.
Register for the workshop today to get performance insights you didn’t think possible.
Resources:
Watch the New Era of Networking playlist: http://cs.co/90058sI1U
Join us at this session to hear about the challenges you might face as you try to support a large group of mobile users and devices for 802.1x authentication. While username & password authentication (eg. 802.1x PEAP) is easily deployed, requiring each device to authenticate with its own unique credential (eg. certificate-based 802.1x EAP-TLS) is a much secure implementation. Join us as we discuss ways to identify the most appropriate 802.1x authentication mechanisms for variety of environments and user profiles.
To learn more, visit us at http://www.arubanetworks.com/wlan. Join the discussion at https://community.arubanetworks.com
Cisco® Application Centric Infrastructure (ACI) is an innovative architecture that radically simplifies, optimizes, and accelerates the entire application deployment lifecycle. Cloud, mobility, and big data applications are causing a shift in the data center model. Cisco ACI redefines the power of IT, enabling IT to be more responsive to changing business and application needs, enhancing agility, and adding business value. Cisco ACI delivers a transformational operating model for next-generation data center and cloud applications. This Cisco ACI hands lab will step you through from the ACI Fabric concepts to deployment. • Cisco ACI Overview • ACI Fabric Discovery • ACI Building Basic Network Constructs • ACI Building Policy Filters and Contracts • : Deploying a 3-Tier Application Network Profile • ACI Integrating with VMware • Deploying a Service Graph with Application Network Profile • Exploring Monitoring and Troubleshooting
AWS storage solutions are designed to deliver secure, scalable, and durable storage for businesses looking to achieve efficiency and scalability within their backup & recovery environments, without the need for an on-premises infrastructure. In this session, you will learn how to deliver lower costs and greater scale with nearly seamless integration into your existing backup & recovery processes to achieve fast, simple wins that demonstrate the scale and flexibility of cloud services for storage. Presented by CommVault & Dow Jones.
MIPI DevCon 2016: How MIPI Debug Specifications Help Me to Develop System SWMIPI Alliance
In this presentation, Norbert Schulz of Intel Corporation will discuss good system debug practices and different MIPI standards for creating state-of-the-art software debug solutions. Many software designers still arbitrarily insert text messages into their code to find errors in the same way as their predecessors did 40 years ago. With the Narrow Interface for Debug and Test (MIPI NIDnT), System Trace Protocol (MIPI STP) and System SW-Trace (SyS-T), a user can analyze IoT, automotive or mobile device software behavior in an easy, low-invasive manner through debug or functional ports, such as a USB Type-C™ connector.
Heterogeneous Computing : The Future of SystemsAnand Haridass
Charts from NITK-IBM Computer Systems Research Group (NCSRG)
- Dennard Scaling,Moore's Law, OpenPOWER, Storage Class Memory, FPGA, GPU, CAPI, OpenCAPI, nVidia nvlink, Google Microsoft Heterogeneous system usage
How to Select Hardware for Internet of Things Systems?Hannes Tschofenig
With the increasing commercial interest in Internet of Things (IoT) the question about a reasonable hardware configuration surfaces again and again.
Peter Aldworth, a hardware engineer with more than 19 years of experience, discusses this topic in a presentation given to the IETF community.
Evaluating UCIe based multi-die SoC to meet timing and power Deepak Shankar
Multi-die designs allow systems engineering to pack more functionality with different timing and power constraints into a single package. Older generation multi-die split the dies into high-speed and low speed. Newer, high-performance multi-die System-on-Chip (SoC) requires interaction between memories across the die-to-die interfaces. Connections between dies must be power efficient, have low latency, provide high bandwidth to transfer massive amounts of data, and deliver error-free operation. The distribution of cores, deep neural networks and AI engines across these dies makes it extremely hard to predict the expected end-to-end latency, power spikes and effective bandwidth. Moreover, Multi-die architectures have evolved from proprietary to industry standard UCIe.
This Webinar looks at the system-wide view of performance and power in a multi-die SOC. We will be showcasing a few use cases that combines various types of processing engines across PCIe and interconnected UCIe. This modeling effort will present the user with different system performance and system architecture models and a guide on how to best bring different aspects of their design together in a holistic way that is optimized for power, timing and functionality.
During the Webinar, users can follow along using VisualSim Cloud. To get started with VisualSim Cloud, users can register and receive a login at https://www.mirabilisdesign.com/visualsim-cloud-login/. Once you receive the login, follow the instructions, and open the models provided in the Template pull-down. More instructions will be provided at the start of the Webinar.
The Ultimate Guide to HBM2E Implementation & Selection - Frank Ferro - Rambus...Rambus
In this presentation we'll be discussing HBM2 and 2E memory technology. There's a lot of decisions that need to be made when you're developing high speed products for AI, and HBM has become the memory of choice. So we're going to go into detail and talk about the selection criteria and implementation details for HBM2E memory.
Knowing what's inside and how it works will help you design, develop, and implement applications better, faster, cheaper, more efficient, and easier to use because you will be able to make informed decisions instead of guestimating and assuming.
VEDLIoT Cognitive IoT Hardware Platform. René Griessl. Workshop on Deep Learning for IoT (DL4IoT), co-located with HiPEAC 2022, Budapest, Hungary, June 2022
Not all networks are created equal. Brocade Ethernet Fabrics, as joined in the IBM Flex EN4023 embedded switch, revolutionizes by automating and optimizing your network, enabling you to reduce total cost of ownership, not just capital expenses. Lab tests have validated the Opex and Capex advantages of VCS Ethernet Fabrics over traditional networking. Learn how customers have reduced network infrastructure requirements by 25% and increases the networks performance by up to 30%. See how Dynamic Ports on Demand can save hardware costs. Learn the dramatic Operational impact VCS Fabric switches have on decreasing time to deploy the network by 79% and decreasing the time to implement network changes by 85%.
Learn about the IBM RackSwitch G8264CS which simplifies deployment with its innovative IBM Omni Port technology. For more information on IBM Systems, visit http://ibm.co/RKEeMO.
Visit the official Scribd Channel of IBM India Smarter Computing at http://bit.ly/VwO86R to get access to more documents.
From cars, to thermostats, through media players and embedded controllers, devices are being connected to the Internet at a furious pace. This session will discuss and demonstrate and coding practices from live Azure customers.
Hyper Transport technology is a very fast, low latency, point-to-point link used for inter-connecting integrated circuits on board. Hyper Transport, previously codenamed as Lightning Data Transport (LDT), provides the bandwidth and flexibility critical for today's networking and computing platforms while retaining the fundamental programming model of PCI. Hyper Transport was invented by AMD and perfected with the help of several partners throughout the industry.
PCIe Gen 3.0 Presentation @ 4th FPGA CampFPGA Central
PCIe Gen3 presentation by PLDA at 4th FPGA Camp in Santa Clara, CA. For more details visit http://www.fpgacentral.com/fpgacamp or http://www.fpgacentral.com
Similar to AMC & VPX Form Factor Boards With High Speed SERDES: Embedded World 2010 (20)
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
Discussion of solutions for SDI to PCIe that enables up to 4 bi-directional channels of 1080p Video. Including an examination of applications, challenges and benefits associated with implementing PCIe-based systems, and a discussion of a video framework that simplifies hardware design for video systems with a PCIe-based design.
Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.
Altera is now shipping our Cyclone® IV FPGAs, the market's lowest cost, lowest power FPGAs, with an integrated 3.125-Gbps transceiver variant. Learn how to meet increasing bandwidth requirements while lowering costs in high-volume applications in this presentation. http://www.altera.com/b/cyclone-iv-fpga-shipping.html
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
2. AMC & VPX form factor boards
with high speed SERDES
Burkhard Jour
BittWare
bjour@bittware.com
3. Agenda
• SerDes technology and protocols
• New board form factors supporing SerDes
switch fabrics
• BittWare COTS FPGA boards
• BittWare ANTLANTiS FrameWork for FPGA
application development
These are 60 slides.
I will not go into details with each slide.
Let me know what you are interested in !
5. Embedded COTS Market - Form Factors
• COTS board technology is in a state of upheaval
Historically based on parallel buses: VME and PCI flavors (cPCI, PMC, PCI,
PC/104).
Tweaks/patches/upgrades were made over the years to improve performance and
ensure backward compatibility - but have reached their technical limits.
VME, cPCI, PCI, PMC, PC/104 boards are considered legacy products.
• New products are leveraging high-speed serial and switch fabric
interconnects
Allow communication between boards at a speed that earlier could only have been
achieved between components on the same board
Offer multiple independent communication path instead of the single bus
bottleneck
Replace fault-prone proprietary front panel interconnect cables that had to be used
for high-speed communication with old systems
Offer massive bandwidth potential for the future
But: Use multiple GHz signals and thus cannot use the old connectors
• New COTS form factor standards are required – and already here
Completely new connectors and backplanes, therefore completely new form
factors
The two clear winners of the new high speed serial formats are already there
Both are based on SerDes based backplane communication
But there is more to consider ...
6. High-Speed Serial Board Formats
Both major competing Standards Organizations have
successfully introduced their high-speed serial board
form factors:
• PICMG (PCI Industrial Computer Manufacturers Group)
Advanced TeleCommunications Architecture (ATCA)
Advanced Mezzinine Cards (AdvancedMC or AMC)
MicroTCA (AMCs interconnected via a backplane)
• VITA (formerly VME Industry Trade Association)
VPX (VITA46/48/65 – purely high-speed connectors)
VXS (VITA41– old VME plus one additional SerDes connector)
Define the mechanical specification & the SerDes
Physical Layer of the signal interfaces –
but allow choice in the protocol used.
7. High-Speed Serial Interconnects
• Physical Layer (PHY) – generally interoperable
SerDes blocks (Serializer/Deserializer, pronounced sir-dees) convert data
between parallel data and serial interfaces, and back again.
Uses low-voltage differential signaling.
Encoding/decoding (e.g. 8B/10B or 64/66B encoding) provides in-band
clock transmission, framing, and DC balance.
The SerDes PHY itself is unidirectional, requiring only 1 pair (2 wires) per
direction
Most protocols, however, require bidirectional communication (4 wires, 2
each way)
Common clock rates (GHz) are 1.25, 2.5, 3.125, 5.0, 6.25, 8.25, 10.0, 11.3
Single (1x) ‘lanes’ can be grouped (bonded) into ‘fat-pipes’ of 2x, 4x, 8x,…
• Higher Layers – many incompatible ‘flavors’
Data Link Layer (Buffer management, virtual lane management, error
control, link training, flow control, QoS, routing, read/writes, packetizing, …)
Transaction Layer (API - Application Programming Interface)
8. Many High-Speed Serial Protocols
• Choose the best fit for your application …
Point-to-Point
- SerialLite
- Aurora
Switched Fabrics
- Ethernet
○ GigE, 10GigE (XAUI)
○ Widely used, but significant protocol overhead and latency
- Serial RapidIO (sRIO)
○ Distributed memory architecture, high bandwidth and low latency
- PCIexpress
○ Same API as PCI thus easy upgrade, high bandwidth but latency
• ... But: Most products only support one protocol!
• Altera Stratix GX based boards support all of them!
Altera Stratix GX FPGAs feature multiple SerDes interfaces
Protocol defined in FPGA logic
All major protocols available as IP components, or already built-in
9. ATCA, AMC and uTCA
• A series of complementary specifications for a
wide range of applications
From large computer centers to small embedded
systems
PICMG 3.x, AMC.x and mTCA.x
• Support for reliability, maintenance & system
level (shelf) management
• All High-Speed Serial Interconnects
10. ATCA: Large Systems
Large 8U boards (322mm x 280mm), targeted at carrier-
grade telecommunications infrastructure applications
Developed as a follow-on to CompactPCI
AMCs
ATCA Carrier
11. AdvancedMC (AMC): Small Modules
Dimensions are 74mm x 183.5mm for single-width
Multiple size for board spacing & component heights
Started as a mezzanine card for AdvancedTCA, but has
grown far beyond with emergence of MicroTCA
Has become a very popular board format, with many
functions and vendors
BittWare’s S4AM AMC board featuring the Stratix IV GX
12. MicroTCA: The Embedded And Industrial Way
Up to twelve AMC modules can be put in a rack with a
backplane instead.
Many different rack sizes, optimized for different
application needs
BittWare’s RapidTCA
Developers System MicroTCA racks
From NAT and Elma
13. VPX (VITA 46/48/65)
• Developed by the VME community
• Targeted at Military/Defense applications
Support for Rugged/Conduction-cooled environments
• VPX retains VME’s existing 6U and 3U form factors
• Supports existing PMC & XMC mezzanines (PMC with
high-speed serial fabric interconnect)
• Maintaining some possible compatibility with VMEbus
(“Old” VME enclosures can be used with a new
backplane).
14. AMC Versus VPX
• Overall, AMC boards & 3U VPX boards are often
architecturally & physically similar
• Advantages of VPX
VPX was designed for rugged environments & conduction
cooling
VPX allows for significantly higher power consumption – provided
you can get all that heat away
3U & 6U formats
• Advantages of AMC
Support hot swapping & Intelligent Platform Management Intf. (IPMI)
More standard host interface & system-level switching
Tends to be less expensive
Compact, Mid-size, and Full-size spacing
• Porting an application between AMC and VPX is much
easier than it was between CPCI and VME
You can use the same switch fabrics between boards
15. COTS (Commercial Off-The-Shelf) Advantages
• Besides of developing your application, you already
have to decide
Form factor selection
Switch fabric selection
• There is more to an FPGA board than just the FPGA
Maintaining signal integrity at higher and higher speeds
Managing onboard power supplies
Thermal/cooling in harsh environments and extended temperatures
Standard Host interfacing
- Booting
- Run-time Command & Control
Tested interface to on-board resources
- Memory
- SerDes
Application Integration
- What would you think about a comprehensive toolset, a FrameWork,
for easier, faster, more reliable FPGA application development?
• So: Don‘t DIY (Do It Yourself), use COTS
16. BittWare: Supplying COTS High-End Signal
Processing Board For More Than 20 Years
• Headquartered in Concord, NH, USA
• Worldwide local sales representatives
• Hardware: High-end COTS FPGA Boards
Well Architected, Executed, & Polished
Full Environmental Verification & Validation (V&V)
Proven & Stable Reduced Risk
• Built in support for “Soft” Products and Ease-of-Use
FINe™: Host Command & Control
ATLANTiS™ FrameWork (AFW): FPGA Development
BittWorks: Host & Embedded Software Development
• Top Quality Supplier
High Quality Manufacturing
High Reliability
Trustworthy & dependable
18. BittWare Hardware – Board Families
• GX-AMC: Altera 2SGX FPGA + FP Modules
• GT Family: Altera 2SGX FPGAs + TS201 DSPs
• S4 Family: Altera 4SGX FPGA + FP Modules
• VITA 57 Front-panel Mezzanine Cards (FMC)
• Accessories & Rapid Development Platform
19. GXAM – Stratix II GX AMC
• Altera® Stratix® II GX (2SGX90/130) FPGA for I/O, routing, & processing
Up to 19 SerDes used for edge interfacing, switch fabrics, etc.
Connected to all AMC ports and clocks, except port 0
Two banks of DDR2 SDRAM (up to 512 MBytes each)
• ATLANTiS FrameWork
Fully validated board-level PHYs for I/O, communications, & memory
Dataflow interconnect fabric allowing modules to be easily connected
A control fabric that allows modules to be easily coordinated & controlled
• Up to 1 GB of on-board DDR2 SDRAM
• BittWare’s FINe bridge for control plane
Port 0 GigE, front panel10/100 Ethernet, & RS-232
Booting of FPGAs via 64 MB Flash
NIOS II running uC-Linux
Completely abstracts host control
• Front panel I/O
10/100 Ethernet, RS-232, JTAG port for debug support
4x SERDES supporting: Serial RapidIO™, PCI Express™, GigE, and (10 GigE)
• BittWare Front-panel Module (FM) for processing & I/O expansion
• Mid-size, single wide AMC (Advanced Mezzanine Card)
Common Options region:
- Port 0 GigE on FINe; Ports 1 ,2 & 3 connect to FPGA
Fat Pipes region has eight ports to FPGA: ports 4-11 configurable to support:
- Serial RapidIO™, PCI Express™, GigE, & XAUI™ (10 GigE)
Full support of IPMI & AMC system clocks (all connected)
21. BittWare’s GT Board Family: Stratix II GX + DSPs
• Hybrid Signal Processing Boards (Altera Stratix II GX & TigerSHARC)
multiprocessing boards for high performance applications
• Altera Stratix II GX FPGA
90K or 130K logic elements (LE)
High speed SerDes transceivers
• ATLANTiS™ FrameWork
Fully validated board-level PHYs for I/O, communications, & memory
Dataflow interconnect fabric allowing ATLANTiS modules to be easily connected
A control fabric that allows modules to be easily coordinated & controlled
• Clusters of 2 or 4 ADSP-TS201S DSPs @ 500MHz
Up to 48 GOPS 16-bit fixed point; 12 GFLOPS floating point processing power
• FINe Host/Control bridge
Implements complete control plane w/ extensive SW support via BittWorks Tools
Greatly simplifies development of data plane I/O & processing in FPGA
• Up to 3 GBytes of DDR2 SDRAM & up to 128 MBytes of QDR
• PMC+ expansion site (GTV6)
• Air cooled and Ruggedized/conduction cooled
• COTS compliant boards with full life cycle management
GT3U: 3U cPCI slot-card (4 DSPs)
GTV6: 6U VME-VXS (2 clusters, 4 DSPs)
GT3X: 3U VPX (4 DSPs)
22. GT Architecture Block Diagram
Memory Module
1GB of DDR2 or
64MB of QDR
32 LVDS pairs -or- 64 Single-Ended DIO
12
SerDes 64
RS232/422
ATLANTiS Interface
Stratix II GX 2 Xcvrs
2SGX90/130
GigE
SharcFINe
TigerSHARC LinkPorts
Bridge
Local PCI 32 bit33
Local PCI (32-bit,33MHz
66MHz)
TigerSHARC TigerSHARC
TS-201 TS-201
64-bit, 100 MHz
#0 #1 Flash
(64 MB)
64- bit, 83.3 MHz
TigerSHARC TigerSHARC
TS-201 TS-201
#2 #3
23. GT3U Features – 3U cPCI
• Altera® Stratix® II GX 90/130 FPGA for I/O, routing, & processing
• One cluster of four ADSP-TS201S TigerSHARC® DSPs
- 48 GOPS 16-bit fixed point, 12 GFLOPS floating point processing power
- Four link ports per DSP
- Two link ports to FPGA; two link ports to other DSPs
- 24 Mbits of on-chip RAM per DSP; Static superscalar architecture
• ATLANTiS FrameWork
- 4 GB/s of simultaneous external input and output
- Eight link ports @ up to 500 MB/s routed from the on-board DSPs
- 36 LVDS pairs (72 pins) comprised of 16 inputs and 20 outputs
- Four channels of high-speed SerDes transceivers
• BittWare Memory Module
- Up to 1 GB of on-board DDR2 SDRAM or 64 MB of QDR SDRAM
• BittWare’s FINe Host/Control bridge
- 32-bit/66 MHz PCI
- 10/100 ethernet
- Two UARTs, software configurable as RS232 or RS422
• 64 MB of flash memory for booting of DSPs and FPGA
• 3U CompactPCI form factor – Air or Conduction Cooled
• Complete software support
24. GTV6 Features – 6U VXS
• Two Altera® Stratix® II GX 90/130 FPGAs for I/O, routing, & processing
• Two clusters of two ADSP-TS201S TigerSHARC® DSPs
- 48 GOPS 16-bit fixed point, 12 GFLOPS floating point processing
- Four link ports per DSP
- Two link ports to FPGA; two link ports to other DSPs
- 24 Mbits of on-chip RAM per DSP; Static superscalar architecture
• ATLANTiS FrameWork
- 4 GB/s of simultaneous external input and output
- Eight link ports @ up to 500 MB/s routed from the on-board DSPs
- 36 LVDS pairs (72 pins) comprised of 16 inputs and 20 outputs
- Four channels of high-speed SerDes transceivers
• Up to 3 GB of DDR2 SDRAM; up to 128 MB of QDR SDRAM
• BittWare’s FINe Host/Control bridge
- 32-bit/66 MHz PCI
- 10/100 ethernet
- Two UARTs, software configurable as RS232 or RS422
• PrPMC site w/ support for BittWare’s PMC+ I/O modules
• 128 MB of flash memory for booting of DSPs & FPGA
• 6U VITA41 form factor – Air or Conduction Cooled
• Complete software support
25. GT3X Features
• 3U VPX form factor
• Altera® Stratix® II GX FPGA supported by BittWare's
ATLANTiS™ FrameWork
19 full-duplex SerDes transceivers
Up to 132,540 equivalent Les
252 embedded 18x18 multipliers and 63 DSP blocks
6.7 Mbits of RAM
IP available for: Serial RapidIO™, PCI Express™, GigE, XAUI™ (10
GigE), CPRI, and OBSAI
• One cluster of four ADSP-TS201S TigerSHARC® DSPs
57.5 GOPS 16-bit fixed point, 14.4 GFLOPS floating point processing
power
• ATLANTiS™ FrameWork
Eight link ports @ up to 1 GByte/s each routed from the on-board
DSPs
32 LVDS pairs comprised of 16 inputs and 16 outputs to P2
15 channels of high-speed SerDes transceivers to P1
• BittWare’s FINe™ bridge chip
10/100 ethernet on front, GigE to rear panel
Two UARTs
• Up to 2 GByte on-board DDR2 SDRAM
• Board Booting via 64 Mbytes Flash nonvolatile memory
26. BittWare’s S4 Board Family
• Stratix IV GX boards w/ expansion mezzanine sites for ultra-high performance
signal processing applications
• Altera Stratix IV GX FPGA – State-of-the-art
230K to 530K logic elements (LE)
High speed SerDes transceivers
• ATLANTiS™ FrameWork
Fully validated board-level interfaces for I/O, communications, and memory
Internal dataflow interconnect fabric that allows the ATLANTiS modules to be easily connected
A control fabric that allows them to be easily coordinated and controlled
• FINe control bridge facilitates separate control & data planes
Greatly simplifies development of data plane I/O & processing
Extensive SW support via BittWorks Tools
• Up to 4 GByte of onboard DDR3 SDRAM & 36 MBytes QDR SDRAM
• VITA-57 Front-panel Mezzanine Card (FMC) for processing & I/O expansion
S4AM: S4GX AMC Card
S43X: S4GX 3U VPX Card
S46X: S4GX 6U VPX Card
27. S4AM Features – AMC
• Altera® Stratix® IV GX (4SGX230/530) FPGA for I/O, routing, & processing
Up to 23 SerDes (up to 10 GHz) used for edge interfacing, switch fabrics, etc.
Connected to all AMC ports and clocks, except port 0
Two banks of DDR3 SDRAM (up to 1 GBytes each)
Two banks of QDR2 SRAM (up to 9 MBytes
• ATLANTiS FrameWork
Fully validated board-level PHYs for I/O, communications, & memory
Dataflow interconnect fabric allowing modules to be easily connected
A control fabric that allows modules to be easily coordinated & controlled
• Up to 2 GB of on-board DDR3 SDRAM & 18 MB of QDR SDRAM
• BittWare’s FINe bridge for control plane
Port 0 GigE, front panel10/100 Ethernet, & RS-232
Booting of FPGAs via 64 MB Flash
NIOS II running uC-Linux
Completely abstracts host control
• Front panel I/O
10/100 Ethernet, RS-232, JTAG port for debug support
4x SERDES supporting: Serial RapidIO™, PCI Express™, GigE, and (10 GigE)
• VITA-57 Front-panel Mezzanine Card (FMC) for processing & I/O expansion
• Mid-size, single wide AMC (Advanced Mezzanine Card)
Common Options region:
- Port 0 GigE on FINe; Ports 1 ,2 & 3 connect to FPGA
Fat Pipes region has twelve (12) ports to FPGA: ports 4-11 & 17-20 to support:
- Serial RapidIO™, PCI Express™, GigE, & XAUI™ (10 GigE)
Full support of IPMI & AMC system clocks (all connected)
28. S4AM Block Diagram – AMC
AMC Temperature AMC
Front Panel Monitoring Edge Conn.
(B+)
10/100b PRELIMINARY FLASH
MMC IPMI
Ethernet
(AtMega16)
JTAG
GigE (Bx)
Header FINe 0
Bridge 1
RS-232 2
3
Sys. Clks
VITA-57/FMC Module Control Data Serdes
Port Port 4-7
(optional) DDR3 SDRAM 4x
(up to 1 GB)
32 8-11
FMC I/O 4x
DDR3 SDRAM FPGA
Connectors (up to 1 GB) 32
QDR2+ SRAM
Stratix IV GX 18
(up to 9 MB)
(4SGX230/530) 18
Clocks, I2C, JTAG, Reset QDR2+ SRAM
18 (up to 9 MB)
Supported by: 18
60 LVDS pairs
ATLANTiS Framework 12-15
4XSerDes 4x 8 LVDS pairs (4I/4O)
Connector
(not w/ 4x 17-20
4x
FMC)
4x
LEDs
switch
PRELIMINARY
29. S43X Features – 3U VPX
• Altera® Stratix® IV GX (4SGX230/530) FPGA for I/O & processing
Up to 27 SerDes (up to 10 GHz) used for edge interfacing, switch fabrics, etc.
Four banks of DDR3 SDRAM (up to 1 GBytes each)
• ATLANTiS FrameWork
Fully validated board-level PHYs for I/O, communications, & memory
Dataflow interconnect fabric allowing modules to be easily connected
A control fabric that allows modules to be easily coordinated & controlled Available
Available
• Up to 4 GB of on-board DDR3 SDRAM (4: 32-bit banks)
• BittWare’s FINe bridge for control plane Q2 2010
Q2 2010
Front or rear panel Ethernet, & RS-232
Booting of FPGAs via 64 MB Flash
NIOS II running uC-Linux
Completely abstracts host control
• Front panel I/O
10/100 Ethernet, RS-232, JTAG port for debug support
4x SERDES supporting: Serial RapidIO™, PCI Express™, GigE, and (10 GigE)
• Rear panel I/O
10/100 Ethernet, RS-232, JTAG port for debug support
15 SERDES to Stratix IV GX: Serial RapidIO™, PCI Express™, GigE, and (10 GigE)
32 LVDS pairs: 16Tx and 16 Rx
• VITA-57 Front-panel Mezzanine Card (FMC) for processing & I/O expansion
8 SERDES
60 LVDS
• Rugged 3U VITA46/48 form factor – Air or Conduction Cooled
• Complete software support
30. S43X Block Diagram – 3U VPX
FLASH PO
JTAG
Header
FINe
Bridge GigE
VITA-57/FMC Module
(optional) RS-232
(sRIO, PCIexp, 10GigE)
FMC I/O P1
Connectors Control Data
Port Port 4x
Serdes
(air-cooled
only) DDR3 SDRAM
(up to 1 GB) 4x
32
(can be DDR3 SDRAM 4x
whole width (up to 1 GB) 32
FPGA
of VPX Front Stratix IV GX DDR3 SDRAM
Panel) 32 (up to 1 GB)
(4SGX230/530)
Clocks, I2C, JTAG, Reset DDR3 SDRAM
Supported by: 32 (up to 1 GB)
60 LVDS pairs
ATLANTiS Framework
4x
Serdes
4XSerDes P2
Connector 32 LVDS pairs
4x
(optional)
4x
LEDs
31. VITA57 Front Panel Modules
• ANSI/VITA57.1-2008
Developed by VITA/VSO; approved July 2008
Intended for use on VME, VPX, cPCI, & AMC (Mid-size)
Air-cooled & Conduction-cooled variants
• Also called FPGA Mezzanine Card (FMC)
Original intent was for I/O customization
Can also be used for processing/memory expansion
• Wide variety of I/O using 400-ball High-speed
Connector
Up to 80 Diff.Pairs at up to 2 Gbps, or 160 SE Signals
Up to 10X SerDes (4x + 4x + 2:1X) at up to 10 Gbps
Reference Clocks
JTAG, I2C, & IPMI
Low pin-count option also supported
• Sophisticated Power Supply support
32. VITA57 Mechanical Overview (Air-Cooled)
Samtec SeaRay 400-ball
High-speed connector
PMC-like Bezel
C B
5 7P
V ITA
33. S4-AMC with VITA57: Standard Mechanicals
• Mid-size AMC
• Front panel handle, etc… omitted for clarity
34. VITA 57 Front-panel Mezzanine Card (FMC)
• Provides Processing and/or I/O expansion for S4 carriers
• S4 carriers are VITA-57 Compliant
Approved ANSI standard
Open format with full documentation and layouts
- Customers & 3rd Parties can build their own
8x SerDes; 60 LVDS; Clocks, I2C, Reset, etc…
Optional I/O out the front panel (non-rugged)
• S4 carrier also supports BittWare mechanical mods to VITA-57 spec
Provides more real-estate and better thermals
Can not be field installed – factory install only
SPFM: SFP/SFP+
B1FM: Four channel ADC (140 MSPS, 16-bit)
D1FM: Single channel ADC (2.5 GHz 10-bit)
S4FM: Stratix IV GX FPGA
T2FM: Dual TigerSHARC (TS201)
35. SPFM: SFP/SFP+ I/O FMC
• 4 SFP/SFP+ Cages
Plug-in your own XCVR
FiberOptic or Copper
• Up to 3.125 GHz each
Will be faster in future
• CPLD support for control & signaling
Error flags
Link Status
Speed control
Start/stop
• Requires
additional SFP Cage
slot height
SFP Finger
36. B1FM: BitSim ADC FMC
• 4 Channel, 130MS/sec, 16-bit
ADC
High-speed A/D module FMC
(VITA-57)
Air-cooled VITA-57 FPGA
Mezzanine Card
External clock input with on-
board clock distribution
Temperature supervision
Available
Available
Q2 2010
Q2 2010
37. D1FM: Delphi ADC FMC
• High Performance A/D
FMC (VITA 57)
1 channel, 2.5 Gsps, 10-
bit ADC
5 GHz input bandwidth
External clock and trigger
inputs
Available
Available
Q3 2010
Q3 2010
38. MicroTCA Rapid Development Platform
• MicroBlade MicroBox 1U chassis
providing 6 mid-size (3 full size) AMC
slots
2 hot-swappable cooling units with 100+
CFM of airflow
300W AC power supply
• Up to 6 BittWare FPGA-based
AdvancedMCs
•
•
BittWorks Develoment Tools
NATview Easy MCH software • Switchless system provides
• MicroTCA carrier hub module (NAT custom backplane to allow direct
MCH Base 12) for central
management and data switching
connection of all AMC boards in
• Optional Concurrent Technologies chassis
processor AMC module
1.86 GHz Core2 Duo processor • Switched system provides
Up to 8 GB DRAM, USB NAND Flash
Optional hard disk and graphics AMC standard backplane supporting
• Optional NAT switch fabric modules switch fabrics such as PCI
for Serial RapidIO, PCI Express, and
10 GigE Express, 10 GigE, and Serial
• Optional SSC Clock module with PCIe RapidIO
clock functionality
• Optional telecom clock module
41. FINe III Host/Control Bridge (S4 Family)
Ethernet
PHY
Ethernet
AM MAC
R
SS
AM r
85 R oll e
/4 SS ntr
32 Y o
S2 P H C
R
T
AR
U
2
R er
D ll
D tro
on
C
2
R
D
D
Flag/Int
MUX
42. FINe III Features (S4 Family)
Host/Control Bridge for ATLANTiS FrameWork FPGA
Boots FPGA from FLASH or Host (via ethernet)
10/100/1000 (GigE) MAC/PHY
- SSRAM packet buffer
Separate Control and Data ports to FPGA
- Memory Mapped Avalon Control Port
- Streaming Avalon Data Port
Dual UARTs with support for RS422/232, I2C, …
Access FPGA mapped memory from Ethernet
Nios II control processor
- Running uClinux & BittWorks
Dual DMA engines to improve data movement performance
Programmable interrupt and flag multiplexer
Extensive SW support via BittWorks Toolkit (HIL) & BWIO
Reference design and IP license available
Implements complete control plane interface
Greatly simplifies development of data plane I/O & processing
Seamlessly integrates with ATLANTiS FrameWork (AFW)
- Can be used without AFW if desired
45. What is ATLANTiS FrameWork (AFW)?
ATLANTiS FrameWork (AFW) integrates:
- Validated reconfigurable HDL components
- Productivity enhancement resources
- Software libraries
to aid customers in developing FPGA based applications utilizing
BittWare’s boards.
ATLANTiS FrameWork helps customers reduce
development costs by providing a proven infrastructure
that supports the development of FPGA based
applications at a higher level of abstraction!
• Customers don’t have to start development with a blank FPGA
• Allows users to focus on unique IP development, rather than having
to ‘re-invent the wheel’ for the low-level
46. FPGA Limitations
• Development is costly!
Complexity
Time to market
Expensive code changes
Tools
• NOT microprocessors
No peripheral infrastructure (must build everything)
Lacks common API
Minimal libraries
No standard methodology
Specialized skill set
47. FPGA Component Implementation
• Start from scratch or reuse an existing core
• Not valuable until data and control interfaces are
properly handled
Registers don’t exist until Most likely has non-standard
they are created control and status registers
Need to define data
f(x) is written in a
bus widths, a specific data
Hardware Description
format, and a transfer protocol
Language (HDL)
May need to add flow
control to custom inputs
and outputs
Might require specific
Best practice to simulate timing requirements
48. FPGA Project Creation & Integration
Component development is the easy part…
Project integration is harder
Simulating the whole Even small project All physical interfaces
project is critical! modifications can be costly! need timing constraints
I/Os are not configured.
Even the clocks need to be created A project needs: pin assignments,
I/O standards, termination, data
Non-standard registers require
direction, drive strength, etc…
a custom control bus
Physical interfaces Components with custom
are required data interfaces
to transfer data off require adapters to
chip IRQs? communicate
What happens on
reset matters
49. ATLANTiS Enables Microprocessor-Like Approach
FPGA Abstraction Requires a Supporting Framework
• Provides a microprocessor/software-like approach to FPGA development
• Allows the FPGA to look like a System-on-a-Chip w/ peripheral support
• Greatly reduces integration effort
• ATLANTiS Provides:
Integrated System
Framework (SoC)
Data & Control Fabrics
• User Provides Only:
Custom Processing
Custom Interfacing
FINe
50. A Closer Look
ATLANTiS FrameWork for FPGA development is
composed of the following:
• Common Interfaces
• Component Libraries
Streaming Data Interconnect
Control & Memory Management
Physical Interfaces
SerDes Protocols
Utility Libraries & Resources
• Simulation & Test
• Flexible Architecture
• Project Support
• Software Development Library
51. Common Interfaces
A standard API for communication between a functional
component and its sources, sinks, masters and slaves.
Benefits:
Abstracts functionality & device interfaces
Avalon
Promotes component & full platform reuse Memory Mapped
Simplified design verification Interface
Enables automatic code generation
Avalon Avalon
Streaming f(x) Streaming
Data Sink Data Source
Basic Component Structure
AFW utilizes Altera’s Avalon Interface (MM & ST)
52. Component Libraries:
Streaming Data Interconnect
Not all Avalon Streaming Data Interfaces are the same!
- Bit widths, data format, packet structure, latency, and more can
vary between components
• Reconfigurable Data Ports
• Streaming data interconnect
fabrics –switching, mux/demux
• Flow Control – FIFOs
X • Data reshaping (Bit width, clock
rate, etc…)
Data Interface
Streaming
• Common adaptors – VIP
Data Fabric streaming data, OCP, …
• Proven Infrastructure
53. Component Libraries:
Control & Memory Management
Not all Avalon Memory Mapped Interfaces are the same!
- Address/data widths, pipelined or not, byte enables, master or
slave, bursting, read latency and more can vary between
components Arbiter
DPM
• Reconfigurable Control Ports
• Memory mapped fabrics – Memory Mapped Fabric
control, status, address Memory Mapped
decoding, arbitration Interface
• Interrupt handlers
• Reset infrastructure
• Storage – DPM, Register Bank
Processing Components
54. Component Libraries:
Physical Interfaces
Arguably the most difficult part of any FPGA design
- Board/pin specific physical properties like impedance, skew, and trace
length must be taken into account to achieve error free data transfer
FPGA Boundary
Board Specific I/O Map
Physical Interfaces Phy Intf
Avalon
AFW provides Key
validated Physical Interface
Physical Interface
Component
communication
paths, complete
Avalon
with proper timing User
Phy Intf
Map Port
constraints & I/O Port Map
Phy Intf
Processing
Avalon
Map Port
Avalon Phy Intf
configuration
Phy Intf Avalon
Port Map Map Port
Avalon Phy Intf
PLL and
Port Map Synch
Reset
Avalon
Phy Intf
Map
** Clock and Reset lines are made
available to all components at both
the Project and User levels.
55. Component Libraries:
Simulation & Test Resources
The quickest path to deployment is through full validation
- AFW supports software simulations and provides hooks for improved
on board test
• Scripted simulation control
• Standard data generators
Random, sine, cosine, sequence, pattern, file
• Verification and diagnostic components
Comparison, capture, threshold, BER, file
• Bus Functional Models (BFM) for each physical
interface, including memory models
56. Component Libraries:
Simulation & Test Resources (cont.)
• AFW Resources allow users to simulate the whole FPGA project
• Getting to this point is costly, we know, we did the work!
57. Component Libraries:
Utility Libraries & Resources
Cut Down on Development Effort
• Standard components for clocking & resets
• Commonly used signal processing functions
Scale, round, saturate
Mag est., magnitude squared Avalon Memory Mapped Interface
Min/max
• Common interface helper functions
Initialization
Scaling, resize, reshape Avalon Avalon
Streaming
Array interfaces Streaming
Data Source
Data Sink
• Recommended Design Practices
Common interface How-To
Project examples
Basic Component Structure
Component templates
Full component and project documentation
58. Software Development Library (BWIO)
Powerful software that saves
significant development time!
• AFW component drivers
• Standard POSIX-Based interface: open,
read, write, ioctl, close
• Portable to multiple different hosts –
TS201, embedded FINe/NIOS and
PC/LINUX (remote)
*Refer to BWIO Library documentation for more details
59. Example Project
Control Plane
Data Plane
Control/Config,
Avalon
Processing
Status and
Physical
Processing
Streaming Data
Utility Builder
SOPC Libraries
Interfaces
Memory
Interface
Components
Interconnect
Management
Components
60. ATLANTiS Summary
ATLANTiS FrameWork moves customers quickly &
confidently from design to deployment
• Raises the FPGA abstraction level
Follows a System On a Chip software methodology
Don’t have to start from scratch
Existing streaming & memory mapped interconnect fabrics
Low level physical interfaces & timing constraints are provided
Pre-existing projects & I/O configuration
• Promote design and FPGA code re-use
Avalon common interface components are reusable & portable
Standard component structure
Reconfigurable HDL components & supporting software development libraries
Straight-forward integration of third-party components
Works with proven, validated COTS boards
• Allows for improved design exploration and validation
Provides standardized simulation & test resources
Supports flexible, static and run-time reconfiguration
Reduce Risk, Trim Time, Cut Costs
Reduce Risk, Trim Time, Cut Costs