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CXL Switch For Future AI
Feb. 2024
Xconn Technologies
Accelerating AI/ML Computing
Introduction of CXL Switch
CXL switch enables scalability
• Efficiently fan out of a large memory expansion and pooling
• Composing an system with multiple heterogeous computing elements
• Simplify system architecture, lower overall TCO
CXL switch enables fabric networks
• multi-level switch and cascading for a computing fabric with thousands of nodes
CXL Switch
Accelerat
or
Memo
ry
CPUs CPUs
CXL Switch
Memo
ry
GFA
M
Memo
ry
CXL Switch CXL Switch
NIC NIC
CXL
Switch
CXL
Switch
Spine
Switches
Leaf
Switches
End
Devices
Fabric
Manag
er
Exampl
e
traffic
flow
XConn’s CXL 2.0 Switch
2,048 GB/s total
BW with 256 lanes
Lowest port-to-port latency
Lowest power consumption/port
• One single XC50256 connects to 32 combined hosts/devices
• Fully support CXL Fabric Manager
• Support switch cascading for a larger size memory pool
• CS (customer samples) now, MP 2Q24
Reduced PCB area
Lower TCO
World’s First CXL2.0
(XC50256) & PCIe 5.0
(XC51256) switch IC
Scalable Memory Expansion
• Assume each CXL memory device is 1 TB
• With a single XC50256 (30 DSPs), up to 30TB memory expansion
CXL Host
CXL 2.0 Switch
D1 … D30
CXL 2.0 Switch
D91 … D120
CXL Host
CXL 2.0 Switch
D30
D1 D2 …
Scalable Memory Pooling & Sharing
Memory Pooling with CXL 1.1/2.0 Hosts and
CXL Memory Devices (SLD and MLD)
D#
H#
D1
H1
D3
H3
D4
H4
D2
H2
CXL 2.0 Switch
Management Host
(CXL FabricManager)
Software Enables CXL 2.0 Based
Memory Sharing
Apollo Ref. Board
CXL Host 0
Management
Host (FM)
CXL Host 1
CXL Memory Expander 0 CXL Memory Expander 1
Node
App
Gismo Library
Gismo
Manager
CPU
Node
App
Gismo Library
CPU
Node
App
Gismo Library
CPU
Shared Memory over CXL
DDR DRAM
(NUMA 0)
DDR DRAM
(NUMA 0)
DDR DRAM
(NUMA 0)
CXL Memory Sharing via
Switch for AI Computing
CXL Memory Sharing is superior than RDMA, due to:
• Lower latency
• Energy efficient
• Simplified programming
• Memory coherency
• Scalability to very large memory
• Lower TCO
CXL memory sharing will boost performance of AI systems hugely
CXL3.1 Switch for AI/ML Systems
…
…
…
…
CXL CPU0 CXL CPU1
NIC/DPU POOL
SSD POOL
CXL MEMORY/
In-Memory Compute
CXL MEMORY
ACC ACC ACC ACC ACC ACC ACC ACC
To CXL Spine Switch
• Memory pooling/sharing/expansion
• Supports All-to-All with scalable
large switching capacity
• Fit for All-reduce, All-gather with
super low latency and high
bandwidth switching
• Scablable fabric network with up
to 4,096 CXL devices
• Hybrid CXL/PCIe mode to connect
CXL and PCIe devices
• Works with emerging CXL devices,
e.g. In Memory Compute
• Lower total power consumption to
reduce energy cost
CXL 3.x
Switch
…
CXL 3.x
Switch CXL 3.x
Switch
XConn – One Switch, Triple Usages
PCIe Only
Apollo I
256 Lane Switch
Hybrid Mode
Apollo I is using Virtual Switch Feature to support 2 CPUs
Apollo I can be split into any ratio between CXL and PCIe
GP
U
#1
GP
U
#4
NIC
#1
NIC
#2
SS
D
#1
SS
D
#2
…
x16 x16 x16 x16 x8 x8
x16 x16
…
Me
m
#1
Me
m
#2
Me
m
#3
Me
m
#5
Me
m
#11
x16 x16 x16
x8 x8
CPU 2
CPU 1
Apollo I
256 Lane Switch
Apollo I is using Virtual Switch Feature to support 2 CPUs
GP
U
#1
GP
U
#4
NIC
#1
NIC
#2
SS
D
#1
SS
D
#2
…
x16 x16 x16 x16 x8 x8
x16 x16
…
NIC
#3
NIC
#4
SS
D
#3
SS
D
#4
GP
U
#5
GP
U
#8
x16 x16 x8 x8
x16 x16
CPU 2
CPU 1
CXL ONLY
Apollo I
256 Lane Switch
Apollo I is using Virtual Switch Feature to support 2 CPUs
Me
m#
1
Me
m
#2
Me
m
#3
Me
m
#5
Me
m
#11
…
x16 x16 x16 x8 x8
x16 x16
…
Me
m
#12
Me
m
#13
Me
m#
14
Me
m
#15
Me
m
#22
x16 x16 x16
x8 x8
CPU 2
CPU 1
XC50256 – 256-lane CXL 2.0 (and PCIe 5.0) Switch
XC51256 – 256-lane PCIe 5.0 (only) Switch
Customers can migrate from PCIe (XC51256) to CXL (XC50256) or vice-versa, or mix-and-match
CXL & PCIe in Hybrid Mode (XC50256) in the same silicon, without any change in their hardware
PCIe Mode CXL Mode
Call for Actions
Join the CXL Consortium
Collaborate on the next generation AI and
computing systems using CXL Technologies
Contact XConn Technologies for a demo of CXL
memory pooling and sharing
Address:
1245 S. Winchester Blvd
San Jose, CA 95128
Web:
Https://www.xconn-tech.com
Email:
JP.Jiang@xconn-tech.com

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Q1 Memory Fabric Forum: XConn CXL Switches for AI

  • 1. CXL Switch For Future AI Feb. 2024 Xconn Technologies Accelerating AI/ML Computing
  • 2. Introduction of CXL Switch CXL switch enables scalability • Efficiently fan out of a large memory expansion and pooling • Composing an system with multiple heterogeous computing elements • Simplify system architecture, lower overall TCO CXL switch enables fabric networks • multi-level switch and cascading for a computing fabric with thousands of nodes CXL Switch Accelerat or Memo ry CPUs CPUs CXL Switch Memo ry GFA M Memo ry CXL Switch CXL Switch NIC NIC CXL Switch CXL Switch Spine Switches Leaf Switches End Devices Fabric Manag er Exampl e traffic flow
  • 3. XConn’s CXL 2.0 Switch 2,048 GB/s total BW with 256 lanes Lowest port-to-port latency Lowest power consumption/port • One single XC50256 connects to 32 combined hosts/devices • Fully support CXL Fabric Manager • Support switch cascading for a larger size memory pool • CS (customer samples) now, MP 2Q24 Reduced PCB area Lower TCO World’s First CXL2.0 (XC50256) & PCIe 5.0 (XC51256) switch IC
  • 4. Scalable Memory Expansion • Assume each CXL memory device is 1 TB • With a single XC50256 (30 DSPs), up to 30TB memory expansion CXL Host CXL 2.0 Switch D1 … D30 CXL 2.0 Switch D91 … D120 CXL Host CXL 2.0 Switch D30 D1 D2 …
  • 5. Scalable Memory Pooling & Sharing Memory Pooling with CXL 1.1/2.0 Hosts and CXL Memory Devices (SLD and MLD) D# H# D1 H1 D3 H3 D4 H4 D2 H2 CXL 2.0 Switch Management Host (CXL FabricManager)
  • 6. Software Enables CXL 2.0 Based Memory Sharing Apollo Ref. Board CXL Host 0 Management Host (FM) CXL Host 1 CXL Memory Expander 0 CXL Memory Expander 1 Node App Gismo Library Gismo Manager CPU Node App Gismo Library CPU Node App Gismo Library CPU Shared Memory over CXL DDR DRAM (NUMA 0) DDR DRAM (NUMA 0) DDR DRAM (NUMA 0)
  • 7. CXL Memory Sharing via Switch for AI Computing CXL Memory Sharing is superior than RDMA, due to: • Lower latency • Energy efficient • Simplified programming • Memory coherency • Scalability to very large memory • Lower TCO CXL memory sharing will boost performance of AI systems hugely
  • 8. CXL3.1 Switch for AI/ML Systems … … … … CXL CPU0 CXL CPU1 NIC/DPU POOL SSD POOL CXL MEMORY/ In-Memory Compute CXL MEMORY ACC ACC ACC ACC ACC ACC ACC ACC To CXL Spine Switch • Memory pooling/sharing/expansion • Supports All-to-All with scalable large switching capacity • Fit for All-reduce, All-gather with super low latency and high bandwidth switching • Scablable fabric network with up to 4,096 CXL devices • Hybrid CXL/PCIe mode to connect CXL and PCIe devices • Works with emerging CXL devices, e.g. In Memory Compute • Lower total power consumption to reduce energy cost CXL 3.x Switch … CXL 3.x Switch CXL 3.x Switch
  • 9. XConn – One Switch, Triple Usages PCIe Only Apollo I 256 Lane Switch Hybrid Mode Apollo I is using Virtual Switch Feature to support 2 CPUs Apollo I can be split into any ratio between CXL and PCIe GP U #1 GP U #4 NIC #1 NIC #2 SS D #1 SS D #2 … x16 x16 x16 x16 x8 x8 x16 x16 … Me m #1 Me m #2 Me m #3 Me m #5 Me m #11 x16 x16 x16 x8 x8 CPU 2 CPU 1 Apollo I 256 Lane Switch Apollo I is using Virtual Switch Feature to support 2 CPUs GP U #1 GP U #4 NIC #1 NIC #2 SS D #1 SS D #2 … x16 x16 x16 x16 x8 x8 x16 x16 … NIC #3 NIC #4 SS D #3 SS D #4 GP U #5 GP U #8 x16 x16 x8 x8 x16 x16 CPU 2 CPU 1 CXL ONLY Apollo I 256 Lane Switch Apollo I is using Virtual Switch Feature to support 2 CPUs Me m# 1 Me m #2 Me m #3 Me m #5 Me m #11 … x16 x16 x16 x8 x8 x16 x16 … Me m #12 Me m #13 Me m# 14 Me m #15 Me m #22 x16 x16 x16 x8 x8 CPU 2 CPU 1 XC50256 – 256-lane CXL 2.0 (and PCIe 5.0) Switch XC51256 – 256-lane PCIe 5.0 (only) Switch Customers can migrate from PCIe (XC51256) to CXL (XC50256) or vice-versa, or mix-and-match CXL & PCIe in Hybrid Mode (XC50256) in the same silicon, without any change in their hardware PCIe Mode CXL Mode
  • 10. Call for Actions Join the CXL Consortium Collaborate on the next generation AI and computing systems using CXL Technologies Contact XConn Technologies for a demo of CXL memory pooling and sharing
  • 11. Address: 1245 S. Winchester Blvd San Jose, CA 95128 Web: Https://www.xconn-tech.com Email: JP.Jiang@xconn-tech.com

Editor's Notes

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  2. host