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Morello Technology Demonstrator Hardware Overview - Mark Inskip, Arm

Presentation from the briefing event for ISCF Digital Security by Design competition: Technology Enabled Business-Led Demonstator Stage 1 Expression of Interest

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Morello Technology Demonstrator Hardware Overview - Mark Inskip, Arm

  1. 1. © 2020 Arm Limited (or its affiliates) Mark Inskip, Program Director Arm Central Engineering 17 March 2020 Morello Technology Demonstrator Hardware Overview
  2. 2. 2 © 2020 Arm Limited (or its affiliates) Morello Board: Capability Hardware Prototype Platform • Silicon implementation of a Capability Hardware CPU Instruction Set Architecture • Implements Morello Profile for A-class Prototype Architecture • Two clusters each of two Rainier CPUs • Interconnect and Memory Controller support for tagged memory • Two channel DDR4 DRAM interface • PCIe Gen3 and Gen4 x16 interface • CCIX (Cache Coherent Interconnect for Accelerators) interface • Mid-range GPU, display processor and HDMI output • On standard uATX form factor board CoreSightSoC-600 Skeena (CoreLink CMN-600 based) CoreLink GIC-600 CoreLink NIC-400 IOFPGA SCP Cortex-M7 MCP Cortex-M7DDR4-2667 Bing (DMC-620 based) CCIXPCIe MMU-600 Rainier ELA-500 Rainier ELA-500 Bing (DMC-620 based) HDMI Mali-D35 Mali-G76 UEFI boot, SCP/MCP FirmwareTrusted Firmware-A Linux Kernel Supporting Arm system IP: GIC-600 (Generic Interrupt Controller), MMU-600 (IO MMU), Dynamic Memory Controller derived from DMC-620, SoC-600 (SoC Debug and Trace), Coherent Mesh Network derived from CMN-600, NIC-400 (Non-coherent interconnect) Supporting 3rd party system IP/hardware: PCIe/CCIX Root Complex (PHY and controller), DDR4/3 PHY, DDR4 memory, IO FPGA Open-source software stack
  3. 3. 3 © 2020 Arm Limited (or its affiliates) Overview – Hardware Bring-up and Roll Out Platforms and milestones Hardware Platform Development Platform and Architecture Enablement Hardware development and bring up SoC and development board design, fabrication, bring up and validation Hardware roll-out Development board manufacture and production test AArch64 platform and Morello architecture support See Morello software and toolchain presentation Development board October 2021 December 2021 evolving functionality Volume shipping
  4. 4. 4 © 2020 Arm Limited (or its affiliates) Morello Block Diagram • Mali-D35 display processor • Single display output • Digital 8:8:8 RGB Output • UXGA60 : 1600x 1200 @60fps • Mali-G76 (Bifrost) • Mid-range GPU • x4 shaders • 256KByte L2 • SODIMM DDR4 2667 x2 (72pin) • 42.7GBytes/s • Capability bit in ECC • Tag$ implementation • SCP & MCP • As per N1 SDP • System control including boot • 2 MP2 Rainier clusters • L1/L2 cache modifications to proliferate capability bit • PCIe gen4 configuration • x16 PCIe CCIX enabled • x16 PCIe IO • Thin Links as per N1 SDP • Facilitates a broader set of IO not contained within the SoC itself 2 x DMC Bing MP2 CPU Rainier Mali-G76 Mali-D35PCIe Gen4 x16 CCIX PCIe x16 MP2 CPU Rainier MCP & SCP CMN-Skeena
  5. 5. 5 © 2020 Arm Limited (or its affiliates) Morello SoC IP Features • CPU Rainier • Based on Morello for A-Profile architecture • Implemented using baseline Neoverse N1 CPU • 2 dual Rainier (MP2) clusters – 4 cores in total • Separate Voltage domain per cluster • Frequency : 2.0 GHz • CMN-Skeena • Based on CMN-600 Coherent Mesh Network • Updated to support transport of ‘tag’ bits from CPUs to DMC-Bing • 4MB System Level Cache, 8MB Snoop Filter • Frequency : 1.5 GHz • DMC-Bing • Two x72-bit DDR4-2667 memory based on DMC-620 • Modified ECC and ‘tag’ cache modes • On chip DDR4 PHY from Cadence • Frequency: 1.33 GHz (DDR4-2667) giving 42.7GBytes/s • GPU Mali-G76 • Bifrost architecture • 4 Shader Cores, 256 KB L2$ • Supports AFBC format • IO Coherent with CPUs • DPU Mali-D35 • Single Display output • Off-chip display PHY (HDMI) • RGB 8:8:8 display output • UXGA60 Resolution (1600 x 1200 @60fps) • PCIe and CCIX • 1 x16 Lane Gen4 PCIe with CCIX support enabling accelerators for chip2chip coherency • Second 1 X16 lane standard Gen4 PCIe Root Port • PCIe / CCIX integration based on SBSA v3.0 • On chip PCIe PHY and PCIe Controller IP from Cadence
  6. 6. 6 © 2020 Arm Limited (or its affiliates) Overview of the Morello Board 1x CCIX compatible PCIe Gen4 x16 slot 3 x Standard PCIe Gen3 x16 slot routed as x16, x8, x1 PCIe Gen3 Switch 2 x SATA II Rear I/O connections HDMI1.4a output 1Gb Ethernet RJ45 4 x USB3.0 PCC Ethernet Config USB (inc UARTs) 32 bit TRACE (MIPI 60) Morello SoC 2 x 72 bit DDR4 RDIMMS, one per channel (16GByte standard config) Motherboard controller (MCC) Morello SoC IOFPGA
  7. 7. 7 © 2020 Arm Limited (or its affiliates) PCIe Routing and Gen3 Switch Functionality Morello SoC
  8. 8. 8 © 2020 Arm Limited (or its affiliates) Morello Hardware Debug Options • ULINKPlus supports all classic debug features such as simple and complex breakpoints and multi-core debugging* • DSTREAM-PT high-performance debug and trace capability, with up to 32 pins parallel trace support and on probe 8GB trace memory store *on-board integration of ULINKPlus under investigation but not confirmed
  9. 9. © 2020 Arm Limited (or its affiliates) Thank You Danke Merci 谢谢 ありがとう Gracias Kiitos 감사합니다 धन्यवाद ‫ا‬ً‫شكر‬ ধন্যবাদ ‫תודה‬
  10. 10. The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. © 2020 Arm Limited (or its affiliates)