During the CXL Forum at OCP Global Summit, memory system architect Jungmin Choi of SK hynix talks about the need for memory bandwidth and capacity, and the SK hynix Niagara solution.
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
During the CXL Forum at OCP Global Summit, Jeff Hilland of HPE explained what CXL, PCI SIG, DMTF, OFA, OCP, and SNIA are doing to make CXL fabric, memory and device management interoperable.
Arm: Enabling CXL devices within the Data Center with Arm SolutionsMemory Fabric Forum
During the CXL Forum at OCP Summit, Arm Director of Segment Marketing Parag Beeraka provides and overview of the Arm portfolio of CXL products for the Data Center
During the CXL Forum at OCP Global Summit, MemVerge software architect Steve Scargall defines the CXL software stack and where the development is being done.
Q1 Memory Fabric Forum: Compute Express Link (CXL) 3.1 UpdateMemory Fabric Forum
OCP Steering Committee member and ex-President of the CXL Consortium, Siamak Tavallaei, provides an update on the CXL specifications with a focus on the recently released 3.1 specification.
All Presentations during CXL Forum at Flash Memory Summit 22Memory Fabric Forum
This deck includes presentations made during the CXL Forum at Flash Memory Summit 22 delivered by AMD, Intel, NVIDIA, The CXL Consortium, The Open Compute Project, Marvell, MemVerge, Micron, SK hynix, Samsung, and VMware
During the CXL Forum at OCP Global Summit, Mahesh Wagh, CXL Consortium TTF Co-chair and Senior Fellow at AMD, presented and update of the CXL Consortium mission and road map.
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
During the CXL Forum at OCP Global Summit, Jeff Hilland of HPE explained what CXL, PCI SIG, DMTF, OFA, OCP, and SNIA are doing to make CXL fabric, memory and device management interoperable.
Arm: Enabling CXL devices within the Data Center with Arm SolutionsMemory Fabric Forum
During the CXL Forum at OCP Summit, Arm Director of Segment Marketing Parag Beeraka provides and overview of the Arm portfolio of CXL products for the Data Center
During the CXL Forum at OCP Global Summit, MemVerge software architect Steve Scargall defines the CXL software stack and where the development is being done.
Q1 Memory Fabric Forum: Compute Express Link (CXL) 3.1 UpdateMemory Fabric Forum
OCP Steering Committee member and ex-President of the CXL Consortium, Siamak Tavallaei, provides an update on the CXL specifications with a focus on the recently released 3.1 specification.
All Presentations during CXL Forum at Flash Memory Summit 22Memory Fabric Forum
This deck includes presentations made during the CXL Forum at Flash Memory Summit 22 delivered by AMD, Intel, NVIDIA, The CXL Consortium, The Open Compute Project, Marvell, MemVerge, Micron, SK hynix, Samsung, and VMware
During the CXL Forum at OCP Global Summit, Mahesh Wagh, CXL Consortium TTF Co-chair and Senior Fellow at AMD, presented and update of the CXL Consortium mission and road map.
Shared Memory Centric Computing with CXL & OMIAllan Cantle
Discusses how CXL can be better utilized as a separate Fabric Cache domain to a processors own Local Cache Domain. This is done by leveraging a Shared Memory Centric architectures that utilize both the Open Memory Interface OMI, and Compute eXpress Link, CXL, for the memory ports.
Molex and Nvidia - Partnership to enable copper for the next generation artif...Memory Fabric Forum
During the CXL Forum at OCP Global Summit, Eddy Hwang of Nvidia and Wai Kong Poon of Molex presented a next-gen architecture for enabling copper for AI computing.
During the CXL Forum at OCP Global Summit, MemVerge CEO Charles Fan presented accomplishments of the CXL industry since 2019, the development of concept cars occurring today, and his predictions for the future of CXL
Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203Linaro
Session ID: SFO17-203
Session Name: Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203
Speaker: Fu Wei
Track: LEG
★ Session Summary ★
This presentation gives an updated RAS architecture on ARM64 base on RAS extension (in ARMv8.2), SDEI (Software Delegated Exception Interface), APEI, UEFI PI-SMM. Will talk about all the components of the new RAS architecture on ARM64, gives audience the current status and the next step of development.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/sfo17/sfo17-203/
Presentation:
Video: https://www.youtube.com/watch?v=NReFBzbeWi0
---------------------------------------------------
★ Event Details ★
Linaro Connect San Francisco 2017 (SFO17)
25-29 September 2017
Hyatt Regency San Francisco Airport
---------------------------------------------------
Keyword:
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
During the CXL Forum at OCP Global Summit, Enfabrica CEO Rochan Sankar described how to bridge the network and memory worlds with their accelerated compute fabric switch.
Q1 Memory Fabric Forum: Memory Processor Interface 2023, Focus on CXLMemory Fabric Forum
Thibault Grossi, Sr. Technology & Market Analyst, shares excerpts from the recently published report, Memory Processor Interface, Focus on CXL. The reports provides a taxonomy of CXL market segments and revenue forecasts through 2028.
Torry Steed, Sr. Product Marketing Manager at SMART Modular, provides an overview of CXL PCIe Add-in Cards (AICs) and memory modules that can be used to expand capacity in servers or in external memory pooling systems.
Q1 Memory Fabric Forum: Building Fast and Secure Chips with CXL IPMemory Fabric Forum
Gary Ruggles, Sr Product Manger for PCIe and CXL Controller IP, provides an provides example use cases for adoption of CXL, an introduction to Synopsys CXL IP Solutions, interop and proof points.
MemVerge CEO Charles Fan describes why memory-hungry generative AI is a driver for CXL technology, the new computing model for AI, and MemVerge software for CXL and AI.
Lightelligence: Optical CXL Interconnect for Large Scale Memory PoolingMemory Fabric Forum
During the CXL Forum at OCP Global Summit, Lightelligence Director of Engineering Ron Swatzentruber provides an overview of the company's optical port expander products and test results.
If AMD Adopted OMI in their EPYC ArchitectureAllan Cantle
AMD's EPYC Architecture has paved the way forward towards Heterogeneous Data Centric Computing, but it is still limited by it's parallel DDR interfaces. This presentation shows the potential for the EPYC architecture if it adopted the Open Memory Interface, OMI, for it's Near Memory interface.
In the CXL Forum Theater at SC23 hosted by MemVerge, the Open Compute Project provided an overview of CXL, as well as CXL-related hardware and software projects at OCP
During the CXL Forum at OCP Global Summit, Michael Ocampo of Astera Labs explained the problem of the memory wall, and how CXL memory powered by Astera Labs can break through
Optimizing Performance and Computing Resource Efficiency of In-Memory Big Dat...Databricks
The performance of modern Big Data frameworks, e.g. Spark, depends greatly on high-speed storage and shuffling, which impose a significant memory burden on production data centers. In many production situations, the persistence and shuffling intensive applications can lead to a major performance loss due to lack of memory. Thus, the common practice is usually to over-allocate the memory assigned to the data workers for production applications, which in turn reduces overall resource utilization. One efficient way to address the dilemma between the performance and cost efficiency of Big Data applications is through data center computing resource disaggregation. This paper proposes and implements a system that incorporates the Apache Spark Big Data framework with a novel in-memory distributed file system to achieve memory disaggregation for data persistence and shuffling. We address the challenge of optimizing performance at a low cost by co-designing the proposed in-memory distributed file system with large-volume DIMMbased persistent memory (PMEM) and RDMA technology. The disaggregation design allows each part of the system to be scaled independently, which is particularly suitable for cloud deployments. The proposed system is evaluated in a productionlevel cluster using real enterprise-level Spark production applications. The results of an empirical evaluation show that the system can achieve up to a 3.5-fold performance improvement for shuffle-intensive applications with the same amount of memory, compared to the default Spark setup. Moreover, by leveraging PMEM, we demonstrate that our system can effectively increase by 66.5% the memory capacity of the computing cluster with affordable cost, with a reasonable execution time overhead with respect to using local DRAM only.
Shared Memory Centric Computing with CXL & OMIAllan Cantle
Discusses how CXL can be better utilized as a separate Fabric Cache domain to a processors own Local Cache Domain. This is done by leveraging a Shared Memory Centric architectures that utilize both the Open Memory Interface OMI, and Compute eXpress Link, CXL, for the memory ports.
Molex and Nvidia - Partnership to enable copper for the next generation artif...Memory Fabric Forum
During the CXL Forum at OCP Global Summit, Eddy Hwang of Nvidia and Wai Kong Poon of Molex presented a next-gen architecture for enabling copper for AI computing.
During the CXL Forum at OCP Global Summit, MemVerge CEO Charles Fan presented accomplishments of the CXL industry since 2019, the development of concept cars occurring today, and his predictions for the future of CXL
Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203Linaro
Session ID: SFO17-203
Session Name: Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203
Speaker: Fu Wei
Track: LEG
★ Session Summary ★
This presentation gives an updated RAS architecture on ARM64 base on RAS extension (in ARMv8.2), SDEI (Software Delegated Exception Interface), APEI, UEFI PI-SMM. Will talk about all the components of the new RAS architecture on ARM64, gives audience the current status and the next step of development.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/sfo17/sfo17-203/
Presentation:
Video: https://www.youtube.com/watch?v=NReFBzbeWi0
---------------------------------------------------
★ Event Details ★
Linaro Connect San Francisco 2017 (SFO17)
25-29 September 2017
Hyatt Regency San Francisco Airport
---------------------------------------------------
Keyword:
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
During the CXL Forum at OCP Global Summit, Enfabrica CEO Rochan Sankar described how to bridge the network and memory worlds with their accelerated compute fabric switch.
Q1 Memory Fabric Forum: Memory Processor Interface 2023, Focus on CXLMemory Fabric Forum
Thibault Grossi, Sr. Technology & Market Analyst, shares excerpts from the recently published report, Memory Processor Interface, Focus on CXL. The reports provides a taxonomy of CXL market segments and revenue forecasts through 2028.
Torry Steed, Sr. Product Marketing Manager at SMART Modular, provides an overview of CXL PCIe Add-in Cards (AICs) and memory modules that can be used to expand capacity in servers or in external memory pooling systems.
Q1 Memory Fabric Forum: Building Fast and Secure Chips with CXL IPMemory Fabric Forum
Gary Ruggles, Sr Product Manger for PCIe and CXL Controller IP, provides an provides example use cases for adoption of CXL, an introduction to Synopsys CXL IP Solutions, interop and proof points.
MemVerge CEO Charles Fan describes why memory-hungry generative AI is a driver for CXL technology, the new computing model for AI, and MemVerge software for CXL and AI.
Lightelligence: Optical CXL Interconnect for Large Scale Memory PoolingMemory Fabric Forum
During the CXL Forum at OCP Global Summit, Lightelligence Director of Engineering Ron Swatzentruber provides an overview of the company's optical port expander products and test results.
If AMD Adopted OMI in their EPYC ArchitectureAllan Cantle
AMD's EPYC Architecture has paved the way forward towards Heterogeneous Data Centric Computing, but it is still limited by it's parallel DDR interfaces. This presentation shows the potential for the EPYC architecture if it adopted the Open Memory Interface, OMI, for it's Near Memory interface.
In the CXL Forum Theater at SC23 hosted by MemVerge, the Open Compute Project provided an overview of CXL, as well as CXL-related hardware and software projects at OCP
During the CXL Forum at OCP Global Summit, Michael Ocampo of Astera Labs explained the problem of the memory wall, and how CXL memory powered by Astera Labs can break through
Optimizing Performance and Computing Resource Efficiency of In-Memory Big Dat...Databricks
The performance of modern Big Data frameworks, e.g. Spark, depends greatly on high-speed storage and shuffling, which impose a significant memory burden on production data centers. In many production situations, the persistence and shuffling intensive applications can lead to a major performance loss due to lack of memory. Thus, the common practice is usually to over-allocate the memory assigned to the data workers for production applications, which in turn reduces overall resource utilization. One efficient way to address the dilemma between the performance and cost efficiency of Big Data applications is through data center computing resource disaggregation. This paper proposes and implements a system that incorporates the Apache Spark Big Data framework with a novel in-memory distributed file system to achieve memory disaggregation for data persistence and shuffling. We address the challenge of optimizing performance at a low cost by co-designing the proposed in-memory distributed file system with large-volume DIMMbased persistent memory (PMEM) and RDMA technology. The disaggregation design allows each part of the system to be scaled independently, which is particularly suitable for cloud deployments. The proposed system is evaluated in a productionlevel cluster using real enterprise-level Spark production applications. The results of an empirical evaluation show that the system can achieve up to a 3.5-fold performance improvement for shuffle-intensive applications with the same amount of memory, compared to the default Spark setup. Moreover, by leveraging PMEM, we demonstrate that our system can effectively increase by 66.5% the memory capacity of the computing cluster with affordable cost, with a reasonable execution time overhead with respect to using local DRAM only.
Q1 Memory Fabric Forum: Using CXL with AI Applications - Steve Scargall.pptxMemory Fabric Forum
MemVerge product manager and software architect Steve Scargall discusses key factors related to the use of CXL with AI apps including, memory expansion form factors, latency and bandwidth memory placement strategies, RDBMS investigation and results, vector database investigation, and results understanding your application behavior.
CFD acceleration with FPGA (byteLAKE's presentation from PPAM 2019)byteLAKE
byteLAKE's presentation from the PPAM 2019 conference.
Abstract:
The goal of this work is to adapt 4 CFD kernels to the Xilinx ALVEO U250 FPGA, including first-order step of the non-linear iterative upwind advection MPDATA schemes (non-oscillatory forward in time), the divergence part of the matrix-free linear operator formulation in the iterative Krylov scheme, tridiagonal Thomas algorithm for vertical matrix inversion inside preconditioner for the iterative solver, and computation of the psuedovelocity for the second pass of upwind algorithm in MPDATA. All the kernels use 3-dimensional compute domain consisted from 7 to 11 arrays. Since all kernels belong to the group of memory bound algorithms, our main challenge is to provide the highest utilization of global memory bandwidth. Our adaptation allows us to reduce the execution time upto 4x.
Find out more at: www.byteLAKE.com/en/CFD
Foot note:
This is the presentation about the non-AI version of byteLAKE's CFD kernels, highly optimized for Alveo FPGA. Based on this research project and many others in the CFD space, we decided to shift the course of the CFD Suite product development and leverage AI to accelerate computations and enable new possibilities. Instead of adapting CFD solvers to accelerators, we use AI and work on a cross-platform solution. More on the latest: www.byteLAKE.com/en/CFDSuite.
-
Update for 2020: byteLAKE is currently developing CFD Suite as AI for CFD Suite, a collection of AI/ Artificial Intelligence Models to accelerate and enable new features for CFD simulations. It is a cross-platform solution (not only for FPGAs). More: www.byteLAKE.com/en/CFDSuite.
Ecosystem Alliance Manager Michael Ocampo talks about the CXL industry's effort to break through the memory wall, memory bound use cases, CXL for modular shared infrastructure, and critical CXL collaboration that's happening now.
Inter connect2016 yss1841-cloud-storage-options-v4Tony Pearson
This session will cover private and public cloud storage options, including flash, disk and tape, to address the different types of cloud storage requirements. It will also explain the use of Active File Management for local space management and global access to files, and support for file-and-sync.
Q1 Memory Fabric Forum: Memory expansion with CXL-Ready Systems and DevicesMemory Fabric Forum
Ravi Gummaluri, Director, CXL System Architecture at Micron describes use cases for memory expansion with tiered DRAM and CXL memory, along with performance data.
SF Big Analytics & SF Machine Learning Meetup: Machine Learning at the Limit ...Chester Chen
Machine Learning at the Limit
John Canny, UC Berkeley
How fast can machine learning and graph algorithms be? In "roofline" design, every kernel is driven toward the limits imposed by CPU, memory, network etc. This can lead to dramatic improvements: BIDMach is a toolkit for machine learning that uses rooflined design and GPUs to achieve two- to three-orders of magnitude improvements over other toolkits on single machines. These speedups are larger than have been reported for *cluster* systems (e.g. Spark/MLLib, Powergraph) running on hundreds of nodes, and BIDMach with a GPU outperforms these systems for most common machine learning tasks. For algorithms (e.g. graph algorithms) which do require cluster computing, we have developed a rooflined network primitive called "Kylix". We can show that Kylix approaches the rooline limits for sparse Allreduce, and empirically holds the record for distributed Pagerank. Beyond rooflining, we believe there are great opportunities from deep algorithm/hardware codesign. Gibbs Sampling (GS) is a very general tool for inference, but is typically much slower than alternatives. SAME (State Augmentation for Marginal Estimation) is a variation of GS which was developed for marginal parameter estimation. We show that it has high parallelism, and a fast GPU implementation. Using SAME, we developed a GS implementation of Latent Dirichlet Allocation whose running time is 100x faster than other samplers, and within 3x of the fastest symbolic methods. We are extending this approach to general graphical models, an area where there is currently a void of (practically) fast tools. It seems at least plausible that a general-purpose solution based on these techniques can closely approach the performance of custom algorithms.
Bio
John Canny is a professor in computer science at UC Berkeley. He is an ACM dissertation award winner and a Packard Fellow. He is currently a Data Science Senior Fellow in Berkeley's new Institute for Data Science and holds a INRIA (France) International Chair. Since 2002, he has been developing and deploying large-scale behavioral modeling systems. He designed and protyped production systems for Overstock.com, Yahoo, Ebay, Quantcast and Microsoft. He currently works on several applications of data mining for human learning (MOOCs and early language learning), health and well-being, and applications in the sciences.
Multi-core processor and Multi-channel memory architectureUmair Amjad
Content of presentation:
Multi-core processors
Multi-channel memory architecture
Comparison between single and multi channel memory
Conclusion
References
Factored Operating Systems (fos) - The Case for a Scalable Operating System for Multicores - Designing a new operating system targeting manycore
systems with scalability as the primary design constraint,
where space sharing replaces time sharing to increase
scalability.
Have you heard that all in-memory databases are equally fast but unreliable, inconsistent and expensive? This session highlights in-memory technology that busts all those myths.
Redis, the fastest database on the planet, is not a simply in-memory key-value data-store; but rather a rich in-memory data-structure engine that serves the world’s most popular apps. Redis Labs’ unique clustering technology enables Redis to be highly reliable, keeping every data byte intact despite hundreds of cloud instance failures and dozens of complete data-center outages. It delivers full CP system characteristics at high performance. And with the latest Redis on Flash technology, Redis Labs achieves close to in-memory performance at 70% lower operational costs. Learn about the best uses of in-memory computing to accelerate everyday applications such as high volume transactions, real time analytics, IoT data ingestion and more.
In-memory processing has started to become the norm in large scale data handling. This is aclose to the metal analysis of highly important but often neglected aspects of memory accesstimes and how it impacts big data and NoSQL technologies.We cover aspects such as the TLB, the Transparent Huge Pages, the QPI Link, Hyperthreading and the impact of virtualization on high-memory footprint applications. We present benchmarks of various technologies ranging from Cloudera’s Impala to Couchbase and how they are impacted by the underlying hardware.The key takeaway is a better understanding of how to size a cluster, how to choose a cloud provider and an instance type for big data and NoSQL workloads and why not every core or GB of RAM is created equal.
Organizations continue to adopt Solr because of its ability to scale to meet even the most demanding workflows. Recently, LucidWorks has been leading the effort to identify, measure, and expand the limits of Solr. As part of this effort, we've learned a few things along the way that should prove useful for any organization wanting to scale Solr. Attendees will come away with a better understanding of how sharding and replication impact performance. Also, no benchmark is useful without being repeatable; Tim will also cover how to perform similar tests using the Solr-Scale-Toolkit in Amazon EC2.
Using Apache Spark to analyze large datasets in the cloud presents a range of challenges. Different stages of your pipeline may be constrained by CPU, memory, disk and/or network IO. But what if all those stages have to run on the same cluster? In the cloud, you have limited control over the hardware your cluster runs on.
You may have even less control over the size and format of your raw input files. Performance tuning is an iterative and experimental process. It’s frustrating with very large datasets: what worked great with 30 billion rows may not work at all with 400 billion rows. But with strategic optimizations and compromises, 50+ TiB datasets can be no big deal.
By using Spark UI and simple metrics, explore how to diagnose and remedy issues on jobs:
Sizing the cluster based on your dataset (shuffle partitions)
Ingestion challenges – well begun is half done (globbing S3, small files)
Managing memory (sorting GC – when to go parallel, when to go G1, when offheap can help you)
Shuffle (give a little to get a lot – configs for better out of box shuffle) – Spill (partitioning for the win)
Scheduling (FAIR vs FIFO, is there a difference for your pipeline?)
Caching and persistence (it’s the cost of doing business, so what are your options?)
Fault tolerance (blacklisting, speculation, task reaping)
Making the best of a bad deal (skew joins, windowing, UDFs, very large query plans)
Writing to S3 (dealing with write partitions, HDFS and s3DistCp vs writing directly to S3)
Similar to SK hynix CXL Disaggregated Memory Solution (20)
Q1 Memory Fabric Forum: ZeroPoint. Remove the waste. Release the power.Memory Fabric Forum
Nilesh Shah provide an overview of the ZeroPoint portable, hardware IP portfolio for lossless memory compression and compaction. The IP boosts memory capacity 2-4x, bandwidth and performance/watt by 50%, and is 1,000x faster than competitors.
Q1 Memory Fabric Forum: CXL-Related Activities within OCPMemory Fabric Forum
OCP steering committee member, and former President of the CXL Consortium, Siamak Tavallaei, provides an overview of CXL-related activities happening within the Open Compute Project.
Q1 Memory Fabric Forum: CXL Controller by Montage TechnologyMemory Fabric Forum
For CXL AIC and memory module designers, Nilesh Shah of Montage provides and overview of their CXL memory controller product, technology, and performance.
Nick Kriczsky and Gorden Getty provide an overview of Teledyne LeCroy’s Austin Labs portfolio of products to services including: 1) testing for protocol and electrical compliance, interoperability, data integrity, and performance, 2) In depth protocol training (PCIe, USB, NVMe, NVMe-oF, Fibre Channel), and 3) Automation (solutions for analysis, jamming, generation)
Torry Steed, Sr. Staff Product Manager at SMART Modular, covers the changing shape of memory leading to new categories of CXL form factors. He dives deeper to address EDSFF and AIC variations, mechanical sizes, installation locations, capacity considerations, and power ratings.
Q1 Memory Fabric Forum: Memory Fabric in a Composable SystemMemory Fabric Forum
Eddie McMorrow, Sr. Product Manager at GigaIO, defines composable infrastructure and memory fabrics, then provides and overview of the FabreX memory fabric.
Q1 Memory Fabric Forum: Micron CXL-Compatible Memory ModulesMemory Fabric Forum
Michael Abraham, Director of Product Management at Micron, discusses data center challenges, the memory and storage hierarchy, Micron CZ120 memory modules, database (TPC-H) improvements, AI inferencing improvements, and how to enabling in your company.
Q1 Memory Fabric Forum: Advantages of Optical CXL for Disaggregated Compute ...Memory Fabric Forum
Ron Swartzentruber, Director of Engineering at Lightelligence, explains why optical connectivity is needed for CXL fabrics, and provides an overview of the Photowave line of port expander PCIe cards and active optical cables.
Arvind Jagannath of VMware makes the case for bridging the CPU-Memory imbalance with memory tiering, describes their vision for memory disaggregation, and explains that VMware will support CXL Expanders – Specific Configurations, Memory Tiering to reduce overall TCO, and Memory Accelerators to enable CXL-based use-cases.
MemVerge Field CTO Yong Tian shows what memory expansion costs with an analysis of various server configurations with up to 8TB of tiered DRAM and CXL memory.
In the CXL Forum Theater at SC23 hosted by MemVerge, Lightelligence describes CXL's need for optical connectivity and their portfolio of CXL optical expander cards and cables
In the CXL Forum Theater at SC23 hosted by MemVerge, Samsung described their the architecture and use cases of their hybrid drive that includes DRAM and Flash memory
In the CXL Forum Theater at SC23, MemVerge provides an overview of how to use CXL memory pools to store shared memory objects to eliminate inter-node AI cluster traffic and accelerate performance
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
2. SK hynix CXL Disaggregated Memory
Solution
Jungmin Choi, Memory System Architect, SK hynix
3. Agenda
Motivation
Growing Memory Bandwidth and Capacity Gap
Challenges in Today’s Datacenter
Solution
Niagara: CXL Disaggregated Memory Prototype
Use Cases of CXL Disaggregated Memory
Other HW-assisted Features of Niagara
Next Step
4. Growing Memory Bandwidth and
Capacity Gap
• Increase in core counts requires continued increase in memory bandwidth &
capacity
• The gap between such requirements and platform provisioning capability is
growing
• CXL creates new opportunities beyond physical limitations, and efficient memory
disaggregation is possible
[Memory Bandwidth Requirement] [Memory Capacity Requirement]
5. Challenges in Today’s Datacenter
• Challenge 1 : Memory stranding & data spill
• The memory utilization of each node in a compute cluster varies time to time
• Unused memory in each node can never be utilized by other nodes, which causes memory
stranding and data spill
VM 1
VM 2
VM 3
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Memory
Stranded
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Memory
Spilled
VM 1
VM 2
VM 3
[Memory Stranding] [Data Spill]
Memory underutilization & Waste of memory
costs
Storage swap & Performance
degradation
Two sides of a
coin
6. Challenges in Today’s Datacenter
• Challenge 2 : Data transfer overhead & data duplication
• In a distributed computing system, there is a network-based data transfer overhead between
remote nodes
• Duplication of shared data between nodes increases local memory pressure
Node
App
DRAM
Node
App
DRAM
Node
App
DRAM
Node
App
DRAM
Network
Serialization & Deserialization
Data Duplication
7. Solution: CXL Disaggregated Memory
System
• CXL disaggregated memory system can support memory pooling & sharing
• Memory pooling : Mitigate memory stranding and data spill by sharing memory resources
between nodes
• Memory sharing : Remove data transfer overhead and data duplication by sharing data
between nodes
Node #1
[Memory Pooling]
Allocate CXL memory based on memory usage for
each node
Share data objects based on zero-copy between
nodes
Node #2 Node #3 Node #4
CXL Disaggregated Memory
[Memory Sharing]
Node #1 Node #2 Node #3 Node #4
CXL Disaggregated Memory
Shared
Object
#1 Shared
Object
#2
Shared
Object
#N
8. Niagara: CXL Disaggregated Memory
Prototype
• Niagara is a 4U FPGA based multi-port CXL disaggregated memory prototype
• Up to 4 CXL host servers can be connected, Support up to 4 channels of DDR4 DIMM (1TB)
• Support memory pooling, sharing and other HW-assisted features
[Rack-Scale System with Niagara]
[Niagara Block Diagram]
[Niagara Specification]
CXL
Interface
CXL 2.0, Gen4x8
Up to 4-port
Memory
4CH DDR4 DIMM
Up to 1 TB
Performan
ce
Latency : 600ns
Bandwidth : 11 GB/s
CXL EP CXL EP CXL EP CXL EP
Memor
y
FPGA
CXL RP
CXL
HW-
assisted
Features
Pooled
Memory
Manage
r
CXL RP CXL RP CXL RP
Memory
Memor
y
Memor
y
Node #1 Node #2 Node #3 Node #4
Niagara
Server #1
Server #2
Server #3
Server #4
9. Use Cases of CXL Disaggregated Memory
• Use case 1 : Memory pooling
• Niagara supports Dynamic Capacity Service (DCS), a HW/SW integrated solution, for memory
pooling
• DCS can dynamically allocate/deallocate disaggregated memory resources for each node
without RESET
• Improve memory utilization and performance of a system equipped with CXL disaggregated
memory
Niagara Prototype
Node 1
Node
2
Node 3 Not Used
Node 4
Resizing
Allocate
d
Memory Mgmt. Subsystem
Local DRAM Zone
(Static Size)
Cluster Management Framework
Host VM Manager
OS/Hypervis
or
Virtual
Machine
CXL
Node #2
Node #3
Node #4
Node #1
VM
Local
DRAM
CXL
Memory
Memory Pooling
Daemon
VM
Local
DRAM
CXL
Memory
Memory Pooling
Daemon
CXL Memory
Zone
(Resizable)
VM Scheduler
Memory
*PMM
Mailbox
Secure
Eraser
**MPU #1
Memory
Section
Table
to MPU #1
to MPU #2
to MPU #3
to MPU #4
from Table
Mailbox
MPU #2
from Table
Mailbox
MPU #3
from Table
Mailbox
MPU #4
from Table
Memory
Memory
Memory
Dynamic Allocation Engine
CXL.io
CXL.mem
CXL.io
CXL.mem
CXL.io
CXL.mem
CXL.io
CXL.mem
CXL
IP
CXL
IP
CXL
IP
CXL
IP
* PMM : Pooled Memory
Manager
** MPU : Memory Protection
Unit
10. Use Cases of CXL Disaggregated
Memory
• Evaluation results of memory pooling
• Reduce execution time by mitigating data spill and improve memory utilization of a
system
[Execution Time of CloudSuite
Benchmark]
Spill to Niagara outperforms NVMe by up to 2.5x
(even though Niagara is an FPGA-based
prototype)
Utilization improved by 35% by applying DCS to
Kubernetes
[Memory Utilization on Kubernetes]
0 50 100 150 200 250 300 350
20
10
0
Normalized Execution Time vs Baseline [%]
Workload
Spilled
to
Medium
[%]
No Spill (Baseline) Spill to Niagara Spill to SSD
2.5x improvement
[ Collaboration with
MemVerge ]
Baseline Kubernetes
DCS-enabled
Kubernetes
Worker
#1
Worker
#2
Worker
#1
Worker
#2
# CPU Cores 112 176 112 176
Local Memory
Capacity
62 GB 62 GB 62 GB 62 GB
CXL Memory Capacity 32 GB 32 GB 64 GB (Pooled)
Total Memory
Capacity
94 GB 94 GB
62-126
GB
62-126
GB
Avg. Memory
Utilization
55.7% 75.1%
35% improvement
11. Use Cases of CXL Disaggregated
Memory
• Use case 2 : Memory sharing
• Niagara supports firmware that allows all hosts to access shared data objects in Niagara
memory
• No more object serialization and transfer over network for remote object access
• No more duplicate object copies on different nodes Zero copy
CXL EP CXL EP CXL EP CXL EP
CXL
RP
Pooled
Memory
Manager
CXL
RP
CXL
RP
CXL
RP
Node
#1
Node
#2
Node
#3
Node
#4
Shared Object
Data Write Data Read Data Read Data Read
12. Use Cases of CXL Disaggregated
Memory
• Evaluation results of memory sharing
• Reduce execution time by eliminating network based data transfer overhead
[Execution Time of *Ray Shuffle
Benchmark]
Ray with Niagara outperforms native Ray by up to
5.9x
[Execution Time of Spark Benchmark]
5.9x improvement
*Ray is an open source based distributed computing framework for AI/ML
[ Collaboration with
MemVerge ]
Merge Hash Join outperforms Sort Merge join by
up to 1.8x
0 20 40 60 80 100 120 140
Query 1
Query 2
Query 3
End-to-End Execution Time [sec]
Mege Hash Join
1.8x improvement
Merge Hash Join
0 20 40 60 80 100
25
50
75
100
Latency [sec]
Partitions
Ray with Shared Memory
End-to-End Execution Time
[sec]
13. Other HW-assisted Features of Niagara
• Niagara supports HW-assisted features to CXL disaggregated memory efficiency
• Block Data Management : Copy or move data within CXL pooled memory
• Snapshot : Save and restore data in CXL Pooled Memory to/from storage device
• Memory Failure Prediction : Predict memory Uncorrectable Errors(UEs) by analyzing memory
failure patterns
[Block Data Management] [Snapshot] [Memory Failure Prediction]
CXL RP
Pooled
Memory
Manage
r
CXL RP
Node #1 Node #N
CXL EP CXL EP
CXL Disaggregated Memory
Data
Copy/Mov
e
CXL RP CXL RP
Node #1 Node #N
CXL EP CXL EP
CXL Disaggregated Memory
Data
Save/Restore
Storage
CXL RP CXL RP
Node #1 Node #N
CXL EP CXL EP
CXL Disaggregated Memory
UE prediction
Notify
predicted
UE
Pooled
Memory
Manage
r
Pooled
Memory
Manage
r
14. • Niagara 2.0 will be available by the end of 2023
• Niagara 2.0 is a 2U CXL disaggregated memory prototype which can connect up to 8 CXL
host servers
• Support DCD (Dynamic Capacity Device) feature defined in CXL specification 3.1
• We look forward to an open collaboration with industry partners to enable HW/SW
ecosystem
Next Step
[Niagara 2.0 Prototype] [Server Cluster with Niagara 2.0]
Server Server
Pooled
Memory
Manager
Cloud
Orchestrato
r
DCD Engine
CXL Disaggregated
Memory
Niagara
2.0
15. Niagara Live Demo
• Demonstrate the allocation/deallocation of
memory space in CXL disaggregated memory
based on dynamic changes in memory
requirements of VM servers
• Check out SK hynix booth (#A8) for a live demo
[Niagara Live Demo System]
Niagara
Server #1
Server #2
Server #3
Server #4
[Demo GUI]
