Prince Kumar is an ASIC/PD engineer with over 1 year of experience in physical design. He has skills in floorplanning, placement, routing, timing closure, and power optimization. His experience includes a project at RV VLSI Design Center working on a 40nm design with 34 macros, 40K standard cells, area of 4.2mm2, power budget of 600mW, and IR drop below 55mV. He is interested in digital design, physical design, STA, Verilog, and physical verification. Prince Kumar holds an Advanced Diploma in ASIC Design and a B.Tech in ECE.

1. PRINCE KUMAR
princerana08@gmail.com +917986342793 Bangalore, India
Core Competency
 Proficient in ASIC/PD Flow from Netlist to
GDSII and hands-on experience in one of
the APR tools.
 Workable experience in Floorplan, Power
Plan, Placement, CTS, Routing, Physical
Verification (DRC/ LVS checks).
 Power Plan: to connect all pins of macros
and standard cells to the Power nets without
any floating wire and DRC errors within IR
Drop limit.
 Understanding of basic concepts and terms
related to STA was necessary for accurate
analysis of timing reports.
 A know-how of cell delays, Derate factors,
Setup time and Hold time, MCMM,
OCV/AOCV, PVT, CRPR, Timing
exceptions(false path & multi cycle path).
 Understanding of Primetime STA tool and
timing closure methodologies and
implementing timing ECOs including effect
on congestion/routing/power.
 Understanding of Power grid, UPF, clock
Tree and low power reduction
implementation methods.
 Familiar with scripting languages like TCL,
Perl, Linux Shell scripting.
 Adequate knowledge of Digital Design,
CMOS, Verilog, Shell scripting, C, Python.
Projects
 Worked in Physical Design Domain at RV
VLSI Design Center, Bangalore
(Technology - 40nm, Macro count - 34,
Standard cell count - 40K, Area - 4.2 mm2,
Supply -1.1V, Clock frequency - 1 GHz,
Metal layers - 7, Power Budget - 600 mW,
IR drop < 55 mV).
 Design an Electronic Voting Machine using
Verilog code.
 DRDO :- Data Fusion on Sled Boun
Application.
Area of Interest
 Digital Design, Physical Design, STA,
Verilog, DFT, Physical Verification.
Experience
 One Year Experience in Physical Design as
Graduate Trainee Engineer (RV VLSI
Design Center).
 One Year Experience in IT as Desktop
Support Engineer. (Vayam info solution pvt
ltd).
Tools
Synopsys - ICC2, PrimeTime, Mentor Graphics:
Calibre, Questasim, Modelsim, Xilinx
Soft Skills
Learning Potential, Team Work, Organization,
Flexibility, Responsibility, Multitasking, Work under
Pressure.
Education
Advanced Diploma in ASIC Design (PD)
RV VLSI Design Center, Bangalore
February 2020
B.Tech in ECE
Indus International University Una (HP) , 2016,
CGPA: 9.01
Diploma in ECE
Indus International University Una (HP) , 2016,
CGPA: 7.9
SSLC 2010
Punjab State Education Board Mohali, 2010
70 %
Languages
English, Punjabi, Hindi