1. GAURAV PANWAR
Mobile: +91-8010393009, E-Mail : gaurav11013624@gmail.com, City: Noida
EDUCATIONAL QUALIFICATIONS
Course Institute/Board Passing Year CGPA/Percentage
B.Tech (ECE) Lovely Professional University,
Phagwara
2014 9.06
SSE
(5685961)
Jawahar Navodaya Vidyalaya (CBSE) 2009 78%
HSE
(5196573)
Jawahar Navodaya Vidyalaya (CBSE) 2007 84.6%
TECHNICAL SKILLS
Software/Hardware Languages Verilog, System Verilog, C, C++
Scripting Languages Shell Scripting, TCL, PERL
EDA Tools JOULES, Genus, QuestaSim, Xilinx ISE, ModelSim
Hardware Designing FPGA
Operating System Linux
Area of Interest Digital and Verilog
WORK EXPERIENCE
Product Validation engineer (intern) 1.4 years
Cadence Design Systems, Noida (Sept 2014 – Present)
Project: Joules
Objective: Accurate RTL power estimation
Description: Joules RTL Power Solution can analyze designs of up to 20 million instances
overnight with gate-level accuracy within 15 percent of final power as signed off in the Cadence
Voltus IC Power Integrity Solution. In addition, the Joules RTL Power Solution integrates
seamlessly with the Cadence Palladium emulation platform and the Stratus High-Level
Synthesis (HLS) platform for early system-level power analysis and optimization.
Role:
• Writing Test cases for feature testing for Joules and Genus.
• Involved in Command testing for LibScore, Power analysis, clock tree setup and analysis
and stimulus Interfaces.
• HDL Modelling in Verilog.
• Automation with Perl scripting knowledge.
Familiar with:
• Synthesis benchmarking w.r.t. (TNS, WNS, Area, Power) across number of customer
designs across the release and debugging QOR degradation issues.
• Lec debugging for non-equivalence.

2. TRAINING & PROJECTS
 INDUSTRIAL TRAINING in VLSI Design - DKOP Labs Pvt. Ltd., Noida (Jan ’14 - Cont...)
 Got hands-on experience on topics like System Verilog, Verilog, FPGA, and Linux.
 Worked at Verification of 8 bit ArithmeticProcessor using System Verilog.
 Worked at VLSI architecture for Secure HASH generator using Verilog HDL on Xilinx
Spartan 3E FPGA kit using Chip Scope Pro Analyzer.
 Interfaced PS2 keyboard, VGA and UART with Xilinx Spartan 3E FPGA kit.
 Verilog Coding of Adaptive Traffic Light Controller & implemented on FPGA kit.
 SUMMER TRAINING in VLSI Design - DKOP Labs Pvt. Ltd., Noida (June-July ’13 )
 Got hands-on experience on various circuits of digital design such as combinational and
sequential circuits in different modeling styles in Verilog and their FPGA
implementation.
 Worked on project UART (Universal Asynchronous Receiver and Transmitter) with FIFO
Buffer in Verilog.
 Worked on the project Voting Machine & Vending Machine in Verilog.
 SUMMER TRAINING in CONTROL and INSTRUMENTATION- NTPC Dadri, Ghaziabad
(June-July ’12 )
 Training in Control and Instrumentation in thermal power plant from NTPC where I gained
industrial experience of Measurement and Control of temperature, pressure and water
flow.
 Got hands on Operations and Monitoring of different sensors such as diaphragm, Bellow,
thermocouple, manometer etc. and Protection required in Thermal Power Plant.
 B.Tech Project – Factory security system, Image Display on Graphical LCD and Moving
Character LCD Display using 8051 Microcontroller.
ACHIEVEMENTS & EXTRA CURRICULAR ACTIVITIES
Education  IEEE workshop on COMSOL Multiphysics held at LPU.
Social  Rajaya Puraskar Winner, in National Scouting.
 Merit Certification in Navodaya Vidyalaya Samiti Special National
adventure programme held at NAI Pachmarhi (M.P).
Sports  Participated in National Skating Tour, NAI Pachmarhi (M.P).