1. AJAY SHARMA Contact: 09599445367~ E-Mail: sajay1592@gmail.com
VLSI Design & Development
Fresh, hardworking, detail-oriented team player offering strong communication skills and customer service capabilities that
contribute to company objectives; targeting assignments preferably in IT industry
Profile Summary
 M.Tech. (VLSI Systems) with 10 months of experience; possess knowledge in:
~Digital Design ~Design Reviews ~ RTL Verifications
~Digital Electronics ~VLSI Design and Test Flow ~ Mixed Signal Design
~Memory Characterization ~Low Power RTL Design Characterization ~Standard Cell Characterization
 Familiar with the concepts of Digital Electronics and Verilog/System Verilog/VHDL Programming.
 Sound knowledge of VLSI Designs & RTL Designs, Front-End Design, Static Timing Analysis & Verification
Methodologies and Low Power RTL Simulation and Implementation.
 Capabilities in swiftly ramping up assignments with competent skills and on-time execution
Knowledge Purview
 Preparing specifications with the clients to ensure drawings are as per the specifications of clients
 Devising the complete set of design programs or jobs that are run on data; streamlining the VLSI design and
verification process
 Managing the run of a set of programs when the design process is initiated; rectifying the errors of the failed programs
 Redressing the errors in one or multiple programs as desired and entering new data and controlling the program
execution by the scheduler
Organizational Experience
Since Mar’15 Synopsys, Noida Contractor in VG Group
Role:
 Steering activities related to Low Power Verification of RTL Designs
 Implementing low power techniques using UPF and checking RTL behaviour on VCS
tool for low power constraints
 Managing system development life cycle of project tasks like investigation, analysis,
design, implementation and testing/ debugging
Academic Details
 M.Tech. in VLSI Systems from Shiv Nadar University, Noida in 2015; secured CGPI : 8.9
 B.Tech. in Electronics Engineering from LNMIIT, Jaipur in 2013; secured CGPI : 7.52
Academic Projects
M.Tech Thesis Project:
Title: Designing of a Low-Noise Amplifier (LNA) with Design Consideration on Gain, Low-Offset
and Low Noise
Period: Aug’14 –May ‘15
Technology: 180nm
Description: The objective of the project was to design a Low-Noise Amplifier for neural signal amplification
with the consideration of maximize gain for low input signal in (~µV) range, with minimum
addable noise. The designed amplifier achieves 68dB gain and a high CMRR (~75dB) and very
low output referred noise (~1nVrms).
Title: Performance Comparison between a 4T and 6T SRAM Memory Cell at 65nm Technology
using Cadence Tool
Period: May’14- Aug’14
Technology: 65nm

2. Description: The project represented the simulation of 4T and 6T SRAM cell topologies and their comparative
analysis on the basis of read noise margin (RNM) and write noise margin (WNM).
Title: Design of ATM Machine Algorithm in VHDL using Modelsim Tool
Period: Jan’14- May’14
Description: The project involved writing a synthesizable HDL code (using NC-sim) for the ATM Machine and
generating the net list and SDC file (using RTL compiler).
Technical Skills
 Low Power Verification
 Strong concepts of UPF and RTL Design
 System Verilog/Verilog/VHDL concepts
 PERL Scripting Language
 UNIX based environment
 VCS Tool for RTL and Low Power Verification
 Verdi for Low Power Verification
 Cadence Tool (Virtuoso, RTL Compiler)
 Mentor Graphics (Modelsim)
Personal Details
Date of Birth: 1st May 1992
Permanent Address: B-Block, Vishnu Hill Town, Behind Saraswati Girls School, Ajmer-305001
Languages Known: English & Hindi