1. CHINTAN VARIA (M): 408 242 4505
San Jose, CA – 95126 chintanvaria@hotmail.com
LinkedIn URL : www.linkedin.com/in/chintanvaria
Objective:
Actively looking for Full time opportunity in Electrical Engineering. Specialization in Digital VLSI.
PROFESSIONAL SUMMARY
 Team Leader of testing team for Steel Automation drives and dealt directly with the customers.
 Worked on PLC based automated test operation bench of automation plant for steel automation drives
and medium Voltage drives ranges from 320volts to 11000volts Industrial supply.
 Developed expertise in the testing and engineering of steel automation drives.
EDUCATION
Master of Science: Electrical Engineering May 2015
San Jose State University GPA: 3.3 out of 4.0
Coursework: ASIC CMOS design, Hi Speed Digital Design, FPGA DSP system design, Digital System Design
and Synthesis, Probability, Digital Signal Processing, Adv. Logic Design, Principles of Semiconductor devices.
Bachelors of Engineering: Electronics and Communication July 2011
Gujarat University Ahmedabad, Gujarat
Completed BE with 1
st
class distinction grade with GPA 3.7 out of 4.0
Technical Expertise
Altera Quartus, Xilinx, MATLAB, OrCAD, Proteus, KEIL, Cadence, Synopsys, AutoCAD Electrical and Mechanical,
Enterprise Resource Planning (ERP system) - Microsoft Navision, MS Office
Skills
Verilog, Basic C, C++, Can deal with any enterprise level software, Also good technical writing and speaking skills.
Experience
Engineering/Testing Engineer (Automation & Drives division) February2012 to July2013
Hitachi Hirel Power Electronics Pvt. Ltd. Ahmedabad, Gujarat
 Designed and implemented electrical equipment facilities and systems for commercial and industrial
purposes.
 Worked with lab instruments such as oscilloscope, logic analyzer, data acquisition system for temperature.
 Corresponded with PLC development team for the control system and test facilities for different test operations
of automation drives.
 Reviewed and designed engineering drawings, schematics, logic and circuit modification, PCB layouts, met
specifications as per customer requirements for newly engineered projects and processes.
 worked on creation of Bill of Material (BOM) for new projects and scheduling of different stage of project to
meet time deadline.
 consistently met strict time deadlines to ensure that new products were available for scheduled client’s
releases.
 Experience of official documentation and standardization of product as per engineering standards.
 Performed very well in different challenging situations individual as well as in team.
Trainee Engineer (Internship) January2011 to April2011
Advantek Solutions Ahmedabad, Gujarat
 Implemented hardware design as per standards and software simulation of live industrial project as per
customer requirements. Collaborated with commissioning process at client site.

2. RELEVANT PROJECTS
Subject: MSEE Project proposal – Spring2015 SJSU
Topic: Implementation of Stereo Vision - based on FPGA – A driverless car concept
Implementing the disparity mapping for a stereo vision system on Altera DE1 FPGA development board. In c and
Verilog. Done the interfacing of SD card and VGA port for input and output of the design.
Subject: FPGA system design – Fall2014 SJSU
Topic: Motion vector calculation algorithm
Implemented full-search block matching algorithm in MATLAB and Verilog. SAD (Sum of Absolute Differences)
criterion was used to calculate motion vector for every non-overlapping block in reference frame.
Subject: Hi-speed digital design – Fall2014 SJSU
Topic: Signal Integrity Analysis for SDRAM
Designed and simulated interface between Atmel processor and 133 MHz SDRAM using their IBIS models with
Cadence SigXplorer.
Subject: Digital System Design – Spring2013 SJSU
Topic: Implement and Analyze Performance of Multi-Level Carry Look-ahead Adders
Implemented and analyzed performance of multi-level CLA and RCA, In order to analyze the performance,
basically explored the correlations between the delay, operand sizes (number of bits) and 5 different designs.
Subject: ASIC Design – Spring2013 SJSU
Topic: Barrel Shifter
Used Verilog to design a buffer/barrel shifter for 4-to-7 bit data conversion and synchronized processing of data.
AWARDS AND EXTRA-CURRICULAR ACTIVITIES
 Awarded youngest Engineer in Hitachi group in India to lead the project and underwent training for
Steel automation drive with an expert Japanese team.
 First, position in national level Autonomous Robotics competition held at Nirma University - Feb 2010
 Qualified for the regional final round of ROBOLIGA, India’s biggest National level Autonomous
Robotics competition organized by ETRIX - Feb 2010
 First, position in mechanical robotics event at Vishwakarma Government Engineering Collage - April 2009
 Organized a successful technical event as Event Coordinator at national level collage technical fest – April 09.