1. Aleksandar Popadic
Date of birth: July 26th
, 1988.
Home address: 70K Dragoslava Srejovica Street, Belgrade, Serbia
Cell phone: +381 69 4104114
E-mail: aleksandar.popadic@live.com
SUMMARY
SoC digital design and verification engineer, with 4 years of experience, working for large international
semiconductor companies. Familiar with latest SoC architecture concepts and capable of writing high quality FW
for complex platforms. Have skills for different planning strategies, and experience in both agile and waterfall
development processes. In my personal time I like to explore new technologies, and write high level software for
web and android platforms. Key personal characteristic is the ability to learn new things with exponential
learning curve.
WORKING EXPERIENCE
 2014-still HTEC (INTEL contractor - Imaging and Camera Technologies Group), Belgrade, Serbia
Position: IP and SoC Verification engineer
Projects summary:
SoC power reduction
Appying different power reduction tecniques in order to save dynamic power
Differential data compressor
Random functional IP level verification following OVM methodology
SoC FW verification
Verify and debug FW on SoC level using specific emulation platform
 2011-2014 Elsys EE (Texas Instruments contractor), Belgrade, Serbia
Position: Design and Verification engineer
Projects summary:
General Purpose Timer
HW/FW co-verification of the module integrated in ARM based SoC
Serial wire debug
UVM based verification component for ARM SWD debugging protocol
Elliptic curve cryptography accelerator
Random functional IP level verification following eRM methodology
Ultra high speed physical layer
Digital design of SD-card physical layer
Camera application layer
Digital design of CSI2 and CSI3 sensors compliant application layer
PROFESSIONAL SKILLS
 TECHNOLOGY
Good: C/C++, JAVA, Verilog, SystemVerilog, VHDL, JavaScript, HTML
Familiar: Python, SQL, CSS, Tcl, Perl, SpecmanE, Bash scripting
 METHODOLOGY
Good: SoC design/verification, Project Planning, UVM, FW programming, UML, OOP
Familiar: Web app development, Android programming, Regular Expressions, Games development

2.  TOOLS
IDE: VisualStudio, Eclipse, NetBeans, Cloud9, Blender 3D
EDA: Cadence Incisive Studio, Synopsys DC, VCS and PT-PX, Mentor Veloce, Atrenta Spyglass
Versioning: Git, Clear-Case, DesignSync
 ADDITIONAL
Open source software and licensing
Computer graphic concepts (scene, mesh, camera, materials, etc...)
Familiar with simple web and database server administration
EDUCATION
 2007-2012 FACULTY OF ELECTRICAL ENGINEERING, University of Belgrade, Serbia
Department of computer science and informatics (RTI)
LANGUAGES
 English: professional
 Serbian: native
HOBBIES
 Physical activity and heathy eating
 Cooking
 Music
INDUSTRIAL PROJECTS
 12.2014.- 5.2015. SoC Power reduction
Job: Locating and fixing poorly gated flops in the SoC in order to save dynamic power
Description: Writing power virus tests at SoC level to generate logic activity information. Generate and analyse
power reports to locate power bugs. Analyse issue registers in RTL and propose solution.
Language: C, TCL, VHDL
Methodology: Local and global clock gating techniques
Tools: Synopsys PT-PX, ANSYS PowerArtist, Synopsys VCS compiler, Cadence NCSIM, Git, Exel
 06.2014.- 12.2014. Differential Data Compressor
Job: Random functional IP level verification using SystemVerilog and following OVM methodology
Description : Plannig and designing verification environment (structure, coverage points, tests, reference
model,..). Writing tests and running regressions to cover both functional and code coverage.
Analysing holes in code coverage to achive 100% coverage. Analyse and verify performance of the
compressor.
Language: System Verilog, VHDL, C, C++
Methodology: OVM
Tools: Synopsys VCS compiler, Visual Studio 2012, Git

3.  02.2013.-06.2014. SoC FW verification
Job: Verifying and debugging FW using Veloce emulation platform
Description : Running firmware testcases on Veloce platform. Extract waveform and debug issues caused by
different behavior on real HW versus pure SW simulation. Anlayse specific testcase performance and
generate reports.
Language: C, Python, Bash Scripting, TCL
Methodology: SoC verification using emulation platform
Tools: Mentor Graphics Veloce machine, Cadence IUS, Git
 10.2013.-02.2014. eGPTimer - General Purpose Timer
Job: HW/FW Co-Verification of the module integrated in ARM based SoC
Description : Designing eGPTimer verification component to drive data to external pins. Extend AHB monitor with
eGPTimer specific checkers and write scoreboard with reference model. Write derect C-test to
configure eGPTimer from ARM M0+ core, and SV random tests to stimulate external pins.
Run regression and analyse coverage.
Language: System Verilog, C
Methodology: CDV & vPlan, UVM, ARM (AHB,APB) subsystem
Tools: Cadence Incisive EDA tools, Design Sync
 09.2013.-10.2013. SWD - Serial Wire Debug
Job: UVM verification component for ARM SWD debugging protocol
Description : Design of reusable SWD SystemVerilog component based on UVM methodology. Write set of
Sequences to wrap SWD functionality for easier use on upper layer with comprehensive
documentation.
Language: System Verilog, C
Methodology: CDV & vPlan, UVM, ARM (AHB,APB) subsystem
Tools: Cadence Incisive EDA tools, Design Sync
 12.2012.-08.2013. ECC - Elliptic curve cryptography Accelerator
Job: Random functional IP level verification environment in SpecmanE
Description : Plannig and designing SpecmanE verification environment (coverage points, reference model,..)
Writing tests and running regressions. Coverage tracking using vPlan tool and following coverage
driven methodology.
Language: Specman E, Verilog, Python
Methodology: CDV & vPlan, UVM
Tools: Cadence Incisive EDA tools, Design Sync
 06.2012.-11.2012. UHS2PHY - Ultra High Speed Physical layer
Job: Design of the SD-Card physical layer
Description : Design of SD-Card data layer protocol module with serialization/deserialization capabilities.
Using AFE model for debugging analog side and power up sequence. Implementing DFT IEEE 1500
protocol wrapper. Instantiation of ISO cells and level shifters between different power islands.
Language: VHDL, Verilog
Tools: Cadence Incisive EDA tools, Clear Case, Atrenta Spyglass

4.  09.2011.-05.2012. CAL - Camera application layer
Job: Design of CSI2 and CSI3 sensors compliant application layer
Description : Update CAL module to support both CSI2 and CSI3 protocols. Upgrade pixel processign pipe to
support additional formats. Module GLS debugging.
Language: VHDL
Tools: Cadence Incisive EDA tools, Clear Case, Atrenta Spyglass
ACADEMIC PROJECTS
 06.2011.-07.2011. Online library
Description: Web application
Language: JAVA (JSF), JScript, HTML, CSS, XML
Tools: NetBeans, Apache Tomcat
 12.2010.-01.2011. MicroJAVA compiler
Description: MicroJAVA compiler
Language: JAVA
Tools: JFlex, CUP, NetBeans
 09.2010.-10.2010. CPU simulator
Description: CPU visual simulator with fully functional assembler
Language: JAVA
Tools: Eclipse IDE and Microsoft Visio 2010
 08.2010.-09.2010. P2P file sharing
Description: Distributed system that facilitate files storage and exchange
Language: JAVA
Tools: Eclipse IDE
 06.2010.-07.2010. FAT16
Description: Implementation of the FAT16 file system.
Language: C++
Tools: Microsoft Visual Studio 2008
 07.2009.-08.2009. OS Kernel
Description: Small operating system kernel with support for multi-threading and time sharing
Language: C++ and x386 assembler
Tools: Microsoft Visual Studio 2005 and Borland C/C++ Compiler 3.1
OTHER
 Driving license
More information is available on request!