1. Himanshu Shivhare
Shree Dashtagiri PG
1st
cross madivala Email: himanshushivhare5@gmail.com
Bangalore-560068 Mobile: +918147199258
Statement of Interests
To pursue a career in Research/Design wherein I can use and acquire my knowledge to
contribute for extensive work, organization goals and achieve set targets in the field of
VLSI and to look for and work on such assignments which will nourish my academic
aptitude and behavioral attitude.
Summary of Qualifications
➢ 3.2 Years of working Experience in VLSI Industry
➢ Good Understanding of the ASIC and FPGA design flow
➢ Experience in writing RTL models in Verilog HDL and
Testbenches in System Verilog
➢ Good Understanding with Engineering Change
Order(ECO)
➢ Good knowledge in verification methodologies
➢ Experience in using industry standard EDA tools for the front-end design
and verification
➢ Experience in working on low power Lattice FPGA devices,iCE40, MachXO2
VLSI Domain Skills
HDLs: Verilog
HVL: SystemVerilog
EDA Tool: Lattice Diamond, iCEcube2, Active-HDL, Synplify-Pro,
Modelsim and Xilinx SE
Domain: ASIC/FPGA Design Flow, Digital Design methodologies
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Synthesis, Functional Coverage, Coverage
Driven Verification, Assertion Based Verification
Experience
Bangalore Dec 2012 - Present, Lattice Semiconductor,Bangalore
Educational Qualification
Bachelor of Engineering, Gargi Institute of science and Technology RGPV, Madhya Pradesh,
India
Discipline: Electronics & Communication Engineering
Percentage: 68.8% First Class
Year: 2012
Achievements
➢ Award for Outstanding Contribution to Lattice Core Values in Lattice Semiconductor

2. VLSI Projects
UART – RTL design and verification
HVL: System Verilog
EDA Tools: Modelsim, Questa – Verification Platform and ISE.
➢ Implemented the UART using Verilog HDL independently.
➢ Architected the class based verification environment using System Verilog.
➢ Verified the RTL model using System Verilog.
➢ Generated functional and code coverage for the RTL verification sign-off
Synthesized the design.
Dual Port RAM – verification
HVL: System Verilog
EDA Tools: Modelsim, Questa – Verification Platform and ISE
➢ Implemented the Dual Port Ram using Verilog HDL independently
➢ Architected the class based verification environment using system Verilog
➢ Verified the RTL module using System Verilog
➢ Generated functional and code coverage for the RTL verification sign-off
Inter Integrated Circuit(I2C) Protocol
HDL : Verilog
EDA Tools: ModelSim, Lattice Diamond
Description: The design used with a microprocessor to read the configuration data from a
serial EEPROM that supports an I2
C protocol. I2
C master using 7-bit addresses and providing
random reads cycles only. Implemented the design on FPGA. The DUT is designed using
Verilog and tools used are ModelSim and Xilinx ISE.
➢ Designed the Slave using Verilog
➢ Verified the RTL module using Verilog
Lattice Reference Designs
Worked on many Lattice Reference designs including HDLC controller, BSCAN
implemented on Lattice FPGAs.
SPI Controller Core - Design
HDL: Verilog
HVL: Verilog
EDA Tools: Modelsim, Xilinx ISE
Description: The SPI Controller Core is an interface between wishbone compatible Master
Device and SPI interface Slave device. It supports variable length of transfer word and the
core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data
transfer at both edges of clock. This core can be configured to connect with 32 slaves. The
SPI Clock frequency can be adjusted by configuring desirable value in 32-bit clock divider
register. The SPI Core RTL is technology independent and fully synthesizable.
➢ Designed the module
➢ Verified the RTL module using Verilog
➢ Generated code coverage for the RTL verification sign-off

3. Engineering Final Year Project:
Fractal Image Compression:
HDL: VHDL
EDA Tools: ModelSim, Xilinx-ISE
Description: Image compression using fractal transform is a promising method which is
potentially capable of achieving very high compression ratios. In fractal image compression
the encoding step is computationally expensive. We present a technique that reduces
computational complexity and hence reducing the encoding time. The fast fractal algorithm
is based on self similarity measures and leads to a novel application of the Fast Fourier
Transform based cross-correlation. The whole design has been done using VHDL. Matlab is
used for converting the Image into Matrix form. It gives the coordinates of RGB plane. The
design is synthesized using Xilinx ISE and Simulated using ModelSim. FPGA Implementation
of Cross Correlation has been done.
Additional Skills
Other Tools : Enterprise Wizard(EW)/Agiloft (Management Tool from Agilant) Site
Core.
Declaration
I hereby declare that the above-furnished information is true to the best of my knowledge.
Himanshu Shivhare