This term presentation was submitted as a partial requirement for the course: MSE 507: Advanced micro-fabrication with CAD (TSUPREM4). In this presentation, the fabrication process of 3D FINFET transistor has been presented in accordance with US patent (Patent no. US 7,973,389 B2, assignee: Intel Corporation, Santa Clara, CA, US) using Shallow Trench Isolation (STI) method.

1. 3D TRI-GATE FULLY-DEPLETED
TRANSISTOR FABRICATION
A Z M NOWZESH HASAN
Student ID: 102-37-404
FEB 14, 2017
Louisiana Tech University

2. 2
 Transistor: invention, and evolution.
 2D and 3D transistor comparison.
 3D tri-gate transistor fabrication process
 Advantages of 3D fin FET transistor
 Q&A session

3. In 1947, Bardeen, Brattain, and
Shockley invented the first
(bipolar) transistor – awarded the
1956 Nobel Prize in Physics
The Invention of the Transistor – 1947

4. Advent of 2D Planner MOSFET –
1963 1965
D. KAHNG M. ATALLA
For the next 50+ years, the 2D structure of the MOSFET transistor remains unchanged
1965

5. First 3D “FinFET”: 1991 – 1991

6. 2D/Planner
3D Tri-gate
 Doped Si creates e flow
 Gate controls the stream of flow
 Acts as an ordinary switch
 Key performance objectives:
• High on/off ratio
• High switching speed
 The gate wrapped on the channel
 2D stream replaced by 3D fin
 Acts as an ordinary switch
 Key performance:
• 50% power reduction
• 37% performance increased
3D

7. FABRICATION PROCESS

8. FABRICATION PROCESS
bulk silicon substrate
Si3N4 layer as hard mask layer
Figure 01. Cross-sectional view of a bulk silicon substrate with hard mask layer
formed from silicon nitride (Si3N4).

9. FABRICATION PROCESS
bulk silicon substrate
Si3N4 layer patterned and etched using
dry etch or reactive ion etch (RIE) of
CHF3, CH3F, or CF4.
Figure 02. Hard mask layer patterned and etched.
The patterned hard layer would
be used as a cap to form a fin
structure.

10. FABRICATION PROCESS
Figure 03. The bulk substrate patterned and etched.
Si3N4
Fin structure
bulk silicon substrate
The bulk substrate patterned and
etched using wet etching by
NH4OH or dry etching by HBrCl

11. FABRICATION PROCESS
Figure 04. Shallow trench isolation (STI) deposition around the fin structure.
Si3N4
Shallow Trench Isolation (STI) deposition
around the fin. SiO2 or SiOF may be used by
CVD, PVD or atomic layer deposition (ALD)
STI layer

12. FABRICATION PROCESS
Figure 05. Shallow trench isolation (STI) deposition around the fin structure.
Shallow Trench Isolation (STI) etching
To expose fin structure
Wet etching (HF) or
dry etching (RIE of CHF3, CH3F, or CF4).
STI layer
Bulk layer
Si3N4

13. FABRICATION PROCESS
Figure 06. Protective nitride cap deposition.
STI layer
Bulk layer
Si3N4 Cap
Protective nitride cap deposition
To protect fin from oxidation
Si3N4 using CVD, PVD or ALD
process and wet or dry etching.

14. FABRICATION PROCESS
Figure 07. Thermal oxidation consumes unprotected Si fin.
STI layer
Bulk layer
Part of Si fin turns into silicon oxide
Thermal oxidation consumes
unprotected Si fin.
To isolate top fin under nitride cap.
Wet oxidation 900 ~ 1100 ⁰C 3 hrs.
Si fin under nitride cap protected and
got isolated after oxidation
Si3N4 Cap

15. FABRICATION PROCESS
Figure 08. Nitride cap removal process.
STI layer
Bulk layer
Nitride cap removal.
To expose from isolated Si body.
High selective wet etching using
phosphoric acid.
Isolated Si body

16. FABRICATION PROCESS
Figure 09. Source and drain doping and gate oxide layer deposition.
STI layer
Bulk layer
SD doping & Gate oxide deposition.
To provide dielectric layer.
Dry oxidation 4 ⁰A to 40 ⁰A
Gate oxide layer

17. FABRICATION PROCESS
Figure 10. Metal layer for gate patterning.
STI layer
Bulk layer
Gate patterning
Metal layer deposition.
Metal layer for gate patterning

18. FABRICATION PROCESS
S

19. FABRICATION PROCESS
STI layer
Bulk layer
DS

20. FABRICATION PROCESS
Figure 11. Metal layer for gate patterning.
STI layer
Bulk layer
Tri-Gate transistors can have multiple fins connected together
to increase total drive strength for higher performance

21. Fin
Gate
Gate

22. The “fully depleted” characteristics of
Tri-Gate transistors provide a
steeper sub-threshold slope that
reduces leakage current
Lower threshold
voltage

23. 22 nm Tri-Gate transistors provide improved
performance at high voltage
and an unprecedented performance gain at
low voltage

24. Advan
 A simplification of engineering for isolation
 Lower parasitic capacitance
 Higher power efficiency
 Lower leakage current
 Easy to control isolation oxide layer thickness
 Gate electrode controls the fin from 3 sides
 Inversion layer increased for higher current drive
 Steeper sub-threshold slope (V-th lower)
 Low V-th allows to operate at lower voltage
 Lower power consumption
 High switching speed
 Short channel effect elimination

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