VLSI technology is constantly scaling to smaller feature sizes, known as scaling. There are two main scaling factors - α which scales all linear dimensions except oxide thickness and voltage, and β which scales oxide thickness and voltage. As devices scale, their parameters like gate area, capacitance, resistance, and delay are affected. Constant field scaling keeps the electric field constant, constant voltage keeps voltage constant, and lateral scaling only reduces the gate length. Scaling improves performance and integration density but physical limits restrict how far it can go, and it increases issues like interconnect delay and crosstalk.

1. Scaling
• VLSI technology is constantly evolving towards
smaller line widths
• Reduced feature size generally leads to
– better / faster performance
– More gate / chip
• More accurate description of modern technology
is ULSI (ultra large scale integration

2. Scaling Factors
• In our discussions we will consider 2 scaling
factors, α and β
• 1/ β is the scaling factor for VDD and oxide
thickness D
• 1/ α is scaling factor for all other linear
dimensions
• We will assume electric field is kept constant

3. Scaling Factors for Device Parameters
Simple derivations showing the effects of scaling are derived in Pucknell
and Eshraghian pages 125 - 129
It is important that you understand how the following parameters are
effected by scaling.
• Gate Area
• Gate Capacitance per unit area
• Gate Capacitance
• Charge in Channel
• Channel Resistance
• Transistor Delay
• Maximum Operating Frequency
• Transistor Current
• Switching Energy
• Power Dissipation Per Gate (Static and Dynamic)
• Power Dissipation Per Unit Area
• Power - Speed Product

4. MOSFET Scaling
❑SCALING - refers to ordered reduction in dimensions of the
MOSFET and other VLSI features
❑Reduce Size of VLSI chips.
❑Change operational characteristics of MOSFETs and parasitic.
❑Physical limits restrict degree of scaling that can be achieved.
❑ Constant Field Scaling
❑ Constant Voltage Scaling
❑ Lateral Scaling

5. Constant Field Scaling
❑ The electric field E is kept constant, and the scaled device is
obtained by applying a dimensionless scale-factor α (such
that E is unchanged):
❑ all dimensions, including those vertical to the
surface (1/α)
❑ device voltages (1/α)
❑ the concentration densities (α).

6. Constant Voltage Scaling
❑ Vdd is kept constant.
❑ All dimensions, including those vertical to the surface
are scaled.
❑ Concentration densities are scaled.

7. Lateral Scaling
❑ Only the gate length is scaled L = 1/α (gate-shrink).
❑ Year Feature Size(μm)
1980 5.0
1983 3.5
1985 2.5
1987 1.75
1989 1.25
1991 1.0
1993 0.8
1995 0.6

8. PARAMETER SCALING MODEL
Lateral
Length (L)
Width (W)
1/α
1
1 1
1/α 1
Supply Voltage (V)
Gate Oxide thickness (tox)
Junction depth (Xj) 1/α 1
1/α α
α α
α 1
Constant Constant
Field Voltage
1/α 1/α
1/α 1/α
1/α
1/α
1/α
α
1/α2
1
1/α 1/α
Current (I)
Power Dissipation (P)
Electric Field
Load Capacitance (C)
Gate Delay (T) 1/α
1/α
1/α2 1/α2

9. Scaling of Interconnects
• Resistance of track R ~ L / wt
• R (scaled) ~ (L / α) / ( (w/ α )* (t
/α))
• R(scaled) = αR
• therefore resistance increases with
scaling
t w L
A
B

10. Scaling - Time Constant
• Time constant of track connected to gate,
• T = R * Cg
• T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg
• Let β = α, therefore T is unscaled!
• Therefore delays in tracks don’t reduce with scaling
• Therefore as tracks get proportionately larger, effect gets
worse
• Cross talk between connections gets worse because of reduced
spacing

11. Scaling of MOS and circuit parameter