VLSI circuit design involves a standardized process of scaling down transistor sizes over multiple generations. This document outlines key aspects of the VLSI design process including: 1) MOSFET layers, stick diagrams, design rules and layout diagrams are used to plan and design VLSI circuits before fabrication. 2) Stick diagrams provide a simplified cartoon view of layouts showing relative placement of transistors without exact sizes or spacings. 3) Scaling down transistor dimensions according to standard scaling factors allows more transistors to fit on chips leading to improved performance over generations, but also introduces challenges like increased interconnect delays and crosstalk.

1. UNIT-3
VLSI CIRCUIT DESIGN
PROCESS

2. CONTENTS:
➢ VLSI design flow
➢ MOS layers
➢ Stick Diagrams
➢ Design Rules and Layout diagrams
➢ 2µm Design Rules
➢ Layout Diagrams for Inverter, Logic gates
➢ Scaling of MOS

3. VLSI Design Flow:

5. MOS Layers :
There are 4 layers
• N-diffusion
• P-diffusion
• Poly Si
• Metal

6. Stick Diagrams :
➢ A stick diagram is a cartoon of a layout.
➢ Does show all components/ vias (except possibly tub
ties), relative placement.
➢ Does not show exact placement, transistor sizes, wire
lengths, wire widths, tub boundaries

7. • Key idea: "Stick figure cartoon" of a layout
• Useful for planning layout
o relative placement of transistors
o assignment of signals to layers
o connections between cells
o cell hierarchy

8. Rules for Drawing Stick Diagrams :
• Metal 1
• Poly Si
• N-diffusion
• P-diffusion
Rule 1:
• When two or more sticks of the same type cross or
touch other that represents electrical contact.

9. Rule 2:
• When two or more sticks of different type cross or touch
other there is no electrical contact.(if contact is needed
show explicitly)

10. Rule 3: When a poly crosses diffusion it represents
MOSFET. If contact is shown it is not transistor.
nMOSFET pMOSFET nMOSFET
(Depletion Mode)

11. nMOS Design Style:
Step 1:Draw metal VDD and GND rails in parallel leaving
sufficient space for circuit components between them.
VDD
GND
Step 2: Thinox (green) paths are drawn between
rails for inverter & inverter logic.
Vin
VOUT
VDD
GND

12. STICK DIAGRAMS
P- Diffusion
n- Diffusion
Poly silicon
Metal 1
Contact cut
N implant
Demarcation line
Substrate contact
PMOS Enhancement Transistor
NMOS Enhancement Transistor
NMOS Depletion transistor
NPN Bipolar Transistor
Buried Contact

13. Step 3: Connect poly over thinox wherever transistor
required.

14. Step 4: Connect metal wherever is required and create
contact for connection.
Vout
Vin
Vin
VOUT
VDD
GND
Depletion
mode nMOS

15. VDD
GND
NMOS INVERTER STICK DIAGRAM
D
A
B
S
D

16. VDD
GND
CMOS INVERTER STICK DIAGRAM
FIG 1 Supply rails

17. VDD
GND
PMOS
NMOS
S
S
D
D
CMOS INVERTER STICK DIAGRAM
Fig 2 Drawing Pmos and Nmos Transistors between Supply rails

18. VDD
GND
PMOS
NMOS
A
S
S
D
D
CMOS INVERTER STICK DIAGRAM
Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input
With same gate poly silicon metal

19. VDD
GND
PMOS
NMOS
A
D
S
S D
CMOS INVERTER STICK DIAGRAM
Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1

20. VDD
GND
PMOS
NMOS
D
A
S
S D
B
CMOS INVERTER STICK DIAGRAM
Fig 5 Take the output with the poly silicon metal

21. VDD
GND
PMOS
NMOS
D
A
S
S D
B
CMOS INVERTER STICK DIAGRAM
Fig 6 Connect the source of Pmos to VDD and Nmos to GND

22. VDD
GND
PMOS
NMOS
D
A
S
S D
B
CONTAC
T
CMOS INVERTER STICK DIAGRAM
Fig 7 Connect the contact cuts where the different metals are connected

23. VDD
GND
PMOS
NMOS
D
A
S
S D
B
CONTAC
T
CMOS INVERTER STICK DIAGRAM
Fig 8 Final CMOS Inverter
Substrate contact

24. VDD
GND
CMOS NAND GATE STICK DIAGRAM
FIG 9 Supply rails

25. VDD
GND
CMOS NAND GATE STICK DIAGRAM
Fig 10 Drawing P and N Diffusion between Supply rails

26. VDD
GND
S
S
S
D
D
D
D
S
A B
C
CMOS NAND GATE STICK DIAGRAM
Fig 11 Drawing the poly silicon for two different inputs and
identify the source and drain

27. VDD
GND
S
S
S
D
D
D
D
S
A B
C
CMOS NAND GATE STICK DIAGRAM
Fig 12 Connect the source of Pmos to VDD and Nmos to GND and
subtrate contacts of both

28. VDD
GND
S
S
S
D
D
D
D
S
A B
C
CMOS NAND GATE STICK DIAGRAM
Fig 13 Draw the output connections

29. VDD
GND
S
S
S
D
D
D
D
S
A B
C
CMOS NAND GATE STICK DIAGRAM
Fig 14 Connect the contact cuts where the different metals are connected

30. LAYOUT

31. 2λ
2λ
1λ
2λ
3λ
P diffusion N diffusion
P diffusion
P diffusion N diffusion
P diffusion
METAL 1
METAL 1
4λ
4λ
3λ

32. 2λ
4λ
4λ
1λ 2λ 4λ
4λ
1λ
2λ
3λ

33. 2λ
2λ
2λ
2λ
2λ
2λ
2λ
2λ
2λ
2λ
6λ x 6λ
2λ
2λ
2λ
2λ
2λ
NMOS
ENHANCEMENT
PMOS
ENHANCEMENT
NMOS DEPLETION

34. LAMBDA BSED RULES

44. Scaling
• VLSI technology is constantly evolving towards
smaller line widths
• Reduced feature size generally leads to
– better / faster performance
– More gate / chip
• More accurate description of modern technology
is ULSI (ultra large scale integration

45. Scaling Factors
• In our discussions we will consider 2 scaling
factors, α and β
• 1/ β is the scaling factor for VDD and oxide
thickness D
• 1/ α is scaling factor for all other linear
dimensions
• We will assume electric field is kept constant

46. Scaling Factors for Device Parameters
Simple derivations showing the effects of scaling are derived in Pucknell
and Eshraghian pages 125 - 129
It is important that you understand how the following parameters are
effected by scaling.
• Gate Area
• Gate Capacitance per unit area
• Gate Capacitance
• Charge in Channel
• Channel Resistance
• Transistor Delay
• Maximum Operating Frequency
• Transistor Current
• Switching Energy
• Power Dissipation Per Gate (Static and Dynamic)
• Power Dissipation Per Unit Area
• Power - Speed Product

47. MOSFET Scaling
❑ Constant Field Scaling
❑ Constant Voltage Scaling
❑ Lateral Scaling
❑SCALING - refers to ordered reduction in dimensions of the
MOSFET and other VLSI features
❑Reduce Size of VLSI chips.
❑Change operational characteristics of MOSFETs and parasitic.
❑Physical limits restrict degree of scaling that can be achieved.

48. Constant Field Scaling
❑ The electric field E is kept constant, and the scaled device is
obtained by applying a dimensionless scale-factor α (such
that E is unchanged):
❑ all dimensions, including those vertical to the
surface (1/α)
❑ device voltages (1/α)
❑ the concentration densities (α).

49. Constant Voltage Scaling
❑ Vdd is kept constant.
❑ All dimensions, including those vertical to the surface
are scaled.
❑ Concentration densities are scaled.

50. Lateral Scaling
❑ Only the gate length is scaled L = 1/α (gate-shrink).
❑ Year Feature Size(μm)
1980 5.0
1983 3.5
1985 2.5
1987 1.75
1989 1.25
1991 1.0
1993 0.8
1995 0.6

51. PARAMETER SCALING MODEL
Constant Constant Lateral
Field Voltage
Length (L) 1/α 1/α
1/α
Width (W) 1/α 1/α
1
Supply Voltage (V) 1/α 1 1
Gate Oxide thickness (tox) 1/α 1/α
1
Junction depth (Xj) 1/α 1/α 1
Current (I) 1/α α α
Power Dissipation (P) 1/α2 α α
Electric Field 1 α 1
Load Capacitance (C) 1/α 1/α

52. Scaling of Interconnects
• Resistance of track R ~ L / wt
• R (scaled) ~ (L / α) / ( (w/ α )* (t
/α))
• R(scaled) = αR
• therefore resistance increases with
scaling
t w L
A
B

53. Scaling - Time Constant
• Time constant of track connected to gate,
• T = R * Cg
• T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg
• Let β = α, therefore T is unscaled!
• Therefore delays in tracks don’t reduce with scaling
• Therefore as tracks get proportionately larger, effect gets
worse
• Cross talk between connections gets worse because of reduced
spacing

54. Scaling of MOS and circuit parameter