This presentation discusses MOSFET scaling and its challenges. It begins by covering Moore's Law, which states that the number of transistors on a chip doubles every 18 months. As sizes shrink due to scaling, short channel effects like drain-induced barrier lowering and hot carrier effects emerge. The presentation covers two types of scaling: constant field scaling, which keeps electric fields constant but increases power density; and constant voltage scaling, which is preferred as it avoids increased power density but reduces threshold voltage. Narrow width effects also occur when channel widths shrink and depletion regions overlap. Overall, the presentation provides an overview of MOSFET scaling techniques and the short channel effects that emerge as sizes shrink.

1. PRESENTATION
ON
Scaling Of MOS
Submitted by :
Raviraj Kour

2. Contents
Moore’s Law
Why Scaling?
Types of Scaling
Short channel Effects
Narrow Width Effects
Queries
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Moore’s Law[1]
 No. of transistors on a chip doubled every 18 to 24 months.
Semiconductor technology will double its effectiveness every 18 months.
Fig. 1 : No. of transistors with years

4. Fig. 2 : End of Moore’s Law
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5. Fig. 3 : Technology Evolution (1997 data)
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6. Why Scaling?[2]
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 Design of high density chips in MOS VLSI technology requires:
 High packing density of MOSFETS
 Small transistor size
 This reduction of size is k/a Scaling.
 S>1 has been introduced leading to reduction of area by a factor S².
Disadvantage : Electric fields within the Gate Oxide grow larger.

7. Statistics[3]
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Fig. 4 : Data showing no. of transistors on processors of Intel Corporation
with Years

8. Let’s Start
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Fig. 5 : MOSFET Scaling by a factor S

9. Types of Scaling
1. Constant field scaling or full scaling :
 Magnitude of internal electric fields is kept constant.
 Only lateral dimensions are changed.
 Threshold voltage is also effected.
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Fig. 6: Full – Scaling of MOSFET

10. Consequences of Constant Field Scaling :
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Fig. 7 : Change in parameters due to full scaling

11. Most significant reduction :
Power dissipation is reduced by a factor of S² as P´= P/S²
 Power density remains unchanged.
 Gate oxide capacitance is scaled down as Cg´ = Cg/S
 Overall performance improvement.
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12. 2. Constant Voltage Scaling :
More preferred.
 All dimensions are scaled down except power supply and terminal voltages.
Fig. 8 : Parameters effected due to Constant Voltage Scaling
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13. Cons of Constant Voltage Scaling :
Increase in drain current density and power density by a factor of
S³ adversely effecting device reliability.
Causes problems like :
 Electro Migration
 Hot Carrier Degradation
 Gate Oxide Breakdown
 Electrical Over-stress
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 When channel length Leff approx. equals source and junction depth xj.
 Why Short Channel MOS , even if it has degraded performance ?
 Threshold voltage is less. Why ?
Effects :
 Drain- Induced Barrier Lowering
 Surface Scattering
 Velocity Saturation
 Impact Ionization
 Hot Carrier Effect
Short Channel Effects[4]

15. Fig. 9: Simplified geometry of MOSFET channel region
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16.  Potential barrier is controlled by both VGS and VDS.
 If drain voltage increases , barrier in the channel decreases , leading to DIBL.
 Allows electron flow between S and D even at VGS < VTO .
A. Drain- Induced Barrier Lowering (DIBL)[5]
Fig. 10 : As channel length decreases, the barrier φB to be surmounted by an electron,
from the source on its way to the drain reduces.
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B. Surface Scattering
 Due to SCE , electric field increases and mobility becomes field dependent.
 Surface scattering occurs.
Average surface mobility decreases.
Fig. 11: Pictorial representation of Surface Scattering[6]

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C. Velocity Saturation
 Velocity of charge carries Vs Electric Field.
 Three regions.
 Reduces current in Short Channel MOSFET.
 Formula :

19. Fig. 14 : Drift Velocity Vs Electric Field
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D. Impact Ionisation[7]
 Due to high electric field which causes high velocity of electrons.
 Generates Electron - Hole pairs.
Fig. 15 : Impact Ionization

21. E. Hot Carrier Effects
 When electrons or holes gain sufficiently large energies to
overcome barrier and get trapped in oxide layer.
 Permanently changes MOSFET switching characteristics.
 Adversely effects reliability.
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Fig. 16 : Hot Electron Currents

22. Narrow Channel Effects[8]
 MOS having channel widths (W) approx. equals depletion region
thickness (xdm) is known as Narrow – Channel MOS.
 Here , Vto (narrow channel) = Vto + ΔVto (most significant)
 Overlapping of Gate Oxide and FOX.
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Fig. 17 : Cross – sectional view of a narrow channel MOSFET

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25. References
[1] lect15-scaling.ppt
[2] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , pg. no. 115 ,
TATA MCGRAW – HILL EDITION
[3] www.intel.com/research/silicon/mooreslaw.htm
[4] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , pg. no. 119 ,
TATA MCGRAW – HILL EDITION
[5] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , pg. no. 127 ,
TATA MCGRAW – HILL EDITION
[6] EE327 Lec 30a - Surface scattering
[7] Introduction to VLSI design (EECS 467) Project Short-Channel Effects in MOSFETs
December 11th, 2000 Fabio D’Agostino Daniele Quercia pdf , pg. no. 3.
[8] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , page no. 125 ,
TATA MCGRAW – HILL EDITION
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