This document contains a list of interview questions related to VLSI design and Verilog. There are 77 questions related to VLSI topics such as setup and hold time, race conditions, critical paths, FPGA vs ASIC, clock domain crossing, LUTs, mux implementation, constraints, sensitivity lists, testing vs verification, latches vs flip-flops, logic types, frequency division, flip-flop designs, counter designs, number representations, hazard avoidance, CMOS basics, propagation delay, static and dynamic hazards, logic design from state diagrams, and more. It also contains 47 questions related to Verilog topics such as synchronous vs asynchronous reset, modeling styles, procedural blocks, monitoring tasks, default values, generate

1. Dr. H P Koringa
Interview Questions for VLSI Job

2. VLSI Questions
1. What is setup and hold time
2. What is race around condition
3. What is set and hold time violation
4. Difference between RAM and FIFO
5. What is critical path
6. What is false path
7. What is metastability in logic design
8. What is meaning of GLITCH and JITTER
9. What is SOC
10. Advantages of FPGA over ASIC

3. VLSI Questions
11. What is CDC (clock domain crossing)
12. What is LUT in FPGA
13. How 2:1 mux implemented in FPGA
14. Use of PARAMETER in verilog
15. Constraints in VLSI design (time, area and power)
16. Importance of sensitivity list in HDL
17. Testing vs verification
18. Transistor vs FET
19. Difference between latch and flip-flop
20. Combination vs sequential logic
21. Moore vs mealy
22. Draw frequency divider (by 2) using D FF

4. VLSI Questions
23. Design T FF using D FF
24. Design counter using D FF
25. Design mod counter using D FF
26. Types of counter
27. What is johnson counter and its use
28. 2’s complement and its use
29. Draw AND, OR, NAND, XOR using MUX
30. Race around condition in JK flip-flop
31. CMOS basic
32. What is propagation delay

5. VLSI Questions
33. What is the static and dynamic hazard in logic
design
34. Draw a logic for given task
35. CPLD basic (PLA, PAL)
36. Signed and unsigned number
37. Design 4:1 using 2:1 mux
38. Design adder using MUX
39. Draw FSM diagram for up and down counter
40. What is clock skew
41. Difference between EEPROM and FLASH
42. Synchronous counter vs asynchronous counter

6. VLSI Questions
43. FSM for sequence detector for overlapping and non
overlapping condition
44. Draw parity generator
45. Draw circuit for random generator
46. How the frequency of the logic can be increase
47. How to avoid set up and hold time violation
48. What is SLACK in digital design
49. What is Static timing analysis
50. Difference between NOT and BUFFER
51. Draw logic circuit from state diagram
52. FSM for given sequence detector
53. Draw output waveform for given logic circuit having
different delay of logic gates.

7. VLSI Questions
54. Advantage of CMOS implementation
55. What is strong and weak logic
56. Why NAND based implementation is preferred
compare to NOR based in CMOS
57. What is substract bias effect
58. How to avoid race around condition
59. What is semi and full custom design

8. Verilog Questions
1. Difference between synchronous and asynchronous
RESET
2. Difference between inter and intra assignment delay
3. What is Gate delay, wire delay, transport delay,
inertial delay, contamination delay
4. Why delay are not synthesizable
5. What is synthesis and what are constraints
6. Verilog Vs RTL code
7. What is RTL code
8. VLSI Design flow
9. ASIC design flow
10. FPGA Design flow

9. Verilog Questions
1. What is testbench
2. What are verilog construct that are not
synthesizable
3. Where not synthesizable constructs are used
4. What is FPGA and why it used
5. Different FPGA board
6. Difference between ASIC and FPGA
7. Difference between DSP and FPGA implementation
8. What is NETLIST
9. What is difference between technology dependent
and technology independent design
10. What is an IC
11. Difference between TASK and FUNCTION

10. Verilog Questions
1. Difference between behavioral and data flow
modelling
2. What is procedural block
3. Difference between ALWAYS and INITIAL
4. Difference between $monitor and $display
5. Difference between $finish and $stop
6. When to use CASE and IF-ELSE
7. What is an IP
8. Difference between wire and reg
9. Difference between & and &&
10. Diffrence between == and ===

11. Verilog Questions
1. Default value of reg and wire
2. Difference between VECTOR and ARRAY
3. What is ZERO delay in verilog
4. Case vs casex vs casez
5. Use of repeat in verilog
6. Use of forever in verilog
7. Difference between repeat and forever
8. Generate clock of 10ns using loop
9. Types of ASIC
10. Difference between function and formal
verification

12. Verilog Questions
1. Generate clock havinf 20ns and 25% duty cycle
2. What is clock gating
3. What is clock skew
4. What is FSM
5. Difference between mealy and moore FSM

13. Wish you all the
best