This document contains eight questions related to digital integrated circuits and applications. The questions cover topics such as CMOS and TTL gates, VHDL programming, counters, decoders, arithmetic circuits, memories and programmable logic devices. Students are instructed to answer any five of the eight questions, which can include circuit design problems, writing VHDL code, explaining concepts, and performing calculations. The exam is worth a total of 80 marks and is aimed at testing knowledge of digital logic design and implementation using integrated circuits.
Fault Tolerant Parallel Filters Based On Bch CodesIJERA Editor
Digital filters are used in signal processing and communication systems. In some cases, the reliability of those
systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that
exploit the filters’ structure and properties to achieve fault tolerance have been proposed. As technology scales,
it enables more complex systems that incorporate many filters. In those complex systems, it is common that
some of the filters operate in parallel, for example, by applying the same filter to different input signals.
Recently, a simple technique that exploits the presence of parallel filters to achieve multiple fault tolerance has
been presented. In this brief, that idea is generalized to show that parallel filters can be protected using Bose–
Chaudhuri–Hocquenghem codes (BCH) in which each filter is the equivalent of a bit in a traditional ECC. This
new scheme allows more efficient protection when the number of parallel filters is large.
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...IJECEIAES
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
Fault Tolerant Parallel Filters Based On Bch CodesIJERA Editor
Digital filters are used in signal processing and communication systems. In some cases, the reliability of those
systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that
exploit the filters’ structure and properties to achieve fault tolerance have been proposed. As technology scales,
it enables more complex systems that incorporate many filters. In those complex systems, it is common that
some of the filters operate in parallel, for example, by applying the same filter to different input signals.
Recently, a simple technique that exploits the presence of parallel filters to achieve multiple fault tolerance has
been presented. In this brief, that idea is generalized to show that parallel filters can be protected using Bose–
Chaudhuri–Hocquenghem codes (BCH) in which each filter is the equivalent of a bit in a traditional ECC. This
new scheme allows more efficient protection when the number of parallel filters is large.
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...IJECEIAES
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Cryptography is the combination of Mathematics and Computer science. Cryptography is used for encryption and decryption of data using mathematics. Cryptography transit the information in an illegible manner such that only intended recipient will be able to decrypt the information
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Implementation of Energy Efficient Scalar Point Multiplication Techniques for...idescitation
Elliptic curve cryptography (ECC) is mainly an
alternative to traditional public-key cryptosystems (PKCs),
such as RSA, due to its smaller key size with same security
level for resource-constrained networks. The computational
efficiency of ECC depends on the scalar point multiplication,
which consists of modular point addition and point doubling
operations. The paper emphasizes on point multiplication
techniques such as Binary, NAF, w-NAF and different
coordinate systems like Affine and Projective (Standard
Projective, Jacobian and Mixed) for point addition and doubling
operations. These operations are compared based on execution
time. The results given here are for general purpose processor
with 1:73 GH z frequency. The implementation is done over
NIST-recommended prime fields 192/224/256/384/521.
This paper presents a design and implementation of FPGA based Bose, Chaudhuri and Hocquenghem (BCH) codes for wireless communication applications. The codes are written in VHDL (Very High Speed Hardware Description Language). Here BCH decoder (15, 5, and 3) is implemented and discussed. And decoder uses serial input and serial output architecture. BCH code forms a large class of powerful random error correcting cyclic codes. BCH operates over algebraic structure called finite fields and they are binary multiple error correcting codes. BCH decoder is implemented by syndrome calculation circuit, the BMA (Berlekamp-Massey algorithm) and Chien search circuit. The codecs are implemented over cyclone FPGA device.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Cryptography is the combination of Mathematics and Computer science. Cryptography is used for encryption and decryption of data using mathematics. Cryptography transit the information in an illegible manner such that only intended recipient will be able to decrypt the information
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Implementation of Energy Efficient Scalar Point Multiplication Techniques for...idescitation
Elliptic curve cryptography (ECC) is mainly an
alternative to traditional public-key cryptosystems (PKCs),
such as RSA, due to its smaller key size with same security
level for resource-constrained networks. The computational
efficiency of ECC depends on the scalar point multiplication,
which consists of modular point addition and point doubling
operations. The paper emphasizes on point multiplication
techniques such as Binary, NAF, w-NAF and different
coordinate systems like Affine and Projective (Standard
Projective, Jacobian and Mixed) for point addition and doubling
operations. These operations are compared based on execution
time. The results given here are for general purpose processor
with 1:73 GH z frequency. The implementation is done over
NIST-recommended prime fields 192/224/256/384/521.
This paper presents a design and implementation of FPGA based Bose, Chaudhuri and Hocquenghem (BCH) codes for wireless communication applications. The codes are written in VHDL (Very High Speed Hardware Description Language). Here BCH decoder (15, 5, and 3) is implemented and discussed. And decoder uses serial input and serial output architecture. BCH code forms a large class of powerful random error correcting cyclic codes. BCH operates over algebraic structure called finite fields and they are binary multiple error correcting codes. BCH decoder is implemented by syndrome calculation circuit, the BMA (Berlekamp-Massey algorithm) and Chien search circuit. The codecs are implemented over cyclone FPGA device.
Keynote (Mike Muller) - Is There Anything New in Heterogeneous Computing - by...AMD Developer Central
Keynote presentation, Is There Anything New in Heterogeneous Computing, by Mike Muller, Chief Technology Officer, ARM, at the AMD Developer Summit (APU13), Nov. 11-13, 2013.
Chemical Technology Jntu Model Paper{Www.Studentyogi.Com}
Digital Ic Applications Jntu Model Paper{Www.Studentyogi.Com}
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Code No: R05310402
Set No. 1
III B.Tech I Semester Regular Examinations, November 2007
DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) What are the parameters that are necessary to de ne the electrical charac-
teristics of CMOS circuits? Mention the typical values of a CMOS NAND
gate.
(b) Design a CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and
function table. [8+8]
2. (a) Mention the DC noise margin levels of ECL 10K family.
(b) A single pull-up resistor to +5V is used to provide a constant-1 logic source
to 15 di erent 74LS00 inputs. What is the maximum value of this resistor?
How much high state DC noise margin can be provided in this case? [6+10]
3. (a) Write a VHDL Entity and Architecture for a 3-bit synchronous counter using
Flip-Flops.
(b) Explain the use of Packages. Give the syntax and structure of a package in
VHDL. [8+8]
4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural
VHDL program for the same. [16]
5. Design a 10 to 4 enco der with inputs 1- out of ?10 co de and outputs in BCD?
Provide the data ow style VHDL program? [16]
6. Write VHDL program for 1-bit comparator circuit with the input bits and equal,
grater than and less than inputs from the previous stage and the outputs contain
equal, greater than and less than conditions. Using this entity write VHDL program
for 16-bit comparator using data ow style. Do not use any additional logic for this
purpose. [16]
7. (a) Di erentiate between ripple counter and synchronous counter? Design a 4-bit
counter in both modes and estimate the propagation delay.
(b) Design a modulo-88 counter using 74X163 Ics. [8+8]
8. (a) Explain the necessity of two-dimensional deco ding mechanism in memories.
Draw MOS transistor memory cell in ROM and explain the operation.
(b) Determine the ROM size needed to realize the logic function performed by
74×153 and 74×139. [8+8]
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Code No: R05310402
Set No. 2
III B.Tech I Semester Regular Examinations, November 2007
DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) Explain how to estimate sinking current for low output and sourcing current
for high output of CMOS gate.
(b) Analyze the fall time of CMOS inverter output with L = 100 L = 2 5 L =
10 . Assume L as stable state voltage. [8+8]
2. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three
parts with the help of functional operation.
(b) Explain sinking current and sourcing current of TTL output. Which of the
above parameters decide the fan-out and how? [8+8]
3. (a) Write a VHDL Entity and Architecture for the following function?
F(x) = a b c
Also draw the relevant logic diagram.
(b) Explain the use of Packages Give the syntax and structure of a package in
VHDL [8+8]
4. Design the logic circuit and write a data- ow style VHDL program for the following
functions.
(a) ( ) = SA,B,C,D (0 2 5 7 8 10 13 15) + (1 6 11)
(b) ( ) = A,B,C,D (1 4 5 7 9 11 12 13 15))
[8+8]
5. With the help of logic diagram explain 74×157 multiplexer? Write the data ow
style VHDL program for this IC? [16]
6. Design a 24-bit comparator circuit using 74×682 ICs and discuss the functionality
of the circuit. Also implement VHDL source co de in data ow style. [16]
7. (a) Distinguish between latch and ip- op. Show the logic diagram for both.
Explain the operation with the help of function table.
(b) Design a Mo dulo-12 ripple counter using 74×74? Write a VHDL program for
this logic using data ow style. [8+8]
8. (a) Discuss how PROM, EPROM and EEPROM technologies di er from each
other.
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Code No: R05310402
Set No. 2
(b) With the help of timing waveforms, explain read and write operations of
SRAM. [8+8]
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Code No: R05310402
Set No. 3
III B.Tech I Semester Regular Examinations, November 2007
DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) Design CMOS transistor circuit for 3-input AND gate. With the help of
function table explain the operation of the circuit diagram.
(b) Design a CMOS transistor circuit that has the functional behavior as
( ) = (a + b) (b + c)(a + c)
Also draw the relevant circuit diagrams. [8+8]
2. (a) Explain the following terms with reference to TTL gate.
i. Voltage levels for logic ‘1’ & logic ‘0’
ii. DC Noise margin
iii. Low-state unit load
iv. High-state fan-out
(b) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation
with the help of function table. [8+8]
3. Explain with an example the syntax and the function of the following VHDL state-
ments.
(a) Process statement
(b) If, else and elseif statements
(c) Case statement
(d) Lo op statement [4×4=16]
4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural
VHDL program for the same. [16]
5. (a) It is necessary to identify the position of mechanical disk, when rotates with
a step of 450. Give the necessary encoding mechanism and draw the logic
circuit?
(b) Using two 74×138 deco ders design a 4 to 16 decoder. [16]
6. (a) Write a VHDL program for the circuit that counts number of Ones in a 16-bit
register using structural style of modeling.
(b) Design a 4×4 combinational multiplier and the write the necessary VHDL
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Code No: R05310402
Set No. 3
7. Show the logic diagram of 74×175 IC and write VHDL program for this IC in data
ow style. Using this entity develop the program for 16-bit register and show the
corresponding circuit also explain how the register is cleared? [16]
8. (a) Draw the basic cell structure of Dynamic RAM. What is the necessity of
refresh cycle? Explain the timing requirements of refresh operation.
(b) Discuss in detail ROM access mechanism with the help of timing waveforms.
[8+8]
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Code No: R05310402
Set No. 4
III B.Tech I Semester Regular Examinations, November 2007
DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) Design CMOS transistor circuit for 3-input AND gate. With the help of
function table explain the operation of the circuit diagram.
(b) Design a CMOS transistor circuit that has the functional behavior as
( ) = (a + b) (b + c)(a + c)
Also draw the relevant circuit diagrams. [8+8]
2. (a) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation
with the help of function table.
(b) A single pull-up resistor to +5V is used to provide a constant-1 logic source
to 15 di erent 74LS00 inputs. What is the maximum value of this resistor?
How much high state DC noise margin can be provided in this case? [8+8]
3. (a) Explain the various data types supported by VHDL. Give the necessary ex-
amples.
(b) Discuss the case statement and its use in the VHDL program. [8+8]
4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural
VHDL program for the same. [16]
5. Design a two-digit BCD adder with logic gates. Using this logic write the VHDL
program. In structural style of modeling. [8+8]
6. Design a combinational logic circuit that counts the number of ones in a 24-bit
register. Write a VHDL program for the same using structural style or modeling.
[16]
7. (a) Draw the logic diagram of 74×163 binary counter and explain its operation.
(b) Design a modulo-100 counter using two 74×163 binary counters? [8+8]
8. (a) Design an 8×4 diode ROM using 74×138 for the following data starting from
the rst location.
6901
(b) How many ROM bits are required to build a 16-bit adder/subtractor with
mode control, carry input, carry output and two’s complement over ow out-
put. Show the block schematic with all inputs and outputs. [8+8]