VLSI design involves integrating hundreds of thousands of transistors onto a single microchip. It follows Moore's law, which predicts that the number of transistors per chip doubles every 18 months. The VLSI design flow includes behavioral, structural, and dataflow modeling using Verilog HDL. Test benches are used to apply inputs to designs and verify functionality. Common digital designs include microprocessors, UARTs for serial communication, and finite state machines like Mealy and Moore machines.

1. VLSI Design

2. Introduction
 Very large-scale integration (VLSI) is the process of integrating or embedding
hundreds of thousands of transistors on a single silicon semiconductor
microchip.
 It is one of the most widely used technologies for microchip processors,
integrated circuits (IC) and component designing
 An Integrated circuit is a set of electronics circuits on a small plate of
semiconductor material.
 Electronic circuit consist of a CPU, ROM, RAM etc.
Ex: Microprocessor
 First IC chip held only two transistors

3. Moor’s Law
Definition:
 Gordon Moore: co-founder of Intel, predicted that the number of transistors per
chip would grow exponentially (double every 18 months)

4. VLSI Design flow

5. Introduction to Verilog
• Verilog is a Hardware Description Language (HDL). It is a language used for describing a
digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can
describe any digital hardware by using HDL at any level. Designs described in HDL are
independent of technology, very easy for designing and debugging, and are normally more
useful than schematics, particularly for large circuits.
• Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL), which is used to describe a
digital system such as a network switch or a microprocessor or a memory a flip-flop.
• Verilog was developed to simplify the process and make the HDL more robust and flexible.
Today, Verilog is the most popular HDL used and practiced throughout the semiconductor
industry.

6. why use hdl?
• Digital systems are highly complex, they consist millions and billions of
transistors.
• For large digital system designs , gate level design is very difficult to achieve
in a short time.
• Hardware description languages allow the designers to describe a circuit using
words and symbols, and then the software converts that textual description
into configuration data that is loaded into FPGA in order to implement the
desired functionality.

7. Fundamental Elements of Verilog HDL
 Lexical conventions:
• The basic lexical conventions used by Verilog HDL are similar to those in the C
programming language. Verilog contains a stream of tokens. Tokens can be
comments, delimiters, numbers, strings, identifiers, and keywords.
 Whitespace:
• White space can contain the characters for blanks, tabs, newlines, and form feeds.
These characters are ignored except when they serve to separate other tokens.
However, blanks and tabs are significant in strings.
 Comments:
• Comments can be inserted in the code for readability and documentation.
1. Single line comments begin with the token // and end with a carriage return
2. Multi line comments begin with the token /* and end with the token */

8. Types of modeling
 Behavioral:
– Models describe what a module does.
– Use of assignment statements, loops, if, else
kind of statements
 Structural:
– Describes the structure of the hardware
components
– Interconnections of primitive gates (AND,
OR, NAND, NOR, etc.) and other modules

9.  Dataflow modelling:
– Dataflow modeling provides the means of describing combinational circuits by
their function rather than by their gate structure. Dataflow modeling uses a
number of operators that act on operands to produce the desired results. Verilog
HDL provides about 30 operator types.

10. Writing Test Bench
 A test bench specifies a sequence of inputs to be applied by the simulator
to an Verilog-based design.
 The test bench uses an initial block and delay statements and procedural
statement.
 Verilog has advanced “behavioral” commands to facilitate this:
– Delay for n units of time
– Full high-level constructs: if, while, sequential assignment.
– Input/output: file I/O, output to display, etc.

11. UART:
 In UART communication, two UARTs communicate directly with each other. The transmitting
UART converts parallel data from a controlling device like a CPU into serial form, transmits it
in serial to the receiving UART, which then converts the serial data back into parallel data for
the receiving device. Only two wires are needed to transmit data between two UARTs. Data
flows from the Tx pin of the transmitting UART to the Rx pin of the receiving UART:

12.  The UART that is going to transmit data receives the data from a data bus. The data bus is used to send data
to the UART by another device like a CPU, memory, or microcontroller. Data is transferred from the data
bus to the transmitting UART in parallel form. After the transmitting UART gets the parallel data from the
data bus, it adds a start bit, a parity bit, and a stop bit, creating the data packet. Next, the data packet is output
serially, bit by bit at the Tx pin. The receiving UART reads the data packet bit by bit at its Rx pin. The
receiving UART then converts the data back into parallel form and removes the start bit, parity bit, and stop
bits. Finally, the receiving UART transfers the data packet in parallel to the data bus on the receiving end:

13. FSM:
 Mealy Machine:
A Mealy Machine is an FSM whose output depends on the present state as well as the present
input.
It has also 6 tuples (Q, q0, ∑, ▲, δ, λ)where-
1. Q is a finite set of states
2. q0 is the initial state
3. ∑ is the input alphabet
4. ▲ is the output alphabet
5. δ is the transition function that maps Q×∑ → Q
6. λ is the output function that maps Q → ▲

14. Moore Machine:
 Moore machine is an FSM whose outputs depend on only the present state
 It has also 6 tuple (Q, ∑, O, δ, X, q0) where −
1. Q is a finite set of states
2. q0 is the initial state
3. ∑ is the input alphabet
4. ▲ is the output alphabet
5. δ is the transition function that maps Q×∑ → Q
6. λ is the output function that maps Q → ▲

15. The difference between the Mealy machine and Moore machine
 Output depends on the present state as well
as present input.
 Mealy Machine places its output on the
transition.
 Less number of states are required.
 There is more hardware requirement for
circuit implementation.
 They react faster to inputs.
 Asynchronous output generation.
 Output is placed on transitions
 It is difficult to design.
 Output depends only upon the present state.
 Moore machine also places its output on the
transition.
 More states are required.
 There is less hardware requirement for circuit
implementation.
 They react slower to inputs
 Synchronous output and state generation.
 Output is placed on states.
 Easy to design.

16. Thank You!