This presentation consists of Authenticated Encryption Decryption Scheme Project Idea, implementation and complete information. This Presentation was given at VLSI DESIGN CONFERENCE 2016 in Kolkata.
Two fish & Rijndael (AES) Encryption AlgorithmRifat Tasnim
In cryptography, the Advanced Encryption Standard (AES) is an encryption standard adopted by the
U.S. government. Back in 1997 the National Institute of Standards and Technology (NIST) made a public call for new cipher
algorithms that could replace the DES. A rough summary of
the requirements made by NIST for the new AES were the
following:
Symmetric-key cipher
Block cipher
Support for 128 bit block sizes
Support for 128, 192, and 256 bit key lengths.
A combination of factors such as security, performance,
efficiency, ease of implementation and flexibility contributed
to the selection of this algorithm as the AES.Twofish and Rijndael were designed to meet the requirements of the
Advanced Encryption Standard(AES) competition and selected among five finalists of that
competition.
Rijndael is the block cipher algorithm recently chosen by the National Institute of Science and Technology (NIST) as the Advanced Encryption Standard (AES). It supercedes the Data Encryption Standard (DES). NIST selected Rijndael as the standard symmetric key encryption algorithm to be used to encrypt sensitive (unclassified) American federal information. The choice was based on a careful and comprehensive analysis of the security and efficiency characteristics of Rijndael's algorithm.
Twofish is a symmetric block cipher with a 128-bit block size and key sizes of 128, 192, or 256 bits. It was designed by Bruce Schneier as an algorithm that is a combination of Blowfish and Square. The Twofish algorithm uses a 16-round structure where the plaintext is divided into four 32-bit words that are xored with key words and undergo transformations in each round before being swapped and combined to produce the ciphertext. Each round uses g-functions consisting of S-boxes and an MDS matrix, along with a PHT to diffuse the outputs which are then combined with key words.
This document provides an overview of digital systems and number representation in digital logic design. It discusses:
- Digital systems take discrete inputs and have discrete internal states to generate discrete outputs.
- Digital systems can be combinational (output depends only on input) or sequential (output depends on input and state). Sequential systems can be synchronous (state updates at clock) or asynchronous.
- Number systems like binary, octal, hexadecimal represent numbers using different radixes or bases. Binary uses two digits (0-1) while octal uses eight and hexadecimal uses sixteen.
- Operations like addition and subtraction can be performed in any number base through appropriate algorithms. Numbers can be converted between bases through division and
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
Twofish is a symmetric block cipher that was a candidate for the Advanced Encryption Standard. It has a 128-bit block size and supports 128, 192, or 256-bit keys. Twofish performs encryption over 16 rounds and uses key-dependent substitution boxes, a pseudo-Hadamard transform, and an MDS matrix for diffusion. The algorithm was designed to be secure, efficient in software and hardware, and easy to implement.
Twofish is a symmetric block cipher that uses a 16-round Feistel network with a block size of 128 bits and key sizes up to 256 bits. It was one of the five finalists in the AES competition. Twofish's building blocks include S-boxes, MDS matrices, and a key schedule. Differential cryptanalysis is the most successful attack against Twofish but requires a large number of chosen plaintexts and computational resources beyond what is practical. Twofish has efficient performance across many platforms and competitive speeds compared to other AES finalists.
This document discusses digital systems and binary number representation. It covers:
1) An overview of digital systems including their applications and design process.
2) Converting between different number bases such as binary, decimal, octal and hexadecimal. Methods for addition, subtraction, multiplication and division in binary are also presented.
3) Techniques for representing negative numbers in binary including sign-magnitude, 1's complement, and 2's complement representations. The process of adding numbers in both the 1's complement and 2's complement systems is explained.
Mcs 012 computer organisation and assemly language programming- ignou assignm...Dr. Loganathan R
The document discusses various computer architecture concepts including:
1. A hypothetical new machine is described with 64 64-bit general purpose registers, 2GB of 32-bit memory, and instructions that are one or two memory words. Four addressing modes are needed: direct, index, base register, and stack to access variables and arrays.
2. Terms related to magnetic disk access are defined, including tracks, sectors, seek time, rotational latency, transfer time, and access time. Calculations are shown to find the average access time of 13.04ms for a 2048 byte sector disk rotating at 3000 RPM with a 64MB/s transfer rate.
3. Input/output techniques like programmed I/O,
Two fish & Rijndael (AES) Encryption AlgorithmRifat Tasnim
In cryptography, the Advanced Encryption Standard (AES) is an encryption standard adopted by the
U.S. government. Back in 1997 the National Institute of Standards and Technology (NIST) made a public call for new cipher
algorithms that could replace the DES. A rough summary of
the requirements made by NIST for the new AES were the
following:
Symmetric-key cipher
Block cipher
Support for 128 bit block sizes
Support for 128, 192, and 256 bit key lengths.
A combination of factors such as security, performance,
efficiency, ease of implementation and flexibility contributed
to the selection of this algorithm as the AES.Twofish and Rijndael were designed to meet the requirements of the
Advanced Encryption Standard(AES) competition and selected among five finalists of that
competition.
Rijndael is the block cipher algorithm recently chosen by the National Institute of Science and Technology (NIST) as the Advanced Encryption Standard (AES). It supercedes the Data Encryption Standard (DES). NIST selected Rijndael as the standard symmetric key encryption algorithm to be used to encrypt sensitive (unclassified) American federal information. The choice was based on a careful and comprehensive analysis of the security and efficiency characteristics of Rijndael's algorithm.
Twofish is a symmetric block cipher with a 128-bit block size and key sizes of 128, 192, or 256 bits. It was designed by Bruce Schneier as an algorithm that is a combination of Blowfish and Square. The Twofish algorithm uses a 16-round structure where the plaintext is divided into four 32-bit words that are xored with key words and undergo transformations in each round before being swapped and combined to produce the ciphertext. Each round uses g-functions consisting of S-boxes and an MDS matrix, along with a PHT to diffuse the outputs which are then combined with key words.
This document provides an overview of digital systems and number representation in digital logic design. It discusses:
- Digital systems take discrete inputs and have discrete internal states to generate discrete outputs.
- Digital systems can be combinational (output depends only on input) or sequential (output depends on input and state). Sequential systems can be synchronous (state updates at clock) or asynchronous.
- Number systems like binary, octal, hexadecimal represent numbers using different radixes or bases. Binary uses two digits (0-1) while octal uses eight and hexadecimal uses sixteen.
- Operations like addition and subtraction can be performed in any number base through appropriate algorithms. Numbers can be converted between bases through division and
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
Twofish is a symmetric block cipher that was a candidate for the Advanced Encryption Standard. It has a 128-bit block size and supports 128, 192, or 256-bit keys. Twofish performs encryption over 16 rounds and uses key-dependent substitution boxes, a pseudo-Hadamard transform, and an MDS matrix for diffusion. The algorithm was designed to be secure, efficient in software and hardware, and easy to implement.
Twofish is a symmetric block cipher that uses a 16-round Feistel network with a block size of 128 bits and key sizes up to 256 bits. It was one of the five finalists in the AES competition. Twofish's building blocks include S-boxes, MDS matrices, and a key schedule. Differential cryptanalysis is the most successful attack against Twofish but requires a large number of chosen plaintexts and computational resources beyond what is practical. Twofish has efficient performance across many platforms and competitive speeds compared to other AES finalists.
This document discusses digital systems and binary number representation. It covers:
1) An overview of digital systems including their applications and design process.
2) Converting between different number bases such as binary, decimal, octal and hexadecimal. Methods for addition, subtraction, multiplication and division in binary are also presented.
3) Techniques for representing negative numbers in binary including sign-magnitude, 1's complement, and 2's complement representations. The process of adding numbers in both the 1's complement and 2's complement systems is explained.
Mcs 012 computer organisation and assemly language programming- ignou assignm...Dr. Loganathan R
The document discusses various computer architecture concepts including:
1. A hypothetical new machine is described with 64 64-bit general purpose registers, 2GB of 32-bit memory, and instructions that are one or two memory words. Four addressing modes are needed: direct, index, base register, and stack to access variables and arrays.
2. Terms related to magnetic disk access are defined, including tracks, sectors, seek time, rotational latency, transfer time, and access time. Calculations are shown to find the average access time of 13.04ms for a 2048 byte sector disk rotating at 3000 RPM with a 64MB/s transfer rate.
3. Input/output techniques like programmed I/O,
International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...IOSR Journals
Abstract: In this paper we have designed and implemented(15, k) a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organized into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form up to k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 code word. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 13.3. BCH encoders are conventionally implemented by linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fan out, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. Also a comparative performance based on synthesis & simulation on FPGA is presented. Keywords: BCH, BCH Encoder, FPGA, VHDL, Error Correction, AWGN, LFSR cyclic redundancy checking, fan out .
Error control coding using bose chaudhuri hocquenghem bch codesIAEME Publication
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Electronic Codebook Book (ECB) encrypts each message block independently without chaining blocks together. This can reveal patterns in the ciphertext if the plaintext has repetitive blocks. Cipher Block Chaining (CBC) chains blocks together by XORing the previous ciphertext block with the current plaintext block before encryption. Counter (CTR) mode encrypts a counter value rather than feedback from previous blocks, allowing parallel encryption. These modes of operation can be used to encrypt data blocks securely depending on needs such as bulk encryption or streaming data.
B.sc cs-ii-u-1.9 digital logic circuits, digital component floting and fixed ...Rai University
1) Fixed point numbers represent integers in a binary format using a fixed number of bits. They have limited range but are fast and inexpensive to implement. Floating point numbers use exponents to represent a wider range of values with varying precision levels.
2) Common data types include short (16-bit integer), int (32-bit integer), float (32-bit floating point), and double (64-bit floating point). Floating point values follow IEEE standards and use significands and exponents.
3) Single precision floating point uses 32 bits with 24 bits for the significand, while double precision uses 64 bits with 53 bits for the significand, allowing wider value ranges to be represented.
This document discusses digital logic design and binary numbers. It covers topics such as digital vs analog signals, binary number systems, addition and subtraction in binary, and number base conversions between decimal, binary, octal, and hexadecimal. It also discusses complements, specifically 1's complement and radix complement. The purpose is to provide background information on fundamental concepts for digital logic design.
Bca 2nd sem-u-1.9 digital logic circuits, digital component floting and fixed...Rai University
1) Fixed point numbers represent integers in a binary format using a fixed number of bits. They have limited range but are fast and inexpensive to implement. Floating point numbers use exponents to represent a wider range of values with varying precision levels.
2) Common data types include short (16-bit integer), int (32-bit integer), float (32-bit floating point), and double (64-bit floating point). Floating point values follow IEEE standards and use significands and exponents.
3) Single precision floating point uses 32 bits with 24 bits for the significand, while double precision uses 64 bits with 53 bits for the significand, allowing wider ranges of values to be represented.
RC5 is a block cipher that uses a variable key size, number of rounds, and word size. It has a simple design that makes it efficient to implement on CPUs. The nominal version uses 32-bit words, a 64-bit block size, 128-bit key, and 12 rounds. It expands the secret key into a table of words that are used in both encryption and decryption, which update both halves of the input block in each round.
The document provides an overview of various data processing circuits including multiplexers, demultiplexers, decoders, encoders, adders, flip-flops and other logic gates. It describes the basic functionality and implementation of different types of multiplexers and demultiplexers with varying number of inputs and outputs. Decoder circuits like 1-of-16 decoder are explained along with their truth tables. Different arithmetic building blocks such as half adder, full adder and arithmetic logic unit are covered. The document also discusses flip-flops like RS, D, JK and their edge-triggered variations. Finally, it provides details on binary coded decimal representation.
This document discusses hash and MAC algorithms. It provides details on hash functions, the Secure Hash Algorithm (SHA), and HMAC.
Hash functions take a message and produce a fixed-size hash value. SHA is a secure hash algorithm developed by NIST that produces 160-bit or longer hash values. It involves padding the message, initializing a buffer, processing the message in blocks through a compression function, and outputting the final hash.
HMAC is a MAC algorithm that incorporates a secret key into an existing hash function like MD5 or SHA. It pads and XORs the key, hashes the result with the message, then hashes again with a padded key to produce the MAC value.
The document discusses different types of binary adders and arithmetic circuits. A binary adder uses full adder circuits connected in cascade to generate the sum of two binary numbers of any length. A binary adder-subtractor can perform both addition and subtraction using an exclusive-OR gate with each full adder and a mode input to control the operation. A binary incrementer independently increments a number using a combinational circuit. An arithmetic circuit uses a parallel adder as its basic component and multiplexers to choose different arithmetic operations like addition, subtraction, and increment on its inputs and output.
This document provides information about BCH codes, including:
1. BCH codes are linear cyclic block codes that can detect and correct errors. They allow flexibility in choosing block length and code rate.
2. Key characteristics of BCH codes include the block length being 2m - 1, error correction ability up to t errors where t<(2m - 1)/2, and minimum distance of at least 2t + 1.
3. Galois fields are finite fields that are important for constructing BCH codes. A generator polynomial is chosen based on the roots in the Galois field and is used to encode messages into codewords.
Performance Improved Multipliers Based on Non-Redundant Radix-4 Signed-Digit ...IJMTST Journal
In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {1; 0; +1; +2} or {-2; -1; 0; +1}, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.
Implementation of Designed Encoder and Decoder for Golay CodeIRJET Journal
This document presents the design and implementation of encoders and decoders for Golay codes. It begins with background on Golay codes, which are error-correcting codes used in wireless communication. It then describes an algorithm for Golay code encoding using polynomial long division to generate check bits from message bits. The document proposes optimized FPGA-based architectures for a Golay (23,12,7) encoder and extending it to a Golay (24,12,8) encoder by adding a parity bit. It provides an example of encoding a message and validating the generated codeword. The encoder architectures use priority encoders, shift registers, and controlled subtractors to efficiently perform the cyclic polynomial long division encoding process in hardware.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
This document describes the design of a BCD adder. It discusses three cases for adding two 4-bit BCD numbers: 1) the sum is valid if less than or equal to 9 with no carry, 2) correction is needed if the sum is greater than 9 with no carry by adding 6, and 3) correction is needed if the sum is less than or equal to 9 but with a carry by adding 6. The design uses two 4-bit binary adders, with the output of the first checked by a combinational circuit to determine if correction is needed. The circuit outputs control the second adder to apply the necessary correction to produce the valid BCD sum.
Maximum likelihood sequence detection with the viterbi algorithmbajrang bansal
This document discusses maximum likelihood sequence detection and the Viterbi algorithm. It begins with an outline and introduction of MLSD. It then describes the Viterbi algorithm, how it uses dynamic programming to detect symbol sequences. It discusses the tools needed for Viterbi algorithm sequence detection including state diagrams and trellises. It provides a step-by-step example of how the Viterbi algorithm works. Finally, it discusses how the Viterbi algorithm can be extended to MLSD and how MLSD works for binary and M-ary signal detection using trellises and minimizing path metrics.
Modified Golomb Code For Integer RepresentationIJSRD
In this computer age, all the computer applications handle data in the form of text, numbers, symbols and combination of all of them. The primary objective of data compression is to reduce the size of data while data needs to be stored and transmitted in the digital devices. Hence, the data compression plays a vital role in the areas of data storage and data transmission. Golomb code, which is a variable-length integer code, has been used for text compression, image compression, video compression and audio compression. The drawback of Golomb code is that it requires more bits to represent large integers if the divisor is small. Alternatively, Golomb code needs more bits to represent small integers if the divisor is large. This paper proposes Modified Golomb Code based on Golomb Code, Extended Golomb Code to represent small as well as large integers compactly for the chosen divisor. In this work, as an application of Modified Golomb Code, Modified Golomb Code is used with Burrows-Wheeler transform for text compression. The performances of Golomb Code and Modified Golomb Code are evaluated on Calcary corpus dataset. The experimental results show that the proposed code provides better compression rate than Golomb code on an average. The performance of the proposed code is also compared with Extended Golomb Codes (EGC). The comparison results show that the proposed code achieves significant improvement for the binary files of Calgary corpus comparing to EGC.
BCH codes, part of the cyclic codes, are very powerful error correcting codes widely used in the information coding techniques. This presentation explains these codes with an example.
This document provides an executive summary and resume for Rabi Shankar Pal, an SAP Basis Consultant with over 9 years of experience. It outlines his skills and experience in areas such as SAP implementation, OS/DB migration, AMS support, and automation of monitoring processes. Recent projects include roles supporting Kellogg and Pennsylvania Department of Revenue. The resume lists educational background and technical certifications.
This presentation consists of the Seminar, provided by me in the partial fulfillment of my Bachelors Degree in G B Pant Engineering College. Seminar included information about Encryption, Decryption, Cryptosystems and Authenticity in crytosystem.
1) The document proposes a technique that allows cryptography and steganography to be combined by encrypting text data and hiding it within the least significant bits of pixels in an image.
2) It discusses using the Advanced Encryption Standard (AES) algorithm to encrypt the text before embedding it in the selected areas of an image.
3) For decryption, the receiver must know the correct encryption key in order to extract the hidden text from the stego-image and decrypt it back to the original plaintext.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...IOSR Journals
Abstract: In this paper we have designed and implemented(15, k) a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organized into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form up to k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 code word. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 13.3. BCH encoders are conventionally implemented by linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fan out, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. Also a comparative performance based on synthesis & simulation on FPGA is presented. Keywords: BCH, BCH Encoder, FPGA, VHDL, Error Correction, AWGN, LFSR cyclic redundancy checking, fan out .
Error control coding using bose chaudhuri hocquenghem bch codesIAEME Publication
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Electronic Codebook Book (ECB) encrypts each message block independently without chaining blocks together. This can reveal patterns in the ciphertext if the plaintext has repetitive blocks. Cipher Block Chaining (CBC) chains blocks together by XORing the previous ciphertext block with the current plaintext block before encryption. Counter (CTR) mode encrypts a counter value rather than feedback from previous blocks, allowing parallel encryption. These modes of operation can be used to encrypt data blocks securely depending on needs such as bulk encryption or streaming data.
B.sc cs-ii-u-1.9 digital logic circuits, digital component floting and fixed ...Rai University
1) Fixed point numbers represent integers in a binary format using a fixed number of bits. They have limited range but are fast and inexpensive to implement. Floating point numbers use exponents to represent a wider range of values with varying precision levels.
2) Common data types include short (16-bit integer), int (32-bit integer), float (32-bit floating point), and double (64-bit floating point). Floating point values follow IEEE standards and use significands and exponents.
3) Single precision floating point uses 32 bits with 24 bits for the significand, while double precision uses 64 bits with 53 bits for the significand, allowing wider value ranges to be represented.
This document discusses digital logic design and binary numbers. It covers topics such as digital vs analog signals, binary number systems, addition and subtraction in binary, and number base conversions between decimal, binary, octal, and hexadecimal. It also discusses complements, specifically 1's complement and radix complement. The purpose is to provide background information on fundamental concepts for digital logic design.
Bca 2nd sem-u-1.9 digital logic circuits, digital component floting and fixed...Rai University
1) Fixed point numbers represent integers in a binary format using a fixed number of bits. They have limited range but are fast and inexpensive to implement. Floating point numbers use exponents to represent a wider range of values with varying precision levels.
2) Common data types include short (16-bit integer), int (32-bit integer), float (32-bit floating point), and double (64-bit floating point). Floating point values follow IEEE standards and use significands and exponents.
3) Single precision floating point uses 32 bits with 24 bits for the significand, while double precision uses 64 bits with 53 bits for the significand, allowing wider ranges of values to be represented.
RC5 is a block cipher that uses a variable key size, number of rounds, and word size. It has a simple design that makes it efficient to implement on CPUs. The nominal version uses 32-bit words, a 64-bit block size, 128-bit key, and 12 rounds. It expands the secret key into a table of words that are used in both encryption and decryption, which update both halves of the input block in each round.
The document provides an overview of various data processing circuits including multiplexers, demultiplexers, decoders, encoders, adders, flip-flops and other logic gates. It describes the basic functionality and implementation of different types of multiplexers and demultiplexers with varying number of inputs and outputs. Decoder circuits like 1-of-16 decoder are explained along with their truth tables. Different arithmetic building blocks such as half adder, full adder and arithmetic logic unit are covered. The document also discusses flip-flops like RS, D, JK and their edge-triggered variations. Finally, it provides details on binary coded decimal representation.
This document discusses hash and MAC algorithms. It provides details on hash functions, the Secure Hash Algorithm (SHA), and HMAC.
Hash functions take a message and produce a fixed-size hash value. SHA is a secure hash algorithm developed by NIST that produces 160-bit or longer hash values. It involves padding the message, initializing a buffer, processing the message in blocks through a compression function, and outputting the final hash.
HMAC is a MAC algorithm that incorporates a secret key into an existing hash function like MD5 or SHA. It pads and XORs the key, hashes the result with the message, then hashes again with a padded key to produce the MAC value.
The document discusses different types of binary adders and arithmetic circuits. A binary adder uses full adder circuits connected in cascade to generate the sum of two binary numbers of any length. A binary adder-subtractor can perform both addition and subtraction using an exclusive-OR gate with each full adder and a mode input to control the operation. A binary incrementer independently increments a number using a combinational circuit. An arithmetic circuit uses a parallel adder as its basic component and multiplexers to choose different arithmetic operations like addition, subtraction, and increment on its inputs and output.
This document provides information about BCH codes, including:
1. BCH codes are linear cyclic block codes that can detect and correct errors. They allow flexibility in choosing block length and code rate.
2. Key characteristics of BCH codes include the block length being 2m - 1, error correction ability up to t errors where t<(2m - 1)/2, and minimum distance of at least 2t + 1.
3. Galois fields are finite fields that are important for constructing BCH codes. A generator polynomial is chosen based on the roots in the Galois field and is used to encode messages into codewords.
Performance Improved Multipliers Based on Non-Redundant Radix-4 Signed-Digit ...IJMTST Journal
In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {1; 0; +1; +2} or {-2; -1; 0; +1}, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.
Implementation of Designed Encoder and Decoder for Golay CodeIRJET Journal
This document presents the design and implementation of encoders and decoders for Golay codes. It begins with background on Golay codes, which are error-correcting codes used in wireless communication. It then describes an algorithm for Golay code encoding using polynomial long division to generate check bits from message bits. The document proposes optimized FPGA-based architectures for a Golay (23,12,7) encoder and extending it to a Golay (24,12,8) encoder by adding a parity bit. It provides an example of encoding a message and validating the generated codeword. The encoder architectures use priority encoders, shift registers, and controlled subtractors to efficiently perform the cyclic polynomial long division encoding process in hardware.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
This document describes the design of a BCD adder. It discusses three cases for adding two 4-bit BCD numbers: 1) the sum is valid if less than or equal to 9 with no carry, 2) correction is needed if the sum is greater than 9 with no carry by adding 6, and 3) correction is needed if the sum is less than or equal to 9 but with a carry by adding 6. The design uses two 4-bit binary adders, with the output of the first checked by a combinational circuit to determine if correction is needed. The circuit outputs control the second adder to apply the necessary correction to produce the valid BCD sum.
Maximum likelihood sequence detection with the viterbi algorithmbajrang bansal
This document discusses maximum likelihood sequence detection and the Viterbi algorithm. It begins with an outline and introduction of MLSD. It then describes the Viterbi algorithm, how it uses dynamic programming to detect symbol sequences. It discusses the tools needed for Viterbi algorithm sequence detection including state diagrams and trellises. It provides a step-by-step example of how the Viterbi algorithm works. Finally, it discusses how the Viterbi algorithm can be extended to MLSD and how MLSD works for binary and M-ary signal detection using trellises and minimizing path metrics.
Modified Golomb Code For Integer RepresentationIJSRD
In this computer age, all the computer applications handle data in the form of text, numbers, symbols and combination of all of them. The primary objective of data compression is to reduce the size of data while data needs to be stored and transmitted in the digital devices. Hence, the data compression plays a vital role in the areas of data storage and data transmission. Golomb code, which is a variable-length integer code, has been used for text compression, image compression, video compression and audio compression. The drawback of Golomb code is that it requires more bits to represent large integers if the divisor is small. Alternatively, Golomb code needs more bits to represent small integers if the divisor is large. This paper proposes Modified Golomb Code based on Golomb Code, Extended Golomb Code to represent small as well as large integers compactly for the chosen divisor. In this work, as an application of Modified Golomb Code, Modified Golomb Code is used with Burrows-Wheeler transform for text compression. The performances of Golomb Code and Modified Golomb Code are evaluated on Calcary corpus dataset. The experimental results show that the proposed code provides better compression rate than Golomb code on an average. The performance of the proposed code is also compared with Extended Golomb Codes (EGC). The comparison results show that the proposed code achieves significant improvement for the binary files of Calgary corpus comparing to EGC.
BCH codes, part of the cyclic codes, are very powerful error correcting codes widely used in the information coding techniques. This presentation explains these codes with an example.
This document provides an executive summary and resume for Rabi Shankar Pal, an SAP Basis Consultant with over 9 years of experience. It outlines his skills and experience in areas such as SAP implementation, OS/DB migration, AMS support, and automation of monitoring processes. Recent projects include roles supporting Kellogg and Pennsylvania Department of Revenue. The resume lists educational background and technical certifications.
This presentation consists of the Seminar, provided by me in the partial fulfillment of my Bachelors Degree in G B Pant Engineering College. Seminar included information about Encryption, Decryption, Cryptosystems and Authenticity in crytosystem.
1) The document proposes a technique that allows cryptography and steganography to be combined by encrypting text data and hiding it within the least significant bits of pixels in an image.
2) It discusses using the Advanced Encryption Standard (AES) algorithm to encrypt the text before embedding it in the selected areas of an image.
3) For decryption, the receiver must know the correct encryption key in order to extract the hidden text from the stego-image and decrypt it back to the original plaintext.
Minor Project- AES Implementation in VerilogHardik Manocha
This presentation described about the Minor project I worked on for partial fulfillment of Bachelors Degree in G B Pant Engineering College. Presentation consisted of Advanced Encryption Standard (AES) and its implementation in Verilog. Different steps of the algorithm are presented.
Using this software any 50 sec audio message can be decrypted into image file and then original message can again be recovered from image file. This project is coded in Matlab and gui is also built in Matlab.
The document describes a modified AES key expansion algorithm for image encryption and decryption. It discusses basics of cryptography and image encryption. It introduces AES and describes the standard AES key expansion process. It then presents a modified AES key expansion algorithm tailored for images where the keys are expanded based on image pixel count, Rcon values are derived from the initial key, and the S-box is shifted based on the initial key. It analyzes the proposed algorithm and shows it offers high encryption quality with minimal time compared to previous techniques.
Encryption converts plaintext into ciphertext using an algorithm and key. Gaussian elimination with partial pivoting and row exchange is used to encrypt images by converting the image matrix to an upper triangular matrix and generating a decryption key. The encrypted image matrix and key can then be multiplied to recover the original image matrix and decrypt the image. This algorithm allows for faster encryption time while still producing robust encryption to prevent unauthorized access to images.
Cryptography is the science of using mathematics to encrypt and decrypt data.
Cryptography enables you to store sensitive information or transmit it across insecure networks so that it cannot be read by anyone except the intended recipient.
This document provides an overview of cryptography. It defines cryptography as the science of securing messages from attacks. It discusses basic cryptography terms like plain text, cipher text, encryption, decryption, and keys. It describes symmetric key cryptography, where the same key is used for encryption and decryption, and asymmetric key cryptography, which uses different public and private keys. It also covers traditional cipher techniques like substitution and transposition ciphers. The document concludes by listing some applications of cryptography like e-commerce, secure data, and access control.
The document provides an overview of encryption, including what it is, why it is used, and how it works. Encryption is the process of encoding information to protect it, while decryption is decoding the information. There are two main types of encryption: asymmetric encryption which uses public and private keys, and symmetric encryption which uses a shared key. Encryption is used to secure important data like health records, credit cards, and student information from being stolen or read without permission. It allows senders to encode plain text into ciphertext using a key.
This project involves Hardware Implementation of TIAOXIN-346, a design submitted in CAESAR in relation to Authenticated Encryption Scheme. This design includes AES for Encryption and Decryption purpose. Presently working on Side Channel Attacks to test the design's security. Complete documentation is on the profile.
Lecture on 18 December 2018
Role of Cryptography in Blockchain
RSA and SHA
Blockchain for Beginners
Elective course from the Faculty of Information Technology, Thai - Nichi Institute of Technology, Bangkok for undergraduate students.
#BlockchainTNI2018
introduction to MD5 Massage Digest Algorithm.pptmadlord2
This document summarizes the MD5 message digest algorithm. It was developed by Professor Ronald L. Rivest in 1991 to take an input of arbitrary length and produce a 128-bit fingerprint. The MD5 algorithm structure and implementation steps are described, including padding the input, appending the length, initializing buffers, and processing the message in 16-word blocks through four rounds of functions. Performance is provided showing MD5 is very fast on 32-bit machines. MD5 is compared to MD4, noting changes made and that it is widely used and considered efficient.
Linear block codes take binary data in blocks and encode them into longer codewords by adding redundant bits to allow for error detection and correction. The document discusses key concepts of linear block codes including generator and parity check matrices, syndrome detection, minimum distance, and applications. It also provides an example of a (6,3) linear block code and a (7,4) Hamming code.
project ppt on anti counterfeiting technique for credit card transaction systemRekha dudiya
CREDI-CRYPT is a technique that hides sensitive credit card information in a background image using both cryptography and steganography. It encodes credit card details like the card number and CVV using techniques like arithmetic coding and Hamming codes. The encoded text is then embedded into the pixel coefficients of the cover image using an integer wavelet transform and optimal pixel adjustment. This ensures confidentiality and integrity of credit card transactions while transmitting payment details over unsecured networks. The system was designed to be used as a standalone application by small to medium banks and organizations for securely storing credit card data without network transfer.
The document discusses the Advanced Encryption Standard (AES) algorithm. It describes AES as a cybersecurity standard for encrypting electronic data using symmetric-key algorithms with key sizes of 128, 192, and 256 bits. The document outlines the key components of AES, including the key expansion, round key addition, byte substitution, row shifting, column mixing, and different numbers of transformation rounds depending on the key size. It also explains the processes of AES encryption and decryption. Finally, it discusses various modes of operation for AES, such as electronic codebook (ECB), cipher block chaining (CBC), cipher feedback (CFM), output feedback (OFM), and counter (CTR) modes.
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...Madhumita Tamhane
In contrast to block codes, Convolution coding scheme has an information frame together with previous m information frames encoded into a single code word frame, hence coupling successive code word frames. Convolution codes are most important Tree codes that satisfy certain additional linearity and time invariance properties. Decoding procedure is mainly devoted to correcting errors in first frame. The effect of these information symbols on subsequent code word frames can be computed and subtracted from subsequent code word frames. Hence in spite of infinitely long code words, computations can be arranged so that the effect of earlier frames, properly decoded, on the current frame is zero.
This document provides an introduction to block cipher systems, including the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES). It describes the basic structure and processes of block ciphers, including the use of secret keys, encryption/decryption algorithms, and block sizes. For DES, it outlines the key size, number of rounds, and encryption flow. For AES, it compares the different key sizes and number of rounds, and provides details on the cryptographic functions used in a single round of encryption.
A very clear presentation on Crytographic Alogotithms DES and RSA with basic concepts of cryptography. This presented by students of Techno India, Salt Lake.
This document discusses channel coding and linear block codes. Channel coding adds redundant bits to input data to allow error detection and correction at the receiver. Linear block codes divide the data into blocks, encode each block into a larger codeword, and use a generator matrix to map message blocks to unique codewords. The codewords can be detected and sometimes corrected using a parity check matrix. Hamming codes are a type of linear block code that can correct single bit errors. The document provides examples of encoding data using generator matrices and decoding using syndrome values and parity check matrices. It also discusses how the minimum distance of a code determines its error detection and correction capabilities.
This document summarizes key aspects of the Data Encryption Standard (DES) block cipher. It describes how DES operates on 64-bit blocks using a 56-bit key in 16 rounds based on a Feistel network structure. Each round uses 48-bit subkeys generated from the main key. The document also discusses DES modes of operation like ECB, CBC, CFB, OFB and CTR and how they encrypt blocks of plaintext. Finally, it notes NIST's role in establishing encryption standards and the history of DES adoption as a standard in 1977.
Transform coding is a lossy compression technique that converts data like images and videos into an alternate form that is more convenient for compression purposes. It does this through a transformation process followed by coding. The transformation removes redundancy from the data by converting pixels into coefficients, lowering the number of bits needed to store them. For example, an array of 4 pixels requiring 32 bits to store originally might only need 20 bits after transformation. Transform coding is generally used for natural data like audio and images, removes redundancy, lowers bandwidth, and can form images with fewer colors. JPEG is an example of transform coding.
This document discusses combinational logic design, specifically combinational logic functions and their implementation using decoders and multiplexers. It provides an overview of combinational logic and covers topics like rudimentary logic functions, decoding using decoders, encoding using encoders, and selecting using multiplexers. Examples are given for implementing combinational logic functions with decoders and multiplexers. Procedures for expanding decoders and multiplexers to handle more inputs and outputs are also described.
Overview on Cryptography and Network SecurityDr. Rupa Ch
These slides give some overview on the the concepts which were in Crytography and network security. I have prepared these slides by the experiece after refer the text bbok as well as resources from the net. Added figures directly from the references. I would like to acknowledge all the authors by originally.
Efficient Data Storage for Analytics with Parquet 2.0 - Hadoop Summit 2014Julien Le Dem
Apache Parquet is an open-source columnar storage format for efficient data storage and analytics. It provides efficient compression and encoding techniques that enable fast scans and queries of large datasets. Parquet 2.0 improves on these efficiencies through techniques like delta encoding, dictionary encoding, run-length encoding and binary packing designed for CPU and cache optimizations. Benchmark results show Parquet provides much better compression and faster query performance than other formats like text, Avro and RCFile. The project is developed as an open source community with contributions from many organizations.
Efficient Data Storage for Analytics with Apache Parquet 2.0Cloudera, Inc.
Apache Parquet is an open-source columnar storage format for efficient data storage and analytics. It provides efficient compression and encoding techniques that enable fast scans and queries of large datasets. Parquet 2.0 improves on these efficiencies through enhancements like delta encoding, binary packing designed for CPU efficiency, and predicate pushdown using statistics. Benchmark results show Parquet provides much better compression and query performance than row-oriented formats on big data workloads. The project is developed as an open-source community with contributions from many organizations.
The IDEA encryption algorithm was designed in 1990 at ETH Zurich. It operates on 64-bit plaintext blocks, has a 128-bit key, and consists of 8 rounds of processing with 16-bit subkeys derived from the main key. The algorithm mixes XOR, addition modulo 216, and multiplication modulo 216 + 1 operations on its 16-bit subblocks at each round. IDEA is faster than DES in software implementations and remains secure against known cryptanalytic attacks due to its large key size and complex operations.
This document provides an introduction and overview of key concepts in software development and data structures. It discusses the software development process, performance analysis using Big O notation, abstract data types, and introduces common data structures. Some key topics covered include specification and design of problems, implementation principles, testing and debugging, complexity analysis, preconditions and postconditions, and object-oriented programming as it relates to data structures.
C++ Is One Of The widely used programming language. Here is the complete presentation PPT notes of C++ programming language. hope it will be helpful to you.
Similar to VLSI DESIGN Conference 2016, Kolkata- Authenticated Encryption Decryption (20)
Initially worked on a prototype for value estimations and later employed the prototype design on an E-Rickshaw. PWM based controller is used for charging Panels and allowing simultaneous charge discharge of batteries
This document proposes a hybrid encryption-decryption algorithm combining AES and DES. It implements the algorithm in VHDL using a Modelsim platform. The hybrid algorithm integrates AES into each iteration of DES's Feistel network, using AES operations like substitution and key addition. This increases computational complexity compared to the individual standards. The VHDL implementation includes modules for AES encryption/decryption and the hybrid algorithm. Simulations validate the code works correctly. Future work could increase iterations to suit different security levels or implement a 128-bit AES variant. The hybrid approach strengthens AES security against attacks.
This document describes the development and implementation of the SPI and UART serial communication protocols in Verilog HDL. Both protocols were implemented considering different operating modes like master/slave and transmit/receive modes. Verilog was used to simulate the protocols in Xilinx ISE Design Suite and Modelsim. A single pin allows selecting between the SPI and UART modes.
8 bit Microprocessor with Single Vectored InterruptHardik Manocha
SoC consists of instruction memory, main memory and microprocessor unit. Instructions are fetched using PC and as per the instruction, main memory and register memory are accessed. 8 bit data bus is built. Working on developing programs to look for microprocessor operation.
Project consists of individual modules of encryption and decryption units. Standard T-DES algorithm is implemented. Presently working on to integrate DES with AES to develop stronger crypto algorithm and test the same against Side Channel Attacks and compare different algorithms.
This document describes a student project to implement the Advanced Encryption Standard (AES) in Verilog. AES is a symmetric block cipher that uses 128-bit blocks and 128/192/256-bit keys. The project aims to develop optimized and synthesizable Verilog code to encrypt and decrypt 128-bit data using AES. The document provides background on cryptography, AES, and its algorithm which includes key expansion, substitution, transposition, and mixing operations. It also outlines the implementation, encryption, decryption, and performance estimation aspects of the project.
Advanced Encryption Standard (AES) with Dynamic Substitution BoxHardik Manocha
AES algorithm has been stated as secure against any attack but increasing fast computing is making hackers to develop the cracks for AES as well. Therefore to further increase the security of AES, i tried to replace Standard static and fixed Substitution Box with a dynamic S Box. Dynamicity is brought with the help of Input key. Static S box is altered using the input key and the new generated s box is used for encryption. Reverse steps goes for Decryption. Presently, working on to test this design against Side Channel attacks and would publish the results here.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...University of Maribor
Slides from talk presenting:
Aleš Zamuda: Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapter and Networking.
Presentation at IcETRAN 2024 session:
"Inter-Society Networking Panel GRSS/MTT-S/CIS
Panel Session: Promoting Connection and Cooperation"
IEEE Slovenia GRSS
IEEE Serbia and Montenegro MTT-S
IEEE Slovenia CIS
11TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTING ENGINEERING
3-6 June 2024, Niš, Serbia
2. About Us
• Design Contest Challenge D3
– Efficient Accelerator for Authenticated Encryption
• Title of the Project: HarSam
• Authors:
» Samnit Dua
• Final Year Student, B.Tech- E.C.E
• G B Pant Government Engineering College, GGSIPU,
Delhi
» Hardik Manocha
• Final Year Student, B.Tech-E.C.E
• G B Pant Government Engineering College, GGSIPU,
Delhi
3. Authenticated Encryption- AE
• What it is:
– A simple process to authenticate the confidential data of a
process, object, human or about anything; to increase the
security associated with the data.
– It describes that the person transmitting the data is the Actual
person who has to send the data.
– On the receiving end, data comes from where it is intended to
come from.
– MUCH SECURE scheme than the scheme of Encrypting (AES)
and then Authenticating the message(MAC).
– Easier for developers to incorporate Authentication in their
designs.
4. AE continued..
•Authentication is much needed to secure the encrypted data.
• Systems involving Encryption without Authentication: XML Encryption, WEP
etc.
• Above mentioned Systems were susceptible to attacks and therefore less
reliable.
• Then came the need for Authenticity to be associated with Encryption so that
attackers had to work upon a stronger string of data.
• Two ways to apply authenticity:
• Encrypt the data and then apply MAC (Message Authentication Code). Two different
processes and therefore complex.
• Encrypt and Authenticate using a single procedure.
• Second method to obtain Authenticated Encryption is much better and widely used by
developers.
5. TIAOXIN-346
• Name of a design which provides the feature of Authenticated
Encryption.
• Designed by Ivica Nikolic of Nanyang Technological University,
Singapore.
• TIAOXIN-346 is one of the Entries of CAESAR, a worldwide
competition related to Encryption.
• HarSam, our project is the Hardware Implementation of TIAOXIN-
346.
7. TIAOXIN-346 Encryption
Inputs:
• Key, K of 128 bits
• Public Message Number- Nonce, IV of 128 bits
• Plaintext, M of 256 bits
• Associated Data, AD of 256 bits
Outputs:
• Ciphertext , C of 256 bits
• Tag of 128 bits
Tiaoxin - 346 (K; IV; M;D) = (C; Tag)
8. Notations and Operations Used
• Word- sequence of 16 bytes.
• Z0- is a constant word with value “428a2f98d728ae227137449123ef65cd”.
• Z1- is a constant word with value “b5c0fbcfec4d3b2fe9b5dba58189dbbc”.
• Ts- state composed of s word. For instance, T3 has 3 words, T4 has 4 words and
T6 has 6 words.
• X Y { bitwise addition (XOR) of the words X and Y}.
• X & Y { bitwise conjunction (AND) of the words X and Y}.
• AES(X; SK) – X is the word and SK is the sub key. AES is one round single of AES.
AES(X; SK) = MixColumns(ShiftRows(SubBytes(X))) + SK
• R(Ts;M) - a round transformation of a state with s words.
R: Ts X M -> Ts new
Further R(Ts;M) uses AES(X;SK) either in keyless mode or keyed mode.
9. UPDATE Function
Update : T3 X T4 X T6 X M0 X M1 X M2 -> T3 X T4 X T6.
T3 new = R(T3,M0); T3=T3 new
T4 new = R(T4,M1); T4=T4 new
T6 new = R(T6,M2); T6=T6 new
Keyed Mode of AES round uses Z0 as Sub Key
10. AES Operations
• STATE Matrix:
Input Data block viewed as 4-by-4 table of bytes.
• Filling Up of STATE Matrix:
1 byte
12. SubBytes: Byte Substitution Operation
• A simple substitution of each byte
• Uses one S-box of 16x16 bytes containing a permutation of all 256 8-bit
values
• Each byte of state is replaced by byte indexed by row (left 4-bits) &
column (right 4-bits)
– E.g. byte {75} is replaced by byte in row 7 column 5
– which has value {5B}
15. • Shifting, which permutes the bytes.
• A circular byte shift in each
– 1st row is unchanged
– 2nd row does 1 byte circular shift to left
– 3rd row does 2 bytes circular shift to left
– 4th row does 3 bytes circular shift to left
ShiftRow Operation
19. TIAOXIN-346 Encryption Processing
• TIAOXIN-346 Encryption Algorithm works in 4 stages and are as following
• Initialization
• Processing Associated Data
• Encryption
• Tag Production
• Above mentioned processes are executed in the same order as they are written.
Initialization --> Processing Associated Data --> Encryption --> Tag Production
20. INITIALIZATION
• In this stage, three states T3, T4 and T6 are loaded with the Inputs
K and IV.
• After fill up process, States T3, T4 and T6 are updated 15 times
using UPDATE function.
21. PROCESSING ASSOCIATED DATA
•The associated data AD is divided into blocks of 32 bytes each. If the last block of
AD is incomplete (the length of the block is less than 32 bytes), padding with
zeroes is done.
AD = AD1; . . . ;ADd
|ADi| = 256 and ADlength = |AD|
The length of the AD is encoded as 16-byte big endian word and stored
in ADlength.
For our design, we have d=1 because AD is of 256 bits in size.
22. ENCRYPTION
•The message M is divided into blocks of 32 bytes each. If the last block of M is
incomplete (the length of the block is less than 32 bytes), padding with zeroes is
done.
M = M1; . . . ; Md
|Mi| = 256 and Mlength = |M|
The length of the M is encoded as 16-byte big endian word and stored
in Mlength.
In our design, we have m=1 because of 256 bit length of M.
C would be equal to M in terms of length.
23. ENCRYPTION continued..
• In case padding with zeroes is done in last block of M, then last
block of C generated in the Encryption stage would undergo
Truncation.
• Suppose last block of M contains ‘b’ bytes then, last block of C
would be truncated after ‘b’ bytes. Therefore “32-b” bytes would
be removed from the last block of C.
• Complete Ciphertext is explained by the following equation:
C = C1|| C2 || . . . || Cm
|| is the Concatenation Operator here
24. Tag Production
This is the Final stage of the complete Encryption Algorithm.
In this step, words holding the length of AD and M are processed.
Firstly, UPDATE function uses ADlength and Mlength
Further, 20 rounds of UPDATE function are used with Z0 and Z1 and Tag is
generated by the XOR operation of all words of T3, T4 and T6
25. TIAOXIN-346 Decryption
• Inputs:
• Key, K of 128 bits
• Public Message Number- Nonce, IV of 128 bits
• Ciphertext, C of 256 bits
• Associated Data, AD of 256 bits
• Tag of 128 bits
• Outputs:
• Plaintext, M of 256 bits
• Fail, single bit in size
Tiaoxin - 346 (K; IV; C;AD,Tag) = (M; Fail)
26. TIAOXIN-346 Decryption Processing
•TIAOXIN-346 Encryption Algorithm works in 4 stages and are as following
• Initialization
• Processing Associated Data
• Decryption
• Tag Production
• Above mentioned processes are executed in the same order as they are
written.
Initialization --> Processing Associated Data --> Decryption --> Tag Production
• Initialization, Processing Associated Data and Finalization stages are exactly
similar to Encryption steps.
• Only the Decryption stage is altered.
27. DECRYPTION
Assuming C has m blocks of 32 bytes
C = C1|| C2 || . . . || Cm
In our design, m=1 and therefore above statements are executed only once.
Padding with zeroes is done similarly as done in Encryption.
If the Tag produced in Decryption is similar to the Input Tag, then only M is generated
at the Output and Fail is made to Logic low. Else Fail is made to Logic High and M
generated in Decryption Stage is not available at the Output port.
35. Modified Version of HarSam
As the comparison summarizes, our design is much
slower than the TIAOXIN-346.
But we have achieved Hardware Implementation.
In order to match the Timing characteristics of
TIAOXIN-346, we have modified our design and built a
newer design.
We have successfully Simulated the design but we
were not able to Synthesize the design due to lack of
our System resources.
38. FUTURE WORKS
• Try to achieve Hardware Implementation of Our
Modified design.
• Further work on to decrease Timing features so as
to take our design to be involved in some
applications.